281a792f2b
Updated the PCAP FSBL defines with driver definitions Signed-off-by: Krishna Chaitanya <kpataka@xilinx.com> Acked-by: Nirmala Pelluri <nirmala@xilinx.com>
690 lines
19 KiB
C
690 lines
19 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file pcap.c
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*
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* Contains code for enabling and accessing the PCAP
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a ecm 02/10/10 Initial release
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* 2.00a jz 05/28/11 Add SD support
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* 2.00a mb 25/05/12 using the EDK provided devcfg driver
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* Nand/SD encryption and review comments
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* 3.00a mb 16/08/12 Added the poll function
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* Removed the FPGA_RST_CTRL define
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* Added the flag for NON PS instantiated bitstream
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* 4.00a sgd 02/28/13 Fix for CR#681014 - ECC init in FSBL should not call
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* fabric_init()
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* Fix for CR#689026 - FSBL doesn't hold PL resets active
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* during bit download
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* Fix for CR#699475 - FSBL functionality is broken and
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* its not able to boot in QSPI/NAND
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* bootmode
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* Fix for CR#705664 - FSBL fails to decrypt the
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* bitstream when the image is AES
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* encrypted using non-zero key value
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* 6.00a kc 08/30/13 Fix for CR#722979 - Provide customer-friendly
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* changelogs in FSBL
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* 7.00a kc 10/25/13 Fix for CR#724620 - How to handle PCAP_MODE after
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* bitstream configuration
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* Fix for CR#726178 - FabricInit() PROG_B is kept active
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* for 5mS.
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* Fix for CR#731839 - FSBL has to check the
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* HMAC error status after decryption
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* 12/04/13 Fix for CR#764382 - How to handle PCAP_MODE after
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* bitstream configuration - PCAP_MODE
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* and PCAP_PR bits are not modified
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* 8.00a kc 2/20/14 Fix for CR#775631 - FSBL: FsblGetGlobalTimer()
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* is not proper
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* 10.00a kc 07/24/14 Fix for CR#809336 - Minor code cleanup
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* </pre>
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*
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* @note
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "pcap.h"
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#include "nand.h" /* For NAND geometry information */
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#include "fsbl.h"
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#include "image_mover.h" /* For MoveImage */
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#include "xparameters.h"
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#include "xil_exception.h"
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#include "xdevcfg.h"
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#include "sleep.h"
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#ifdef XPAR_XWDTPS_0_BASEADDR
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#include "xwdtps.h"
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#endif
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/************************** Constant Definitions *****************************/
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/*
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* The following constants map to the XPAR parameters created in the
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* xparameters.h file. They are only defined here such that a user can easily
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* change all the needed parameters in one place.
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*/
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#define DCFG_DEVICE_ID XPAR_XDCFG_0_DEVICE_ID
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Function Prototypes ******************************/
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extern int XDcfgPollDone(u32 MaskValue, u32 MaxCount);
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/************************** Variable Definitions *****************************/
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/* Devcfg driver instance */
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static XDcfg DcfgInstance;
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XDcfg *DcfgInstPtr;
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#ifdef XPAR_XWDTPS_0_BASEADDR
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extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
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#endif
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/******************************************************************************/
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/**
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*
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* This function transfer data using PCAP
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*
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* @param SourceDataPtr is a pointer to where the data is read from
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* @param DestinationDataPtr is a pointer to where the data is written to
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* @param SourceLength is the length of the data to be moved in words
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* @param DestinationLength is the length of the data to be moved in words
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* @param SecureTransfer indicated the encryption key location, 0 for
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* non-encrypted
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*
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* @return
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* - XST_SUCCESS if the transfer is successful
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* - XST_FAILURE if the transfer fails
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*
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* @note None
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*
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****************************************************************************/
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u32 PcapDataTransfer(u32 *SourceDataPtr, u32 *DestinationDataPtr,
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u32 SourceLength, u32 DestinationLength, u32 SecureTransfer)
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{
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u32 Status;
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u32 IntrStsReg;
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u32 PcapTransferType = XDCFG_CONCURRENT_NONSEC_READ_WRITE;
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/*
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* Check for secure transfer
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*/
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if (SecureTransfer) {
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PcapTransferType = XDCFG_CONCURRENT_SECURE_READ_WRITE;
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}
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#ifdef FSBL_PERF
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XTime tXferCur = 0;
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FsblGetGlobalTime(&tXferCur);
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#endif
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/*
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* Clear the PCAP status registers
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*/
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Status = ClearPcapStatus();
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if (Status != XST_SUCCESS) {
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fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n");
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return XST_FAILURE;
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}
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#ifdef XPAR_XWDTPS_0_BASEADDR
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/*
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* Prevent WDT reset
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*/
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XWdtPs_RestartWdt(&Watchdog);
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#endif
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/*
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* PCAP single DMA transfer setup
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*/
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SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER);
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DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER);
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/*
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* Transfer using Device Configuration
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*/
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Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr,
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SourceLength,
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(u8 *)DestinationDataPtr,
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DestinationLength, PcapTransferType);
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if (Status != XST_SUCCESS) {
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fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %d \r \n",Status);
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return XST_FAILURE;
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}
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/*
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* Dump the PCAP registers
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*/
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PcapDumpRegisters();
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/*
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* Poll for the DMA done
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*/
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Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT);
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if (Status != XST_SUCCESS) {
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fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n");
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return XST_FAILURE;
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}
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fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r");
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/*
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* Check for errors
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*/
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IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
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if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
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fsbl_printf(DEBUG_INFO,"Errors in PCAP \r\n");
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return XST_FAILURE;
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}
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/*
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* For Performance measurement
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*/
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#ifdef FSBL_PERF
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XTime tXferEnd = 0;
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fsbl_printf(DEBUG_GENERAL,"Time taken is ");
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FsblMeasurePerfTime(tXferCur,tXferEnd);
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#endif
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return XST_SUCCESS;
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}
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/******************************************************************************/
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/**
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*
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* This function loads PL partition using PCAP
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*
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* @param SourceDataPtr is a pointer to where the data is read from
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* @param DestinationDataPtr is a pointer to where the data is written to
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* @param SourceLength is the length of the data to be moved in words
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* @param DestinationLength is the length of the data to be moved in words
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* @param SecureTransfer indicated the encryption key location, 0 for
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* non-encrypted
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*
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* @return
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* - XST_SUCCESS if the transfer is successful
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* - XST_FAILURE if the transfer fails
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*
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* @note None
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*
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****************************************************************************/
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u32 PcapLoadPartition(u32 *SourceDataPtr, u32 *DestinationDataPtr,
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u32 SourceLength, u32 DestinationLength, u32 SecureTransfer)
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{
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u32 Status;
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u32 IntrStsReg;
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u32 PcapTransferType = XDCFG_NON_SECURE_PCAP_WRITE;
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/*
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* Check for secure transfer
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*/
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if (SecureTransfer) {
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PcapTransferType = XDCFG_SECURE_PCAP_WRITE;
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}
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#ifdef FSBL_PERF
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XTime tXferCur = 0;
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FsblGetGlobalTime(&tXferCur);
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#endif
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/*
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* Clear the PCAP status registers
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*/
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Status = ClearPcapStatus();
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if (Status != XST_SUCCESS) {
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fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n");
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return XST_FAILURE;
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}
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/*
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* For Bitstream case destination address will be 0xFFFFFFFF
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*/
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DestinationDataPtr = (u32*)XDCFG_DMA_INVALID_ADDRESS;
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/*
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* New Bitstream download initialization sequence
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*/
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FabricInit();
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#ifdef XPAR_XWDTPS_0_BASEADDR
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/*
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* Prevent WDT reset
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*/
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XWdtPs_RestartWdt(&Watchdog);
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#endif
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/*
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* PCAP single DMA transfer setup
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*/
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SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER);
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DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER);
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/*
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* Transfer using Device Configuration
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*/
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Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr,
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SourceLength,
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(u8 *)DestinationDataPtr,
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DestinationLength, PcapTransferType);
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if (Status != XST_SUCCESS) {
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fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %d \r \n",Status);
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return XST_FAILURE;
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}
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/*
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* Dump the PCAP registers
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*/
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PcapDumpRegisters();
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/*
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* Poll for the DMA done
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*/
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Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT);
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if (Status != XST_SUCCESS) {
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fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n");
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return XST_FAILURE;
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}
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fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r");
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/*
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* Poll for FPGA Done
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*/
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Status = XDcfgPollDone(XDCFG_IXR_PCFG_DONE_MASK, MAX_COUNT);
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if (Status != XST_SUCCESS) {
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fsbl_printf(DEBUG_INFO,"PCAP_FPGA_DONE_FAIL\r\n");
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return XST_FAILURE;
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}
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fsbl_printf(DEBUG_INFO,"FPGA Done ! \n\r");
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/*
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* Check for errors
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*/
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IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
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if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
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fsbl_printf(DEBUG_INFO,"Errors in PCAP \r\n");
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return XST_FAILURE;
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}
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/*
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* For Performance measurement
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*/
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#ifdef FSBL_PERF
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XTime tXferEnd = 0;
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fsbl_printf(DEBUG_GENERAL,"Time taken is ");
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FsblMeasurePerfTime(tXferCur,tXferEnd);
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#endif
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return XST_SUCCESS;
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}
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/******************************************************************************/
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/**
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*
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* This function Initializes the PCAP driver.
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*
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* @param none
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*
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* @return
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* - XST_SUCCESS if the pcap driver initialization is successful
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* - XST_FAILURE if the pcap driver initialization fails
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*
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* @note none
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*
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****************************************************************************/
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int InitPcap(void)
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{
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XDcfg_Config *ConfigPtr;
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int Status = XST_SUCCESS;
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DcfgInstPtr = &DcfgInstance;
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/*
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* Initialize the Device Configuration Interface driver.
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*/
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ConfigPtr = XDcfg_LookupConfig(DCFG_DEVICE_ID);
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Status = XDcfg_CfgInitialize(DcfgInstPtr, ConfigPtr,
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ConfigPtr->BaseAddr);
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if (Status != XST_SUCCESS) {
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fsbl_printf(DEBUG_INFO, "XDcfg_CfgInitialize failed \n\r");
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return XST_FAILURE;
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}
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return XST_SUCCESS;
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}
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/******************************************************************************/
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/**
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*
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* This function programs the Fabric for use.
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*
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* @param None
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*
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* @return None
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* - XST_SUCCESS if the Fabric initialization is successful
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* - XST_FAILURE if the Fabric initialization fails
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* @note None
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*
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****************************************************************************/
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void FabricInit(void)
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{
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u32 PcapReg;
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u32 PcapCtrlRegVal;
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u32 StatusReg;
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/*
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* Set Level Shifters DT618760 - PS to PL enabling
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*/
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Xil_Out32(PS_LVL_SHFTR_EN, LVL_PS_PL);
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fsbl_printf(DEBUG_INFO,"Level Shifter Value = 0x%x \r\n",
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Xil_In32(PS_LVL_SHFTR_EN));
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/*
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* Get DEVCFG controller settings
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*/
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PcapReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
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XDCFG_CTRL_OFFSET);
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/*
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* Setting PCFG_PROG_B signal to high
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*/
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XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
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(PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
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/*
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* Check for AES source key
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*/
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PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr);
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if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
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/*
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* 5msec delay
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*/
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usleep(5000);
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}
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/*
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* Setting PCFG_PROG_B signal to low
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*/
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XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
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(PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK));
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/*
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* Check for AES source key
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*/
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if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
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/*
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* 5msec delay
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*/
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usleep(5000);
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}
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/*
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* Polling the PCAP_INIT status for Reset
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*/
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while(XDcfg_GetStatusRegister(DcfgInstPtr) &
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XDCFG_STATUS_PCFG_INIT_MASK);
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/*
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* Setting PCFG_PROG_B signal to high
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*/
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XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
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(PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
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/*
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* Polling the PCAP_INIT status for Set
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*/
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while(!(XDcfg_GetStatusRegister(DcfgInstPtr) &
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XDCFG_STATUS_PCFG_INIT_MASK));
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/*
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* Get Device configuration status
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*/
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StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
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fsbl_printf(DEBUG_INFO,"Devcfg Status register = 0x%x \r\n",StatusReg);
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fsbl_printf(DEBUG_INFO,"PCAP:Fabric is Initialized done\r\n");
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}
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/******************************************************************************/
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/**
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*
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* This function Clears the PCAP status registers.
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*
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* @param None
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*
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* @return
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* - XST_SUCCESS if the pcap status registers are cleared
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* - XST_FAILURE if errors are there
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* - XST_DEVICE_BUSY if Pcap device is busy
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* @note None
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*
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****************************************************************************/
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u32 ClearPcapStatus(void)
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{
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u32 StatusReg;
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u32 IntStatusReg;
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/*
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* Clear it all, so if Boot ROM comes back, it can proceed
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*/
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XDcfg_IntrClear(DcfgInstPtr, 0xFFFFFFFF);
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/*
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* Get PCAP Interrupt Status Register
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*/
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IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
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if (IntStatusReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
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fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %x\r\n",
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IntStatusReg);
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return XST_FAILURE;
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}
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/*
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* Read the PCAP status register for DMA status
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*/
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StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
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fsbl_printf(DEBUG_INFO,"PCAP:StatusReg = 0x%.8x\r\n", StatusReg);
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/*
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* If the queue is full, return w/ XST_DEVICE_BUSY
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*/
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if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
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XDCFG_STATUS_DMA_CMD_Q_F_MASK) {
|
|
|
|
fsbl_printf(DEBUG_INFO,"PCAP_DEVICE_BUSY\r\n");
|
|
return XST_DEVICE_BUSY;
|
|
}
|
|
|
|
fsbl_printf(DEBUG_INFO,"PCAP:device ready\r\n");
|
|
|
|
/*
|
|
* There are unacknowledged DMA commands outstanding
|
|
*/
|
|
if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_E_MASK) !=
|
|
XDCFG_STATUS_DMA_CMD_Q_E_MASK) {
|
|
|
|
IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
|
|
|
|
if ((IntStatusReg & XDCFG_IXR_DMA_DONE_MASK) !=
|
|
XDCFG_IXR_DMA_DONE_MASK){
|
|
/*
|
|
* Error state, transfer cannot occur
|
|
*/
|
|
fsbl_printf(DEBUG_INFO,"PCAP:IntStatus indicates error\r\n");
|
|
return XST_FAILURE;
|
|
}
|
|
else {
|
|
/*
|
|
* clear out the status
|
|
*/
|
|
XDcfg_IntrClear(DcfgInstPtr, XDCFG_IXR_DMA_DONE_MASK);
|
|
}
|
|
}
|
|
|
|
if ((StatusReg & XDCFG_STATUS_DMA_DONE_CNT_MASK) != 0) {
|
|
XDcfg_IntrClear(DcfgInstPtr, StatusReg &
|
|
XDCFG_STATUS_DMA_DONE_CNT_MASK);
|
|
}
|
|
|
|
fsbl_printf(DEBUG_INFO,"PCAP:Clear done\r\n");
|
|
|
|
return XST_SUCCESS;
|
|
}
|
|
|
|
/******************************************************************************/
|
|
/**
|
|
*
|
|
* This function prints PCAP register status.
|
|
*
|
|
* @param none
|
|
*
|
|
* @return none
|
|
*
|
|
* @note none
|
|
*
|
|
****************************************************************************/
|
|
void PcapDumpRegisters (void) {
|
|
|
|
fsbl_printf(DEBUG_INFO,"PCAP register dump:\r\n");
|
|
|
|
fsbl_printf(DEBUG_INFO,"PCAP CTRL 0x%x: 0x%08x\r\n",
|
|
XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET,
|
|
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET));
|
|
fsbl_printf(DEBUG_INFO,"PCAP LOCK 0x%x: 0x%08x\r\n",
|
|
XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET,
|
|
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET));
|
|
fsbl_printf(DEBUG_INFO,"PCAP CONFIG 0x%x: 0x%08x\r\n",
|
|
XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET,
|
|
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET));
|
|
fsbl_printf(DEBUG_INFO,"PCAP ISR 0x%x: 0x%08x\r\n",
|
|
XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET,
|
|
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET));
|
|
fsbl_printf(DEBUG_INFO,"PCAP IMR 0x%x: 0x%08x\r\n",
|
|
XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET,
|
|
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET));
|
|
fsbl_printf(DEBUG_INFO,"PCAP STATUS 0x%x: 0x%08x\r\n",
|
|
XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET,
|
|
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET));
|
|
fsbl_printf(DEBUG_INFO,"PCAP DMA SRC ADDR 0x%x: 0x%08x\r\n",
|
|
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET,
|
|
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET));
|
|
fsbl_printf(DEBUG_INFO,"PCAP DMA DEST ADDR 0x%x: 0x%08x\r\n",
|
|
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET,
|
|
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET));
|
|
fsbl_printf(DEBUG_INFO,"PCAP DMA SRC LEN 0x%x: 0x%08x\r\n",
|
|
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET,
|
|
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET));
|
|
fsbl_printf(DEBUG_INFO,"PCAP DMA DEST LEN 0x%x: 0x%08x\r\n",
|
|
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET,
|
|
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET));
|
|
fsbl_printf(DEBUG_INFO,"PCAP ROM SHADOW CTRL 0x%x: 0x%08x\r\n",
|
|
XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET,
|
|
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET));
|
|
fsbl_printf(DEBUG_INFO,"PCAP MBOOT 0x%x: 0x%08x\r\n",
|
|
XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET,
|
|
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET));
|
|
fsbl_printf(DEBUG_INFO,"PCAP SW ID 0x%x: 0x%08x\r\n",
|
|
XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET,
|
|
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET));
|
|
fsbl_printf(DEBUG_INFO,"PCAP UNLOCK 0x%x: 0x%08x\r\n",
|
|
XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET,
|
|
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET));
|
|
fsbl_printf(DEBUG_INFO,"PCAP MCTRL 0x%x: 0x%08x\r\n",
|
|
XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET,
|
|
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET));
|
|
}
|
|
|
|
/******************************************************************************/
|
|
/**
|
|
*
|
|
* This function Polls for the DMA done or FPGA done.
|
|
*
|
|
* @param none
|
|
*
|
|
* @return
|
|
* - XST_SUCCESS if polling for DMA/FPGA done is successful
|
|
* - XST_FAILURE if polling for DMA/FPGA done fails
|
|
*
|
|
* @note none
|
|
*
|
|
****************************************************************************/
|
|
int XDcfgPollDone(u32 MaskValue, u32 MaxCount)
|
|
{
|
|
int Count = MaxCount;
|
|
u32 IntrStsReg = 0;
|
|
|
|
/*
|
|
* poll for the DMA done
|
|
*/
|
|
IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
|
|
while ((IntrStsReg & MaskValue) !=
|
|
MaskValue) {
|
|
IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
|
|
Count -=1;
|
|
|
|
if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
|
|
fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %x\r\n",
|
|
IntrStsReg);
|
|
PcapDumpRegisters();
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
if(!Count) {
|
|
fsbl_printf(DEBUG_GENERAL,"PCAP transfer timed out \r\n");
|
|
return XST_FAILURE;
|
|
}
|
|
if (Count > (MAX_COUNT-100)) {
|
|
fsbl_printf(DEBUG_GENERAL,".");
|
|
}
|
|
}
|
|
|
|
fsbl_printf(DEBUG_GENERAL,"\n\r");
|
|
|
|
XDcfg_IntrClear(DcfgInstPtr, IntrStsReg & MaskValue);
|
|
|
|
return XST_SUCCESS;
|
|
}
|