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Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
414 lines
15 KiB
C
414 lines
15 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* The CSU_DMA is present inside CSU (Configuration Security Unit) module which
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* is located within the Low-Power Subsystem (LPS) internal to the PS.
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* CSU_DMA allows the CSU to move data efficiently between the memory (32 bit
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* AXI interface) and the CSU stream peripherals (SHA, AES and PCAP) via Secure
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* Stream Switch (SSS).
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*
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* The CSU_DMA is a 2 channel simple DMA, allowing separate control of the SRC
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* (read) channel and DST (write) channel. The DMA is effectively able to
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* transfer data:
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* - From PS-side to the SSS-side (SRC DMA only)
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* - From SSS-side to the PS-side (DST DMA only)
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* - Simultaneous PS-side to SSS_side and SSS-side to the PS-side
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*
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* <b>Initialization & Configuration</b>
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*
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* The device driver enables higher layer software (e.g., an application) to
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* communicate to the CSU_DMA core.
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*
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* XCsuDma_CfgInitialize() API is used to initialize the CSU_DMA core.
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* The user needs to first call the XCsuDma_LookupConfig() API which returns
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* the Configuration structure pointer which is passed as a parameter to the
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* XCsuDma_CfgInitialize() API.
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*
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* <b> Interrupts </b>
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* This driver will not support handling of interrupts user should write handler
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* to handle the interrupts.
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*
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* <b> Virtual Memory </b>
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*
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* This driver supports Virtual Memory. The RTOS is responsible for calculating
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* the correct device base address in Virtual Memory space.
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*
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* <b> Threads </b>
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*
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* This driver is not thread safe. Any needs for threads or thread mutual
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* exclusion must be satisfied by the layer above this driver.
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*
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* <b> Asserts </b>
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*
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* Asserts are used within all Xilinx drivers to enforce constraints on argument
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* values. Asserts can be turned off on a system-wide basis by defining, at
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* compile time, the NDEBUG identifier. By default, asserts are turned on and it
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* is recommended that users leave asserts on during development.
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*
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* <b> Building the driver </b>
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*
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* The XCsuDma driver is composed of several source files. This allows the user
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* to build and link only those parts of the driver that are necessary.
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*
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* @file xcsudma.h
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*
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* This header file contains identifiers and register-level driver functions (or
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* macros), range macros, structure typedefs that can be used to access the
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* Xilinx CSU_DMA core instance.
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*
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ------ -------- -----------------------------------------------------
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* 1.0 vnsld 22/10/14 First release
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* </pre>
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*
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******************************************************************************/
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#ifndef XCSUDMA_H_
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#define XCSUDMA_H_ /**< Prevent circular inclusions
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* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xcsudma_hw.h"
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xstatus.h"
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#include "xil_cache.h"
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/************************** Constant Definitions *****************************/
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/** @name CSU_DMA Channels
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* @{
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*/
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typedef enum {
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XCSUDMA_SRC_CHANNEL = 0U, /**< Source Channel of CSU_DMA */
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XCSUDMA_DST_CHANNEL /**< Destination Channel of CSU_DMA */
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}XCsuDma_Channel;
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/*@}*/
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/** @name CSU_DMA pause types
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* @{
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*/
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typedef enum {
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XCSUDMA_PAUSE_MEMORY, /**< Pauses memory data transfer
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* to/from CSU_DMA */
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XCSUDMA_PAUSE_STREAM, /**< Pauses stream data transfer
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* to/from CSU_DMA */
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}XCsuDma_PauseType;
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/*@}*/
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/** @name Ranges of Size
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* @{
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*/
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#define XCSUDMA_SIZE_MAX 0x07FFFFFF /**< Maximum allowed no of words */
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/*@}*/
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/***************** Macros (Inline Functions) Definitions *********************/
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/*****************************************************************************/
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/**
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*
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* This function resets the CSU_DMA core.
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*
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* @param None.
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*
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* @return None.
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*
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* @note None.
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* C-style signature:
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* void XCsuDma_Reset()
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*
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******************************************************************************/
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#define XCsuDma_Reset() \
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Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \
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(u32)(XCSUDMA_RESET_SET_MASK)); \
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Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \
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(u32)(XCSUDMA_RESET_UNSET_MASK));
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/*****************************************************************************/
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/**
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* This function will be in busy while loop until the data transfer is
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* completed.
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*
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* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
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* @param Channel represents the type of channel either it is Source or
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* Destination.
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* Source channel - XCSUDMA_SRC_CHANNEL
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* Destination Channel - XCSUDMA_DST_CHANNEL
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*
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* @return None.
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*
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* @note This function should be called after XCsuDma_Transfer in polled
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* mode to wait until the data gets transfered completely.
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* C-style signature:
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* void XCsuDma_WaitForDone(XCsuDma *InstancePtr,
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* XCsuDma_Channel Channel)
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*
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******************************************************************************/
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#define XCsuDma_WaitForDone(InstancePtr,Channel) \
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while((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
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((u32)(XCSUDMA_I_STS_OFFSET) + \
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((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
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(u32)(XCSUDMA_IXR_DONE_MASK)) != (XCSUDMA_IXR_DONE_MASK))
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/*****************************************************************************/
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/**
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*
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* This function returns the number of completed SRC/DST DMA transfers that
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* have not been acknowledged by software based on the channel selection.
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*
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* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
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* @param Channel represents the type of channel either it is Source or
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* Destination.
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* Source channel - XCSUDMA_SRC_CHANNEL
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* Destination Channel - XCSUDMA_DST_CHANNEL
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*
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* @return Count is number of completed DMA transfers but not acknowledged
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* (Range is 0 to 7).
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* - 000 - All finished transfers have been acknowledged.
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* - Count - Count number of finished transfers are still
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* outstanding.
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*
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* @note None.
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* C-style signature:
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* u8 XCsuDma_GetDoneCount(XCsuDma *InstancePtr,
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* XCsuDma_Channel Channel)
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*
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******************************************************************************/
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#define XCsuDma_GetDoneCount(InstancePtr, Channel) \
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((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
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((u32)(XCSUDMA_STS_OFFSET) + \
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((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
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(u32)(XCSUDMA_STS_DONE_CNT_MASK)) >> \
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(u32)(XCSUDMA_STS_DONE_CNT_SHIFT))
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/*****************************************************************************/
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/**
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*
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* This function returns the current SRC/DST FIFO level in 32 bit words of the
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* selected channel
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* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
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* @param Channel represents the type of channel either it is Source or
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* Destination.
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* Source channel - XCSUDMA_SRC_CHANNEL
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* Destination Channel - XCSUDMA_DST_CHANNEL
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*
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* @return FIFO level. (Range is 0 to 128)
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* - 0 Indicates empty
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* - Any number 1 to 128 indicates the number of entries in FIFO.
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*
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* @note None.
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* C-style signature:
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* u8 XCsuDma_GetFIFOLevel(XCsuDma *InstancePtr,
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* XCsuDma_Channel Channel)
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*
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******************************************************************************/
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#define XCsuDma_GetFIFOLevel(InstancePtr, Channel) \
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((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
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((u32)(XCSUDMA_STS_OFFSET) + \
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((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
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(u32)(XCSUDMA_STS_FIFO_LEVEL_MASK)) >> \
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(u32)(XCSUDMA_STS_FIFO_LEVEL_SHIFT))
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/*****************************************************************************/
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/**
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*
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* This function returns the current number of read(src)/write(dst) outstanding
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* commands based on the type of channel selected.
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*
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* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
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* @param Channel represents the type of channel either it is Source or
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* Destination.
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* Source channel - XCSUDMA_SRC_CHANNEL
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* Destination Channel - XCSUDMA_DST_CHANNEL
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*
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* @return Count of outstanding commands. (Range is 0 to 9).
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*
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* @note None.
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* C-style signature:
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* u8 XCsuDma_GetWROutstandCount(XCsuDma *InstancePtr,
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* XCsuDma_Channel Channel)
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*
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******************************************************************************/
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#define XCsuDma_GetWROutstandCount(InstancePtr, Channel) \
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((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
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((u32)(XCSUDMA_STS_OFFSET) + \
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((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
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(u32)(XCUSDMA_STS_OUTSTDG_MASK)) >> \
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(u32)(XCUSDMA_STS_OUTSTDG_SHIFT))
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/*****************************************************************************/
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/**
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*
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* This function returns the status of Channel either it is busy or not.
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*
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* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
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* @param Channel represents the type of channel either it is Source or
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* Destination.
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* Source channel - XCSUDMA_SRC_CHANNEL
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* Destination Channel - XCSUDMA_DST_CHANNEL
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*
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* @return Returns the current status of the core.
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* - TRUE represents core is currently busy.
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* - FALSE represents core is not involved in any transfers.
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*
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* @note None.
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* C-style signature:
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* s32 XCsuDma_IsBusy(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
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*
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******************************************************************************/
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#define XCsuDma_IsBusy(InstancePtr, Channel) \
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((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
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((u32)(XCSUDMA_STS_OFFSET) + \
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((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
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(u32)(XCSUDMA_STS_BUSY_MASK)) == (XCSUDMA_STS_BUSY_MASK)) ? \
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(TRUE) : (FALSE)
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/**************************** Type Definitions *******************************/
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/**
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* This typedef contains configuration information for a CSU_DMA core.
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* Each CSU_DMA core should have a configuration structure associated.
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*/
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typedef struct {
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u16 DeviceId; /**< DeviceId is the unique ID of the
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* device */
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u32 BaseAddress; /**< BaseAddress is the physical base address
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* of the device's registers */
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} XCsuDma_Config;
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/******************************************************************************/
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/**
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*
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* The XCsuDma driver instance data structure. A pointer to an instance data
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* structure is passed around by functions to refer to a specific driver
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* instance.
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*/
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typedef struct {
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XCsuDma_Config Config; /**< Hardware configuration */
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u32 IsReady; /**< Device and the driver instance
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* are initialized */
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}XCsuDma;
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/******************************************************************************/
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/**
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* This typedef contains all the configuration feilds which needs to be set
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* before the start of the data transfer. All these feilds of CSU_DMA can be
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* configured by using XCsuDma_SetConfig API.
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*/
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typedef struct {
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u8 SssFifoThesh; /**< SSS FIFO threshold value */
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u8 ApbErr; /**< ABP invalid access error */
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u8 EndianType; /**< Type of endianess */
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u8 AxiBurstType; /**< Type of AXI bus */
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u32 TimeoutValue; /**< Time out value */
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u8 FifoThresh; /**< FIFO threshold value */
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u8 Acache; /**< AXI CACHE selection */
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u8 RouteBit; /**< Selection of Route */
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u8 TimeoutEn; /**< Enable of time out counters */
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u16 TimeoutPre; /**< Pre scaler value */
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u8 MaxOutCmds; /**< Maximum number of outstanding
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* commands */
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}XCsuDma_Configure;
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/*****************************************************************************/
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/************************** Function Prototypes ******************************/
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XCsuDma_Config *XCsuDma_LookupConfig(u16 DeviceId);
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s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr,
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u32 EffectiveAddr);
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void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
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u64 Addr, u32 Size, u8 EnDataLast);
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void XCsuDma_LoopBackTransfer(XCsuDma *InstancePtr, u64 SrcAddr, u64 DstAddr,
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u32 Size);
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u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
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u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
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void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
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XCsuDma_PauseType Type);
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s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
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XCsuDma_PauseType Type);
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void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
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XCsuDma_PauseType Type);
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u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr);
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void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr);
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void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
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XCsuDma_Configure *ConfigurValues);
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void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
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XCsuDma_Configure *ConfigurValues);
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void XCsuDma_ClearDoneCount(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
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void XCsuDma_SetSafetyCheck(XCsuDma *InstancePtr, u32 Value);
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u32 XCsuDma_GetSafetyCheck(XCsuDma *InstancePtr);
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/* Interrupt related APIs */
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u32 XCsuDma_IntrGetStatus(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
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void XCsuDma_IntrClear(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
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u32 Mask);
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void XCsuDma_EnableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
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u32 Mask);
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void XCsuDma_DisableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
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u32 Mask);
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u32 XCsuDma_GetIntrMask(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
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s32 XCsuDma_SelfTest(XCsuDma *InstancePtr);
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/******************************************************************************/
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#ifdef __cplusplus
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}
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#endif
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#endif /* End of protection macro */
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