ae31a85612
Upgrade and make misra c compliant Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
628 lines
31 KiB
C
Executable file
628 lines
31 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xemacps_hw.h
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*
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* This header file contains identifiers and low-level driver functions (or
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* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
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* High-level driver functions are defined in xemacps.h.
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*
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* @note
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a wsy 01/10/10 First release.
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* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
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* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
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* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
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* to 0x1fff. This fixes the CR#744902.
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* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
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* </pre>
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*
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******************************************************************************/
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#ifndef XEMACPS_HW_H /* prevent circular inclusions */
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#define XEMACPS_HW_H /* by using protection macros */
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xil_io.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/************************** Constant Definitions *****************************/
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#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
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supported */
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#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
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#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
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on the local bus */
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#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
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options that impose alignment
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restrictions on the buffer data on
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the local bus */
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/** @name Direction identifiers
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*
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* These are used by several functions and callbacks that need
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* to specify whether an operation specifies a send or receive channel.
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* @{
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*/
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#define XEMACPS_SEND 1U /**< send direction */
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#define XEMACPS_RECV 2U /**< receive direction */
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/*@}*/
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/** @name MDC clock division
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* currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
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* @{
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*/
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typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
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MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
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} XEmacPs_MdcDiv;
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/*@}*/
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#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
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bytes, 64, 128, ... 10240 */
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#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
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unit, this is HW setup */
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#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
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#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
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#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
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/* Register offset definitions. Unless otherwise noted, register access is
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* 32 bit. Names are self explained here.
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*/
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#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
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#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
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#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
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#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
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#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
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#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
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#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
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#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
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#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
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#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
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#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
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#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
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#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
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#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
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#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
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#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
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#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
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#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
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#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
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#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
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#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
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#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
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#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
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#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
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#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
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#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
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#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
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#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
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#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
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#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
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#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
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reg */
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#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
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reg */
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#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
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transmitted counter */
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#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
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Frames counter*/
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#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
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Frame counter */
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#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
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Counter */
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#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
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Transmitted counter */
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#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
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Frames Transmitted
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counter */
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#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
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Frames Transmitted
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counter*/
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#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
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Frames transmitted
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counter */
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#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
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Frames transmitted
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counter */
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#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
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Frames transmitted
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counter */
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#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
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1519 byte Frames
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transmitted counter */
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#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
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counter */
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#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
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Counter */
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#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
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Counter */
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#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
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Counter */
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#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
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Counter */
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#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
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Frame Counter */
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#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
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Error Counter */
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#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
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Low */
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#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
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High */
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#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
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Received Counter */
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#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
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Frames Received Counter */
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#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
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Frames Received Counter */
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#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
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Received Counter */
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#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
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Received Counter */
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#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
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Frames Received Counter */
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#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
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Frames Received Counter */
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#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
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Frames Received Counter */
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#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
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Frames Received Counter */
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#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
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Frames Received Counter */
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#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
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Frames Received Counter */
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#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
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Counter */
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#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
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Counter */
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#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
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Counter */
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#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
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Error Counter */
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#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
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Counter */
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#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
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#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
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#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
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Counter */
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#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
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#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
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Counter */
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#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
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Counter */
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#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
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Counter */
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#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
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offset, for clearing */
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#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
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#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
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#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
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adjustment counter */
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#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
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increment counter */
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#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
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counter */
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#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
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nanosecond counter */
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#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
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counter */
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#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
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nanosecond counter */
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#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
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second counter */
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#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
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nanosecond counter */
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#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
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second counter */
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#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
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nanosecond counter */
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#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
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reg */
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#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
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reg */
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#define XEMACPS_MSBBUF_QBASE_OFFSET 0x000004C8U /**< MSB Buffer Q Base
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reg */
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#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
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reg */
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#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
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reg */
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#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
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reg */
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/* Define some bit positions for registers. */
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/** @name network control register bit definitions
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* @{
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*/
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#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
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Rx SRAM */
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#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
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pause frame */
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#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
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#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
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after current frame */
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#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
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#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
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stat counters */
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#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
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registers */
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#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
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registers */
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#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
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#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
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#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
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#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
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/*@}*/
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/** @name network configuration register bit definitions
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* @{
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*/
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#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
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non-standard preamble */
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#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
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#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
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FCS error */
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#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
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#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
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offload */
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#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
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Frames to memory */
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#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
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#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
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#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
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#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
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received frames */
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#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
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/**< RX length error discard */
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#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
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#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
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#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
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#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
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/**< External address match enable */
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#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
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#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
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frames reception */
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#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
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frames */
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#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
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frames */
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#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
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broadcast frames */
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#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
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#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
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#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
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frames */
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#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
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#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
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#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
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/*@}*/
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/** @name network status register bit definitaions
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* @{
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*/
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#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
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#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
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/*@}*/
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/** @name MAC address register word 1 mask
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* @{
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*/
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#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
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bit[31:0] are in BOTTOM */
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/*@}*/
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/** @name DMA control register bit definitions
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* @{
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*/
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#define XEMACPS_DMACR_TXEXTEND_MASK 0x02000000U /**< Tx Extended desc mode */
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#define XEMACPS_DMACR_RXEXTEND_MASK 0x01000000U /**< Rx Extended desc mode */
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#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
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size */
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#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
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size */
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#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
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checksum offload */
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#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
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#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
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#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
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#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
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#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
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#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
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#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
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#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
|
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/*@}*/
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|
|
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/** @name transmit status register bit definitions
|
|
* @{
|
|
*/
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|
#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
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#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
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|
#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
|
|
#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
|
|
mid frame */
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|
#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
|
|
#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
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|
#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
|
|
#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
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|
|
|
#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
|
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(u32)XEMACPS_TXSR_URUN_MASK | \
|
|
(u32)XEMACPS_TXSR_BUFEXH_MASK | \
|
|
(u32)XEMACPS_TXSR_RXOVR_MASK | \
|
|
(u32)XEMACPS_TXSR_FRAMERX_MASK | \
|
|
(u32)XEMACPS_TXSR_USEDREAD_MASK)
|
|
/*@}*/
|
|
|
|
/**
|
|
* @name receive status register bit definitions
|
|
* @{
|
|
*/
|
|
#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
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#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
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|
#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
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#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
|
|
|
|
#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
|
|
(u32)XEMACPS_RXSR_RXOVR_MASK | \
|
|
(u32)XEMACPS_RXSR_BUFFNA_MASK)
|
|
/*@}*/
|
|
|
|
/**
|
|
* @name Interrupt Q1 status register bit definitions
|
|
* @{
|
|
*/
|
|
#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
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|
#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
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|
|
|
#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
|
|
(u32)XEMACPS_INTQ1SR_TXERR_MASK)
|
|
|
|
/*@}*/
|
|
|
|
/**
|
|
* @name interrupts bit definitions
|
|
* Bits definitions are same in XEMACPS_ISR_OFFSET,
|
|
* XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
|
|
* @{
|
|
*/
|
|
#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Psync transmitted */
|
|
#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req
|
|
transmitted */
|
|
#define XEMACPS_IXR_PTPSTX_MASK 0x00800000U /**< PTP Sync transmitted */
|
|
#define XEMACPS_IXR_PTPDRTX_MASK 0x00400000U /**< PTP Delay_req transmitted
|
|
*/
|
|
#define XEMACPS_IXR_PTPPSRX_MASK 0x00200000U /**< PTP Psync received */
|
|
#define XEMACPS_IXR_PTPPDRRX_MASK 0x00100000U /**< PTP Pdelay_req received */
|
|
#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync received */
|
|
#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req received */
|
|
#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
|
|
#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
|
|
zero */
|
|
#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
|
|
#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
|
|
#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
|
|
#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
|
|
#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
|
|
no buffers*/
|
|
#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
|
|
#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
|
|
#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
|
|
#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
|
|
#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
|
|
#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
|
|
#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
|
|
|
|
#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
|
|
(u32)XEMACPS_IXR_RETRY_MASK | \
|
|
(u32)XEMACPS_IXR_URUN_MASK | \
|
|
(u32)XEMACPS_IXR_TXUSED_MASK)
|
|
|
|
|
|
#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
|
|
(u32)XEMACPS_IXR_RXUSED_MASK | \
|
|
(u32)XEMACPS_IXR_RXOVR_MASK)
|
|
|
|
/*@}*/
|
|
|
|
/** @name PHY Maintenance bit definitions
|
|
* @{
|
|
*/
|
|
#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
|
|
#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
|
|
#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
|
|
#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
|
|
#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
|
|
#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
|
|
#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
|
|
#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
|
|
/*@}*/
|
|
|
|
/* Transmit buffer descriptor status words offset
|
|
* @{
|
|
*/
|
|
#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
|
|
#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
|
|
#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
|
|
|
|
/*
|
|
* @}
|
|
*/
|
|
|
|
/* Transmit buffer descriptor status words bit positions.
|
|
* Transmit buffer descriptor consists of two 32-bit registers,
|
|
* the first - word0 contains a 32-bit address pointing to the location of
|
|
* the transmit data.
|
|
* The following register - word1, consists of various information to control
|
|
* the XEmacPs transmit process. After transmit, this is updated with status
|
|
* information, whether the frame was transmitted OK or why it had failed.
|
|
* @{
|
|
*/
|
|
#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
|
|
#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
|
|
#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
|
|
#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
|
|
#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
|
|
#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
|
|
#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
|
|
#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
|
|
#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
|
|
/*
|
|
* @}
|
|
*/
|
|
|
|
/* Receive buffer descriptor status words bit positions.
|
|
* Receive buffer descriptor consists of two 32-bit registers,
|
|
* the first - word0 contains a 32-bit word aligned address pointing to the
|
|
* address of the buffer. The lower two bits make up the wrap bit indicating
|
|
* the last descriptor and the ownership bit to indicate it has been used by
|
|
* the XEmacPs.
|
|
* The following register - word1, contains status information regarding why
|
|
* the frame was received (the filter match condition) as well as other
|
|
* useful info.
|
|
* @{
|
|
*/
|
|
#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
|
|
#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
|
|
#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
|
|
#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
|
|
#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
|
|
matched */
|
|
#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
|
|
#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
|
|
#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
|
|
#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
|
|
#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
|
|
#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
|
|
#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
|
|
#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
|
|
#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
|
|
|
|
#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
|
|
#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
|
|
#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
|
|
/*
|
|
* @}
|
|
*/
|
|
|
|
/*
|
|
* Define appropriate I/O access method to memory mapped I/O or other
|
|
* interface if necessary.
|
|
*/
|
|
|
|
#define XEmacPs_In32 Xil_In32
|
|
#define XEmacPs_Out32 Xil_Out32
|
|
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
*
|
|
* Read the given register.
|
|
*
|
|
* @param BaseAddress is the base address of the device
|
|
* @param RegOffset is the register offset to be read
|
|
*
|
|
* @return The 32-bit value of the register
|
|
*
|
|
* @note
|
|
* C-style signature:
|
|
* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
|
|
*
|
|
*****************************************************************************/
|
|
#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
|
|
XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
|
|
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
*
|
|
* Write the given register.
|
|
*
|
|
* @param BaseAddress is the base address of the device
|
|
* @param RegOffset is the register offset to be written
|
|
* @param Data is the 32-bit value to write to the register
|
|
*
|
|
* @return None.
|
|
*
|
|
* @note
|
|
* C-style signature:
|
|
* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
|
|
* u32 Data)
|
|
*
|
|
*****************************************************************************/
|
|
#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
|
|
XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
|
|
|
|
/************************** Function Prototypes *****************************/
|
|
/*
|
|
* Perform reset operation to the emacps interface
|
|
*/
|
|
void XEmacPs_ResetHw(u32 BaseAddr);
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* end of protection macro */
|