889c80eb83
v_tpg IP has a new example design available in vivado catalogue. Associated example software is added to the driver along with the xsct script to create sdk project Signed-off-by: Rohit Consul <rohit.consul@xilinx.com> Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
30 lines
1.3 KiB
Text
30 lines
1.3 KiB
Text
vtpg_example.tcl automates the process of generating the downloadable bit & elf files from the provided example hdf file.
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Example application design source files (contained within "examples" folder) are tightly coupled with the v_tpg example design available in Vivado Catalogue.
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To run the provided tcl
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1. Copy the exported example design hdf file in the "examples" directory of the driver
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2. Launch the xsct terminal
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3. cd into the examples directory
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4. source the tcl file
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xsct%>source vtpg_example.tcl
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4. execute the script
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xsct%>vtpg_example <hdf_file_name.hdf>
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Script will perform following operations
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1. Create workspace
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2. Create HW project
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3. Create BSP
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4. Create Application Project
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5. Build BSP and Application Project
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After the process is complete required files will be available in
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bit file -> vtpg_example.sdk/vtpg_example_hw_platform folder
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elf file -> vtpg_example.sdk/vtpg_example_design/{Debug/Release} folder
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When executed on the board the example application will perform following operations
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1. Program Video Clock Generator to 1080p@60Hz
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2. Program TPG0 & TPG1 to 1080p@60Hz
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3. Check for Video Lock and report the status (PASS/FAIL)on UART
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4. Repeat Steps 1-3 for 4KP@30Hz and 4KP@60Hz
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Note: Serial terminal baud rate should be set to 9600
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