eff8fdf3f3
-Added logic to fix vdma ip alignement issues with different bit width at axis and aximm interface at all supported pixel/clk and color depth combinations -Moved stream (input/output) validation logic scattered around in different blocks to a central location -Added API to report subsystem configuration status -Code cleanup and changed relevant prints to dbg print Signed-off-by: Rohit Consul <rohit.consul@xilinx.com> Reviewed-by: Andrei Simion <andreis@xilinx.com> |
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