f20ccd3175
This patch updates the doxygen for the drivers axivdma, can, canps ,devcfg , bram to include .h files in the listof files provided in the index.html file. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
90 lines
5.7 KiB
HTML
Executable file
90 lines
5.7 KiB
HTML
Executable file
<html>
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<head>
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<meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
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<title>
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Xilinx Driver devcfg v3_1: devcfg v3_1
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</title>
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<link href="doxygen_kalyanidocs/doc/css/driver_api_doxygen.css" rel="stylesheet" type="text/css">
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</head>
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<h3 class="PageHeader">Xilinx Processor IP Library</h3>
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<hl>Software Drivers</hl>
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<hr class="whs1">
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<!-- Generated by Doxygen 1.6.1 -->
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<div class="navigation" id="top">
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<div class="tabs">
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<ul>
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<li class="current"><a href="index.html"><span>Main Page</span></a></li>
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<li><a href="annotated.html"><span>Classes</span></a></li>
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<li><a href="files.html"><span>Files</span></a></li>
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</ul>
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</div>
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</div>
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<div class="contents">
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<h1>devcfg v3_1</h1><p>The is the main header file for the Device Configuration Interface of the Zynq device. The device configuration interface has three main functionality. 1. AXI-PCAP 2. Security Policy 3. XADC This current version of the driver supports only the AXI-PCAP and Security Policy blocks. There is a separate driver for XADC.</p>
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<p>AXI-PCAP is used for download/upload an encrypted or decrypted bitstream. DMA embedded in the AXI PCAP provides the master interface to the Device configuration block for any DMA transfers. The data transfer can take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip RAM/DDR/peripheral memory).</p>
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<p>The current driver only supports the downloading the FPGA bitstream and readback of the decrypted image (sort of loopback). The driver does not know what information needs to be written to the FPGA to readback FPGA configuration register or memory data. The application above the driver should take care of creating the data that needs to be downloaded to the FPGA so that the bitstream can be readback. This driver also does not support the reading of the internal registers of the PCAP. The driver has no knowledge of the PCAP internals.</p>
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<p><b> Initialization and Configuration </b></p>
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<p>The device driver enables higher layer software (e.g., an application) to communicate with the Device Configuration device.</p>
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<p><a class="el" href="xdevcfg_8c.html#afcaaa8ac67cf7316c54d1cba36e83e08">XDcfg_CfgInitialize()</a> API is used to initialize the Device Configuration Interface. The user needs to first call the <a class="el" href="xdevcfg_8h.html#a33bfeb1455b8553f55d614ec46a52670">XDcfg_LookupConfig()</a> API which returns the Configuration structure pointer which is passed as a parameter to the <a class="el" href="xdevcfg_8c.html#afcaaa8ac67cf7316c54d1cba36e83e08">XDcfg_CfgInitialize()</a> API.</p>
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<p><b>Interrupts</b> The Driver implements an interrupt handler to support the interrupts provided by this interface.</p>
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<p><b> Threads </b></p>
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<p>This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.</p>
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<p><b> Asserts </b></p>
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<p>Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.</p>
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<p><b> Building the driver </b></p>
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<p>The <a class="el" href="struct_x_dcfg.html">XDcfg</a> driver is composed of several source files. This allows the user to build and link only those parts of the driver that are necessary.</p>
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<p><br/>
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<br/>
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</p>
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<pre>
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MODIFICATION HISTORY:</pre><pre> Ver Who Date Changes
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----- --- -------- ---------------------------------------------
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1.00a hvm 02/07/11 First release
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2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
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source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
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APIs is words (32 bit) and not bytes.
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Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
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to add information that 2 LSBs of the Source/Destination
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address when equal to 2<>b01 indicate the last DMA command
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of an overall transfer.
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Destination Address passed to this API for secure transfers
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instead of using 0xFFFFFFFF for CR 662197. This issue was
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resulting in the failure of secure transfers of
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non-bitstream images.
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2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
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set the mask instead of oring it with the
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value read from the interrupt status register
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Added defines for the PS Version bits,
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removed the FIFO Flush bits from the
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Miscellaneous Control Reg.
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Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
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and XDcfg_SelectPcapInterface APIs for CR 643295
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The user has to call the XDcfg_SelectIcapInterface API
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for the PL reconfiguration using AXI HwIcap.
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Updated the XDcfg_Transfer API to clear the
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QUARTER_PCAP_RATE_EN bit in the control register for
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non secure writes for CR 675543.
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2.02a nm 01/31/13 Fixed CR# 679335.
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Added Setting and Clearing the internal PCAP loopback.
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Removed code for enabling/disabling AES engine as BootROM
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locks down this setting.
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Fixed CR# 681976.
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Skip Checking the PCFG_INIT in case of non-secure DMA
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loopback.
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Fixed CR# 699558.
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XDcfg_Transfer fails to transfer data in loopback mode.
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Fixed CR# 701348.
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Peripheral test fails with Running
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DcfgSelfTestExample() in SECURE bootmode.
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2.03a nm 04/19/13 Fixed CR# 703728.
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Updated the register definitions as per the latest TRM
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version UG585 (v1.4) November 16, 2012.
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3.0 adk 10/12/13 Updated as per the New Tcl API's
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3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
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</pre> </div>
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<p class="Copyright">
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Copyright © 1995-2014 Xilinx, Inc. All rights reserved.
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</p>
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</body>
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</html>
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