embeddedsw/XilinxProcessorIPLib
Andrei-Liviu Simion f1c4b783ad dptx: Handle new PHY_CONFIG bit for 8b10b encoding.
Bit 21 of DPTX register PHY_CONFIG (0x200) enables 8b10b encoding.

In v6.0 of the DPTX core, the default value is '1'.
Current driver should keep this value untouched when writing to the PHY_CONFIG
register.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-27 12:56:52 +05:30
..
drivers dptx: Handle new PHY_CONFIG bit for 8b10b encoding. 2015-04-27 12:56:52 +05:30