2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
789 lines
21 KiB
C
Executable file
789 lines
21 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/**
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*
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* @file xaxiethernet_example_util.c
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*
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* This file implements the utility functions for the Axi Ethernet example code.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a asa 6/30/10 First release based on the ll temac driver
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* 3.01a srt 02/03/13 Added support for SGMII mode (CR 676793).
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* 02/14/13 Added support for Zynq (CR 681136).
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* 3.02a srt 04/24/13 Modified parameter *_SGMII_PHYADDR to *_PHYADDR, the
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* config parameter C_PHYADDR applies to SGMII/1000BaseX
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* modes of operation and added support for 1000BaseX mode
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* (CR 704195). Added function *_ConfigureInternalPhy()
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* for this purpose.
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* 04/24/13 Added support for RGMII mode.
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* 3.02a srt 08/06/13 Fixed CR 717949:
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* Configures external Marvel 88E1111 PHY based on the
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* axi ethernet physical interface type and allows to
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* operate in specific interface mode without changing
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* jumpers on the Microblaze board.
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*
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* </pre>
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "xaxiethernet_example.h"
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#if !defined (__MICROBLAZE__) && !defined(__PPC__)
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#include "sleep.h"
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#endif
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/************************** Variable Definitions ****************************/
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/*
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* Local MAC address
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*/
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char AxiEthernetMAC[6] = { 0x00, 0x0A, 0x35, 0x01, 0x02, 0x03 };
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/******************************************************************************/
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/**
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*
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* Set the MAC addresses in the frame.
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*
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* @param FramePtr is the pointer to the frame.
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* @param DestAddr is the Destination MAC address.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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void AxiEthernetUtilFrameHdrFormatMAC(EthernetFrame *FramePtr, char *DestAddr)
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{
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char *Frame = (char *) FramePtr;
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char *SourceAddress = AxiEthernetMAC;
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int Index;
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/*
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* Destination address
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*/
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for (Index = 0; Index < XAE_MAC_ADDR_SIZE; Index++) {
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*Frame++ = *DestAddr++;
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}
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/*
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* Source address
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*/
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for (Index = 0; Index < XAE_MAC_ADDR_SIZE; Index++) {
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*Frame++ = *SourceAddress++;
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}
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}
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/******************************************************************************/
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/**
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*
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* Set the frame type for the specified frame.
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*
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* @param FramePtr is the pointer to the frame.
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* @param FrameType is the Type to set in frame.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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void AxiEthernetUtilFrameHdrFormatType(EthernetFrame *FramePtr, u16 FrameType)
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{
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char *Frame = (char *) FramePtr;
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/*
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* Increment to type field
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*/
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Frame = Frame + 12;
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FrameType = Xil_Htons(FrameType);
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/*
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* Set the type
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*/
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*(u16 *) Frame = FrameType;
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}
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/******************************************************************************/
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/**
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* This function places a pattern in the payload section of a frame. The pattern
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* is a 8 bit incrementing series of numbers starting with 0.
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* Once the pattern reaches 256, then the pattern changes to a 16 bit
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* incrementing pattern:
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* <pre>
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* 0, 1, 2, ... 254, 255, 00, 00, 00, 01, 00, 02, ...
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* </pre>
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*
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* @param FramePtr is a pointer to the frame to change.
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* @param PayloadSize is the number of bytes in the payload that will be
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* set.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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void AxiEthernetUtilFrameSetPayloadData(EthernetFrame *FramePtr,
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int PayloadSize)
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{
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unsigned BytesLeft = PayloadSize;
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u8 *Frame;
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u16 Counter = 0;
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/*
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* Set the frame pointer to the start of the payload area
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*/
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Frame = (u8 *) FramePtr + XAE_HDR_SIZE;
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/*
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* Insert 8 bit incrementing pattern
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*/
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while (BytesLeft && (Counter < 256)) {
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*Frame++ = (u8) Counter++;
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BytesLeft--;
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}
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/*
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* Switch to 16 bit incrementing pattern
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*/
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while (BytesLeft) {
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*Frame++ = (u8) (Counter >> 8); /* high */
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BytesLeft--;
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if (!BytesLeft)
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break;
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*Frame++ = (u8) Counter++; /* low */
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BytesLeft--;
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}
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}
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/******************************************************************************/
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/**
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*
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* Set the frame VLAN info for the specified frame.
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*
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* @param FramePtr is the pointer to the frame.
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* @param VlanNumber is the VlanValue insertion position to set in frame.
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* @param Vid is the 4 bytes Vlan value (TPID, Priority, CFI, VID)
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* to be set in frame.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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void AxiEthernetUtilFrameHdrVlanFormatVid(EthernetFrame *FramePtr,
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u32 VlanNumber, u32 Vid)
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{
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char *Frame = (char *) FramePtr;
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/*
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* Increment to type field
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*/
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Frame = Frame + 12 + (VlanNumber * 4);
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Vid = Xil_Htonl(Vid);
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/*
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* Set the type
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*/
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*(u32 *) Frame = Vid;
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}
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/******************************************************************************/
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/**
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*
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* Set the frame type for the specified frame.
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*
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* @param FramePtr is the pointer to the frame.
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* @param FrameType is the Type to set in frame.
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* @param VlanNumber is the VLAN friendly adjusted insertion position to
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* set in frame.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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void AxiEthernetUtilFrameHdrVlanFormatType(EthernetFrame *FramePtr,
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u16 FrameType, u32 VlanNumber)
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{
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char *Frame = (char *) FramePtr;
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/*
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* Increment to type field
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*/
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Frame = Frame + 12 + (VlanNumber * 4);
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FrameType = Xil_Htons(FrameType);
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/*
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* Set the type
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*/
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*(u16 *) Frame = FrameType;
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}
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/******************************************************************************/
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/**
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* This function places a pattern in the payload section of a frame. The pattern
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* is a 8 bit incrementing series of numbers starting with 0.
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* Once the pattern reaches 256, then the pattern changes to a 16 bit
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* incrementing pattern:
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* <pre>
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* 0, 1, 2, ... 254, 255, 00, 00, 00, 01, 00, 02, ...
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* </pre>
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*
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* @param FramePtr is a pointer to the frame to change.
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* @param PayloadSize is the number of bytes in the payload that will be set.
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* @param VlanNumber is the VLAN friendly adjusted insertion position to
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* set in frame.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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void AxiEthernetUtilFrameSetVlanPayloadData(EthernetFrame *FramePtr,
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int PayloadSize, u32 VlanNumber)
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{
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unsigned BytesLeft = PayloadSize;
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u8 *Frame;
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u16 Counter = 0;
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/*
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* Set the frame pointer to the start of the payload area
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*/
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Frame = (u8 *) FramePtr + XAE_HDR_SIZE + (VlanNumber * 4);
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/*
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* Insert 8 bit incrementing pattern
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*/
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while (BytesLeft && (Counter < 256)) {
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*Frame++ = (u8) Counter++;
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BytesLeft--;
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}
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/*
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* Switch to 16 bit incrementing pattern
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*/
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while (BytesLeft) {
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*Frame++ = (u8) (Counter >> 8); /* high */
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BytesLeft--;
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if (!BytesLeft)
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break;
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*Frame++ = (u8) Counter++; /* low */
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BytesLeft--;
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}
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}
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/******************************************************************************/
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/**
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* This function verifies the frame data against a CheckFrame.
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*
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* Validation occurs by comparing the ActualFrame to the header of the
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* CheckFrame. If the headers match, then the payload of ActualFrame is
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* verified for the same pattern Util_FrameSetPayloadData() generates.
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*
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* @param CheckFrame is a pointer to a frame containing the 14 byte header
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* that should be present in the ActualFrame parameter.
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* @param ActualFrame is a pointer to a frame to validate.
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*
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* @return - XST_SUCCESS if successful.
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* - XST_FAILURE in case of failure.
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*
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* @note None.
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*
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******************************************************************************/
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int AxiEthernetUtilFrameVerify(EthernetFrame * CheckFrame,
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EthernetFrame * ActualFrame)
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{
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unsigned char *CheckPtr = (unsigned char *) CheckFrame;
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unsigned char *ActualPtr = (unsigned char *) ActualFrame;
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u16 BytesLeft;
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u16 Counter;
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int Index;
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/*
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* Compare the headers
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*/
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for (Index = 0; Index < XAE_HDR_SIZE; Index++) {
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if (CheckPtr[Index] != ActualPtr[Index]) {
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return XST_FAILURE;
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}
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}
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Index = 0;
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BytesLeft = *(u16 *) &ActualPtr[12];
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BytesLeft = Xil_Ntohs(BytesLeft);
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/*
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* Get the length of the payload, do not use VLAN TPID here.
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* TPID needs to be verified.
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*/
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while ((0x8100 == BytesLeft) || (0x88A8 == BytesLeft) ||
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(0x9100 == BytesLeft) || (0x9200 == BytesLeft)) {
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Index++;
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BytesLeft = *(u16 *) &ActualPtr[12+(4*Index)];
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BytesLeft = Xil_Ntohs(BytesLeft);
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}
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/*
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* Validate the payload
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*/
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Counter = 0;
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ActualPtr = &ActualPtr[14+(4*Index)];
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/*
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* Check 8 bit incrementing pattern
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*/
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while (BytesLeft && (Counter < 256)) {
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if (*ActualPtr++ != (u8) Counter++) {
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return XST_FAILURE;
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}
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BytesLeft--;
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}
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/*
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* Check 16 bit incrementing pattern
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*/
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while (BytesLeft) {
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if (*ActualPtr++ != (u8) (Counter >> 8)) { /* high */
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return XST_FAILURE;
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}
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BytesLeft--;
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if (!BytesLeft)
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break;
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if (*ActualPtr++ != (u8) Counter++) { /* low */
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return XST_FAILURE;
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}
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BytesLeft--;
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}
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return XST_SUCCESS;
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}
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/******************************************************************************/
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/**
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* This function sets all bytes of a frame to 0.
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*
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* @param FramePtr is a pointer to the frame itself.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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void AxiEthernetUtilFrameMemClear(EthernetFrame * FramePtr)
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{
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u32 *Data32Ptr = (u32 *) FramePtr;
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u32 WordsLeft = sizeof(EthernetFrame) / sizeof(u32);
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/*
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* Frame should be an integral number of words
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*/
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while (WordsLeft--) {
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*Data32Ptr++ = 0;
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}
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}
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/******************************************************************************/
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/**
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*
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* This function detects the PHY address by looking for successful MII status
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* register contents (PHY register 1). It looks for a PHY that supports
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* auto-negotiation and 10Mbps full-duplex and half-duplex. So, this code
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* won't work for PHYs that don't support those features, but it's a bit more
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* general purpose than matching a specific PHY manufacturer ID.
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*
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* Note also that on some (older) Xilinx ML4xx boards, PHY address 0 does not
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* properly respond to this query. But, since the default is 0 and asssuming
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* no other address responds, then it seems to work OK.
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*
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* @param The Axi Ethernet driver instance
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*
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* @return The address of the PHY (defaults to 0 if none detected)
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*
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* @note None.
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*
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******************************************************************************/
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/* Use MII register 1 (MII status register) to detect PHY */
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#define PHY_DETECT_REG 1
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/* Mask used to verify certain PHY features (or register contents)
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* in the register above:
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* 0x1000: 10Mbps full duplex support
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* 0x0800: 10Mbps half duplex support
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* 0x0008: Auto-negotiation support
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*/
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#define PHY_DETECT_MASK 0x1808
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u32 AxiEthernetDetectPHY(XAxiEthernet * AxiEthernetInstancePtr)
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{
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u16 PhyReg;
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int PhyAddr;
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for (PhyAddr = 31; PhyAddr >= 0; PhyAddr--) {
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XAxiEthernet_PhyRead(AxiEthernetInstancePtr, PhyAddr,
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PHY_DETECT_REG, &PhyReg);
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if ((PhyReg != 0xFFFF) &&
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((PhyReg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
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/* Found a valid PHY address */
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return PhyAddr;
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}
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}
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return 0; /* Default to zero */
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}
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/******************************************************************************/
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/**
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* Set PHY to loopback mode. This works with the marvell PHY common on ML40x
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* evaluation boards
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*
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* @param Speed is the loopback speed 10, 100, or 1000 Mbit
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*
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******************************************************************************/
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/* IEEE PHY Specific definitions */
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#define PHY_R0_CTRL_REG 0
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#define PHY_R3_PHY_IDENT_REG 3
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#define PHY_R0_RESET 0x8000
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#define PHY_R0_LOOPBACK 0x4000
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#define PHY_R0_ANEG_ENABLE 0x1000
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#define PHY_R0_DFT_SPD_MASK 0x2040
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#define PHY_R0_DFT_SPD_10 0x0000
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#define PHY_R0_DFT_SPD_100 0x2000
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#define PHY_R0_DFT_SPD_1000 0x0040
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#define PHY_R0_ISOLATE 0x0400
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/* Marvel PHY 88E1111 Specific definitions */
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#define PHY_R20_EXTND_CTRL_REG 20
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#define PHY_R27_EXTND_STS_REG 27
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#define PHY_R20_DFT_SPD_10 0x20
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#define PHY_R20_DFT_SPD_100 0x50
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#define PHY_R20_DFT_SPD_1000 0x60
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#define PHY_R20_RX_DLY 0x80
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#define PHY_R27_MAC_CONFIG_GMII 0x000F
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#define PHY_R27_MAC_CONFIG_MII 0x000F
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#define PHY_R27_MAC_CONFIG_RGMII 0x000B
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#define PHY_R27_MAC_CONFIG_SGMII 0x0004
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/* Marvel PHY 88E1116R Specific definitions */
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#define PHY_R22_PAGE_ADDR_REG 22
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#define PHY_PG2_R21_CTRL_REG 21
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#define PHY_REG21_10 0x0030
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#define PHY_REG21_100 0x2030
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#define PHY_REG21_1000 0x0070
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/* Marvel PHY flags */
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#define MARVEL_PHY_88E1111_MODEL 0xC0
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#define MARVEL_PHY_88E1116R_MODEL 0x240
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#define PHY_MODEL_NUM_MASK 0x3F0
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/******************************************************************************/
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/**
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*
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* This function sets the PHY to loopback mode. This works with the marvell PHY
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* common on ML40x evaluation boards.
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*
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* @param AxiEthernetInstancePtr is a pointer to the instance of the
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* AxiEthernet component.
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* @param Speed is the loopback speed 10, 100, or 1000 Mbit.
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*
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* @return - XST_SUCCESS if successful.
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* - XST_FAILURE, in case of failure..
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*
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* @note None.
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*
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******************************************************************************/
|
|
int AxiEthernetUtilEnterLoopback(XAxiEthernet *AxiEthernetInstancePtr,
|
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int Speed)
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{
|
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u16 PhyReg0;
|
|
signed int PhyAddr;
|
|
u8 PhyType;
|
|
u16 PhyModel;
|
|
u16 PhyReg20; /* Extended PHY specific Register (Reg 20)
|
|
of Marvell 88E1111 PHY */
|
|
u16 PhyReg21; /* Control Register MAC (Reg 21)
|
|
of Marvell 88E1116R PHY */
|
|
|
|
/* Get the Phy Interface */
|
|
PhyType = XAxiEthernet_GetPhysicalInterface(AxiEthernetInstancePtr);
|
|
|
|
/* Detect the PHY address */
|
|
if (PhyType != XAE_PHY_TYPE_1000BASE_X) {
|
|
PhyAddr = AxiEthernetDetectPHY(AxiEthernetInstancePtr);
|
|
} else {
|
|
PhyAddr = XPAR_AXIETHERNET_0_PHYADDR;
|
|
}
|
|
|
|
XAxiEthernet_PhyRead(AxiEthernetInstancePtr, PhyAddr,
|
|
PHY_R3_PHY_IDENT_REG, &PhyModel);
|
|
PhyModel = PhyModel & PHY_MODEL_NUM_MASK;
|
|
|
|
/* Clear the PHY of any existing bits by zeroing this out */
|
|
PhyReg0 = PhyReg20 = PhyReg21 = 0;
|
|
|
|
switch (Speed) {
|
|
case XAE_SPEED_10_MBPS:
|
|
PhyReg0 |= PHY_R0_DFT_SPD_10;
|
|
PhyReg20 |= PHY_R20_DFT_SPD_10;
|
|
PhyReg21 |= PHY_REG21_10;
|
|
break;
|
|
|
|
case XAE_SPEED_100_MBPS:
|
|
PhyReg0 |= PHY_R0_DFT_SPD_100;
|
|
PhyReg20 |= PHY_R20_DFT_SPD_100;
|
|
PhyReg21 |= PHY_REG21_100;
|
|
break;
|
|
|
|
case XAE_SPEED_1000_MBPS:
|
|
PhyReg0 |= PHY_R0_DFT_SPD_1000;
|
|
PhyReg20 |= PHY_R20_DFT_SPD_1000;
|
|
PhyReg21 |= PHY_REG21_1000;
|
|
break;
|
|
|
|
default:
|
|
AxiEthernetUtilErrorTrap("Intg_LinkSpeed not 10, 100, or 1000 mbps");
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
/* RGMII mode Phy specific registers initialization */
|
|
if ((PhyType == XAE_PHY_TYPE_RGMII_2_0) ||
|
|
(PhyType == XAE_PHY_TYPE_RGMII_1_3)) {
|
|
if (PhyModel == MARVEL_PHY_88E1111_MODEL) {
|
|
PhyReg20 |= PHY_R20_RX_DLY;
|
|
/*
|
|
* Adding Rx delay. Configuring loopback speed.
|
|
*/
|
|
XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
|
|
PhyAddr, PHY_R20_EXTND_CTRL_REG,
|
|
PhyReg20);
|
|
} else if (PhyModel == MARVEL_PHY_88E1116R_MODEL) {
|
|
/*
|
|
* Switching to PAGE2
|
|
*/
|
|
XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
|
|
PhyAddr,
|
|
PHY_R22_PAGE_ADDR_REG, 2);
|
|
/*
|
|
* Adding Tx and Rx delay. Configuring loopback speed.
|
|
*/
|
|
XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
|
|
PhyAddr,
|
|
PHY_PG2_R21_CTRL_REG, PhyReg21);
|
|
/*
|
|
* Switching to PAGE0
|
|
*/
|
|
XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
|
|
PhyAddr,
|
|
PHY_R22_PAGE_ADDR_REG, 0);
|
|
}
|
|
PhyReg0 &= (~PHY_R0_ANEG_ENABLE);
|
|
}
|
|
|
|
/* Configure interface modes */
|
|
if (PhyModel == MARVEL_PHY_88E1111_MODEL) {
|
|
if ((PhyType == XAE_PHY_TYPE_RGMII_2_0) ||
|
|
(PhyType == XAE_PHY_TYPE_RGMII_1_3)) {
|
|
XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
|
|
PhyAddr, PHY_R27_EXTND_STS_REG,
|
|
PHY_R27_MAC_CONFIG_RGMII);
|
|
} else if (PhyType == XAE_PHY_TYPE_SGMII) {
|
|
XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
|
|
PhyAddr, PHY_R27_EXTND_STS_REG,
|
|
PHY_R27_MAC_CONFIG_SGMII);
|
|
} else if ((PhyType == XAE_PHY_TYPE_GMII) ||
|
|
(PhyType == XAE_PHY_TYPE_MII)) {
|
|
XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
|
|
PhyAddr, PHY_R27_EXTND_STS_REG,
|
|
PHY_R27_MAC_CONFIG_GMII );
|
|
}
|
|
}
|
|
|
|
/* Set the speed and put the PHY in reset, then put the PHY in loopback */
|
|
XAxiEthernet_PhyWrite(AxiEthernetInstancePtr, PhyAddr,
|
|
PHY_R0_CTRL_REG,
|
|
PhyReg0 | PHY_R0_RESET);
|
|
AxiEthernetUtilPhyDelay(AXIETHERNET_PHY_DELAY_SEC);
|
|
XAxiEthernet_PhyRead(AxiEthernetInstancePtr,PhyAddr,
|
|
PHY_R0_CTRL_REG, &PhyReg0);
|
|
XAxiEthernet_PhyWrite(AxiEthernetInstancePtr, PhyAddr,
|
|
PHY_R0_CTRL_REG,
|
|
PhyReg0 | PHY_R0_LOOPBACK);
|
|
|
|
if ((PhyType == XAE_PHY_TYPE_SGMII) ||
|
|
(PhyType == XAE_PHY_TYPE_1000BASE_X)) {
|
|
AxiEthernetUtilConfigureInternalPhy(AxiEthernetInstancePtr, Speed);
|
|
}
|
|
|
|
AxiEthernetUtilPhyDelay(1);
|
|
|
|
return XST_SUCCESS;
|
|
}
|
|
|
|
/******************************************************************************/
|
|
/**
|
|
*
|
|
* This function is called by example code when an error is detected. It
|
|
* can be set as a breakpoint with a debugger or it can be used to print out the
|
|
* given message if there is a UART or STDIO device.
|
|
*
|
|
* @param Message is the text explaining the error
|
|
*
|
|
* @return None
|
|
*
|
|
* @note None
|
|
*
|
|
******************************************************************************/
|
|
void AxiEthernetUtilErrorTrap(char *Message)
|
|
{
|
|
static int Count = 0;
|
|
|
|
Count++;
|
|
|
|
#ifdef STDOUT_BASEADDRESS
|
|
xil_printf("%s\r\n", Message);
|
|
#endif
|
|
}
|
|
|
|
/******************************************************************************/
|
|
/**
|
|
*
|
|
* For Microblaze we use an assembly loop that is roughly the same regardless of
|
|
* optimization level, although caches and memory access time can make the delay
|
|
* vary. Just keep in mind that after resetting or updating the PHY modes,
|
|
* the PHY typically needs time to recover.
|
|
*
|
|
* @return None
|
|
*
|
|
* @note None
|
|
*
|
|
******************************************************************************/
|
|
void AxiEthernetUtilPhyDelay(unsigned int Seconds)
|
|
{
|
|
#if defined (__MICROBLAZE__) || defined(__PPC__)
|
|
static int WarningFlag = 0;
|
|
|
|
/* If MB caches are disabled or do not exist, this delay loop could
|
|
* take minutes instead of seconds (e.g., 30x longer). Print a warning
|
|
* message for the user (once). If only MB had a built-in timer!
|
|
*/
|
|
if (((mfmsr() & 0x20) == 0) && (!WarningFlag)) {
|
|
WarningFlag = 1;
|
|
}
|
|
|
|
#define ITERS_PER_SEC (XPAR_CPU_CORE_CLOCK_FREQ_HZ / 6)
|
|
asm volatile ("\n"
|
|
"1: \n\t"
|
|
"addik r7, r0, %0 \n\t"
|
|
"2: \n\t"
|
|
"addik r7, r7, -1 \n\t"
|
|
"bneid r7, 2b \n\t"
|
|
"or r0, r0, r0 \n\t"
|
|
"bneid %1, 1b \n\t"
|
|
"addik %1, %1, -1 \n\t"
|
|
:: "i"(ITERS_PER_SEC), "d" (Seconds));
|
|
#else
|
|
sleep(Seconds);
|
|
#endif
|
|
}
|
|
|
|
/******************************************************************************/
|
|
/**
|
|
*
|
|
* This function configures the internal phy for SGMII and 1000baseX modes.
|
|
* *
|
|
* @param AxiEthernetInstancePtr is a pointer to the instance of the
|
|
* AxiEthernet component.
|
|
* @param Speed is the loopback speed 10, 100, or 1000 Mbit.
|
|
*
|
|
* @return - XST_SUCCESS if successful.
|
|
* - XST_FAILURE, in case of failure..
|
|
*
|
|
* @note None.
|
|
*
|
|
******************************************************************************/
|
|
int AxiEthernetUtilConfigureInternalPhy(XAxiEthernet *AxiEthernetInstancePtr,
|
|
int Speed)
|
|
{
|
|
u16 PhyReg0;
|
|
signed int PhyAddr;
|
|
|
|
PhyAddr = XPAR_AXIETHERNET_0_PHYADDR;
|
|
|
|
/* Clear the PHY of any existing bits by zeroing this out */
|
|
PhyReg0 = 0;
|
|
XAxiEthernet_PhyRead(AxiEthernetInstancePtr, PhyAddr,
|
|
PHY_R0_CTRL_REG, &PhyReg0);
|
|
|
|
PhyReg0 &= (~PHY_R0_ANEG_ENABLE);
|
|
PhyReg0 &= (~PHY_R0_ISOLATE);
|
|
|
|
switch (Speed) {
|
|
case XAE_SPEED_10_MBPS:
|
|
PhyReg0 |= PHY_R0_DFT_SPD_10;
|
|
break;
|
|
case XAE_SPEED_100_MBPS:
|
|
PhyReg0 |= PHY_R0_DFT_SPD_100;
|
|
break;
|
|
case XAE_SPEED_1000_MBPS:
|
|
PhyReg0 |= PHY_R0_DFT_SPD_1000;
|
|
break;
|
|
default:
|
|
AxiEthernetUtilErrorTrap(
|
|
"Intg_LinkSpeed not 10, 100, or 1000 mbps\n\r");
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
AxiEthernetUtilPhyDelay(1);
|
|
XAxiEthernet_PhyWrite(AxiEthernetInstancePtr, PhyAddr,
|
|
PHY_R0_CTRL_REG, PhyReg0);
|
|
return XST_SUCCESS;
|
|
}
|