938554c908
This patch removes the compilation error and warning in the emacps driver. Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
260 lines
9.7 KiB
C
Executable file
260 lines
9.7 KiB
C
Executable file
/* $Id: xemacps_intr.c,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */
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/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xemacps_intr.c
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*
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* Functions in this file implement general purpose interrupt processing related
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* functionality. See xemacps.h for a detailed description of the driver.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a wsy 01/10/10 First release
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* 1.03a asa 01/24/13 Fix for CR #692702 which updates error handling for
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* Rx errors. Under heavy Rx traffic, there will be a large
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* number of errors related to receive buffer not available.
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* Because of a HW bug (SI #692601), under such heavy errors,
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* the Rx data path can become unresponsive. To reduce the
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* probabilities for hitting this HW bug, the SW writes to
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* bit 18 to flush a packet from Rx DPRAM immediately. The
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* changes for it are done in the function
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* XEmacPs_IntrHandler.
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* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification
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* and 64-bit changes.
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* </pre>
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "xemacps.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Function Prototypes ******************************/
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/************************** Variable Definitions *****************************/
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/*****************************************************************************/
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/**
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* Install an asynchronious handler function for the given HandlerType:
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*
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* @param InstancePtr is a pointer to the instance to be worked on.
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* @param HandlerType indicates what interrupt handler type is.
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* XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
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* XEMACPS_HANDLER_ERROR.
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* @param FuncPointer is the pointer to the callback function
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* @param CallBackRef is the upper layer callback reference passed back when
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* when the callback function is invoked.
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*
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* @return
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*
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* None.
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*
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* @note
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* There is no assert on the CallBackRef since the driver doesn't know what
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* it is.
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*
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*****************************************************************************/
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LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
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void *FuncPointer, void *CallBackRef)
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{
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LONG Status;
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(FuncPointer != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
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switch (HandlerType) {
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case XEMACPS_HANDLER_DMASEND:
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Status = (LONG)(XST_SUCCESS);
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InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
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InstancePtr->SendRef = CallBackRef;
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break;
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case XEMACPS_HANDLER_DMARECV:
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Status = (LONG)(XST_SUCCESS);
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InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
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InstancePtr->RecvRef = CallBackRef;
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break;
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case XEMACPS_HANDLER_ERROR:
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Status = (LONG)(XST_SUCCESS);
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InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
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InstancePtr->ErrorRef = CallBackRef;
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break;
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default:
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Status = (LONG)(XST_INVALID_PARAM);
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break;
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}
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return Status;
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}
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/*****************************************************************************/
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/**
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* Master interrupt handler for EMAC driver. This routine will query the
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* status of the device, bump statistics, and invoke user callbacks.
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*
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* This routine must be connected to an interrupt controller using OS/BSP
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* specific methods.
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*
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* @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
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* interrupt.
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*
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******************************************************************************/
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void XEmacPs_IntrHandler(void *XEmacPsPtr)
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{
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u32 RegISR;
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u32 RegSR;
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u32 RegCtrl;
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u32 RegQ1ISR = 0U;
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XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
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/* This ISR will try to handle as many interrupts as it can in a single
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* call. However, in most of the places where the user's error handler
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* is called, this ISR exits because it is expected that the user will
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* reset the device in nearly all instances.
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*/
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RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
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XEMACPS_ISR_OFFSET);
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/* Read Transmit Q1 ISR */
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if (InstancePtr->Version == 7)
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RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
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XEMACPS_INTQ1_STS_OFFSET);
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/* Clear the interrupt status register */
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XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
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RegISR);
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/* Receive complete interrupt */
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if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
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/* Clear RX status register RX complete indication but preserve
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* error bits if there is any */
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XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
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XEMACPS_RXSR_OFFSET,
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((u32)XEMACPS_RXSR_FRAMERX_MASK |
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(u32)XEMACPS_RXSR_BUFFNA_MASK));
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InstancePtr->RecvHandler(InstancePtr->RecvRef);
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}
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/* Transmit Q1 complete interrupt */
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if ((InstancePtr->Version == 7) &&
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((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
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/* Clear TX status register TX complete indication but preserve
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* error bits if there is any */
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XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
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XEMACPS_INTQ1_STS_OFFSET,
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XEMACPS_INTQ1SR_TXCOMPL_MASK);
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XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
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XEMACPS_TXSR_OFFSET,
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((u32)XEMACPS_TXSR_TXCOMPL_MASK |
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(u32)XEMACPS_TXSR_USEDREAD_MASK));
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InstancePtr->SendHandler(InstancePtr->SendRef);
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}
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/* Transmit complete interrupt */
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if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
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/* Clear TX status register TX complete indication but preserve
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* error bits if there is any */
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XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
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XEMACPS_TXSR_OFFSET,
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((u32)XEMACPS_TXSR_TXCOMPL_MASK |
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(u32)XEMACPS_TXSR_USEDREAD_MASK));
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InstancePtr->SendHandler(InstancePtr->SendRef);
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}
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/* Receive error conditions interrupt */
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if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
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/* Clear RX status register */
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RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
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XEMACPS_RXSR_OFFSET);
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XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
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XEMACPS_RXSR_OFFSET, RegSR);
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/* Fix for CR # 692702. Write to bit 18 of net_ctrl
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* register to flush a packet out of Rx SRAM upon
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* an error for receive buffer not available. */
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if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
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RegCtrl =
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XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
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XEMACPS_NWCTRL_OFFSET);
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RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
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XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
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XEMACPS_NWCTRL_OFFSET, RegCtrl);
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}
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InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_RECV,
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RegSR);
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}
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/* When XEMACPS_IXR_TXCOMPL_MASK is flaged, XEMACPS_IXR_TXUSED_MASK
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* will be asserted the same time.
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* Have to distinguish this bit to handle the real error condition.
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*/
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/* Transmit Q1 error conditions interrupt */
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if ((InstancePtr->Version == 7) &&
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((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
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((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
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/* Clear Interrupt Q1 status register */
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XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
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XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
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InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
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RegQ1ISR);
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}
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/* Transmit error conditions interrupt */
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if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
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(!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
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/* Clear TX status register */
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RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
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XEMACPS_TXSR_OFFSET);
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XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
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XEMACPS_TXSR_OFFSET, RegSR);
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InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
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RegSR);
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}
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}
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