faa2628852
Initial DisplayPort TX driver submission. Currently, only supporting SST. Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
4916 lines
215 KiB
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4916 lines
215 KiB
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xdptx_hw.h File Reference
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<link href="$DriverApiDocsCssPath" rel="stylesheet" type="text/css">
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<h3 class="PageHeader">Xilinx Processor IP Library</h3>
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<hl>Software Drivers</hl>
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<li><a href="index.html"><span>Main Page</span></a></li>
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<h1>xdptx_hw.h File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
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This header file contains the identifiers and low-level driver functions (or macros) that can be used to access the device. High-level driver functions are defined in xdptx.h.<p>
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<pre>
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MODIFICATION HISTORY:</pre><p>
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<pre> Ver Who Date Changes
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----- ---- -------- -----------------------------------------------
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1.00a als 05/17/14 Initial release.
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</pre>
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<p>
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<code>#include "xil_io.h"</code><br>
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<code>#include "xil_types.h"</code><br>
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<table border="0" cellpadding="0" cellspacing="0">
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<tr><td></td></tr>
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<tr><td colspan="2"><br><h2>DPTX core registers: Link configuration field.</h2></td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#5b1fe80c1adb3f1744a83f19854fb7b4">XDPTX_LINK_BW_SET</a> 0x0000</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#f0852cab2ae824fe3dfd71c8d093f143">XDPTX_LANE_COUNT_SET</a> 0x0004</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#2505aad381cb4ca9d1c970523229934b">XDPTX_ENHANCED_FRAME_EN</a> 0x0008</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#80266896bc3c68c7109deba44db4fcac">XDPTX_TRAINING_PATTERN_SET</a> 0x000C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#5359209ff45ece205f47013ac8f8b481">XDPTX_LINK_QUAL_PATTERN_SET</a> 0x0010</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#245e3300cb64b18ae8b5a2c05a2726a5">XDPTX_SCRAMBLING_DISABLE</a> 0x0014</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#dadb6bd439c17cd13d8fa0fc9ac5187d">XDPTX_DOWNSPREAD_CTRL</a> 0x0018</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#d67b688fb3c16c3aa74b8c6f5a6b4967">XDPTX_SOFT_RESET</a> 0x001C</td></tr>
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<tr><td colspan="2"><br><h2>DPTX core registers: Core enables.</h2></td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#59794e061554b270d02fad1a8aaa37a3">XDPTX_ENABLE</a> 0x0080</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#191c735a2ebed97d890953adcdec2d39">XDPTX_ENABLE_MAIN_STREAM</a> 0x0084</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#73580ca967b5973c7e1fbce580863441">XDPTX_ENABLE_SEC_STREAM</a> 0x0088</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#5217c3a80875b6dcda385d57c2116551">XDPTX_FORCE_SCRAMBLER_RESET</a> 0x00C0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#3d5b09f9d08691a1e9de0d7b5677a5fc">XDPTX_TX_MST_CONFIG</a> 0x00D0</td></tr>
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<tr><td colspan="2"><br><h2>DPTX core registers: Core ID.</h2></td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#e92176c8f7b15bf84f9aa8e25100e15c">XDPTX_VERSION</a> 0x00F8</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#fe16c5bc7cdf55f7851c23e27e0fad65">XDPTX_CORE_ID</a> 0x00FC</td></tr>
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<tr><td colspan="2"><br><h2>DPTX core registers: AUX channel interface.</h2></td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#ca3cbd1da75b9c1ad84c29caa94aa1c6">XDPTX_AUX_CMD</a> 0x0100</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#17b9eb2badecaf2e252834db0e9fb454">XDPTX_AUX_WRITE_FIFO</a> 0x0104</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#f52ee8f253e0d90f456e57b99956d39b">XDPTX_AUX_ADDRESS</a> 0x0108</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#bf2869e5451d401fcaefafc818884742">XDPTX_AUX_CLK_DIVIDER</a> 0x010C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#22adbb477c55f0ca7fc3740f53d69fed">XDPTX_TX_USER_FIFO_OVERFLOW</a> 0x0110</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#0f779ac12934252a5548f520e776b1e8">XDPTX_INTERRUPT_SIG_STATE</a> 0x0130</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#c3a7fc3419105d0db69c67ba2b48a1d5">XDPTX_AUX_REPLY_DATA</a> 0x0134</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#8680af673f3229e41eca23d54f4dbbed">XDPTX_AUX_REPLY_CODE</a> 0x0138</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#8e8272c15321880111c6a5c253a21d5a">XDPTX_AUX_REPLY_COUNT</a> 0x013C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#2864b992eaaffb92419a1d5c4287553a">XDPTX_INTERRUPT_STATUS</a> 0x0140</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#27c315c49cfa0c9659403e5378cf3acb">XDPTX_INTERRUPT_MASK</a> 0x0144</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#96d63a4878d267090ed96df9276d25b1">XDPTX_REPLY_DATA_COUNT</a> 0x0148</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#862f248407790107b10e27b095ccde28">XDPTX_REPLY_STATUS</a> 0x014C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#17f41514d28ecba0cd98d2e3605c725c">XDPTX_HPD_DURATION</a> 0x0150</td></tr>
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<tr><td colspan="2"><br><h2>DPTX core registers: Main stream attributes for SST / MST STREAM1.</h2></td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#71148ad51c2dcde442f3661ac23b1c8a">XDPTX_MAIN_STREAM_HTOTAL</a> 0x0180</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#72ccb4478dc0844d4564fd883595894f">XDPTX_MAIN_STREAM_VTOTAL</a> 0x0184</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#5021184f173d31eaf40914c08aa67c70">XDPTX_MAIN_STREAM_POLARITY</a> 0x0188</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#c68242b93975b27a4dd5f5424edca7c4">XDPTX_MAIN_STREAM_HSWIDTH</a> 0x018C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#80c45e2a27ace9e4b0750311c0ef84a9">XDPTX_MAIN_STREAM_VSWIDTH</a> 0x0190</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#f7dbf65764896c37d62a1be149cae2f8">XDPTX_MAIN_STREAM_HRES</a> 0x0194</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#c4442cbc0e52f8ba741a7becd59b7264">XDPTX_MAIN_STREAM_VRES</a> 0x0198</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#6878375b4d3054a6438d6c120f7aee92">XDPTX_MAIN_STREAM_HSTART</a> 0x019C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#59f96811362a03af568f526087d813c2">XDPTX_MAIN_STREAM_VSTART</a> 0x01A0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#ec12e1b6482a3af5aefc43344ed3bb3d">XDPTX_MAIN_STREAM_MISC0</a> 0x01A4</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#dae3820b7afc1aa4e0f71b6daad496a9">XDPTX_MAIN_STREAM_MISC1</a> 0x01A8</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#a9bdd81b87727fd34d2a7980d3bb8024">XDPTX_M_VID</a> 0x01AC</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#630b1bfbcebf8469d72b29b80e5cf9ef">XDPTX_TU_SIZE</a> 0x01B0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#246df330b0d3f6ea5d05fd95089e9f99">XDPTX_N_VID</a> 0x01B4</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#2eccd9b84a12fae6acf5fa0fb7e8963d">XDPTX_USER_PIXEL_WIDTH</a> 0x01B8</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#59420080445456a7bae12e8cdebbec5d">XDPTX_USER_DATA_COUNT_PER_LANE</a> 0x01BC</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#feb884273648457f2af0709b75df4928">XDPTX_MAIN_STREAM_INTERLACED</a> 0x01C0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#c0d71f16f11b0debe9e20c47442208bf">XDPTX_MIN_BYTES_PER_TU</a> 0x01C4</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#95e419cf6d2c09a29e29584e26120376">XDPTX_FRAC_BYTES_PER_TU</a> 0x01C8</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#5a2bc7766152ab752d2a3821c439740f">XDPTX_INIT_WAIT</a> 0x01CC</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#192b3ac947426e2781f599d9aed2be57">XDPTX_STREAM0</a> 0x01D0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#3d5adff92f22f4916380275fcb78aca2">XDPTX_STREAM1</a> 0x01D4</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#abbb86cc9a2f8bb9dae29262b6d60b2b">XDPTX_STREAM2</a> 0x01D8</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#c9c2cc3ea5a63b843a362b6df260b8e5">XDPTX_STREAM3</a> 0x01DC</td></tr>
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<tr><td colspan="2"><br><h2>DPTX core registers: PHY configuration status.</h2></td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#487854c0977ce9c4e9c4e58039986124">XDPTX_PHY_CONFIG</a> 0x0200</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#4079f5af02adffbfb20e539e2d07e24e">XDPTX_PHY_VOLTAGE_DIFF_LANE_0</a> 0x0220</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#ba11c9397ca6e296d47c91d7771be137">XDPTX_PHY_VOLTAGE_DIFF_LANE_1</a> 0x0224</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#9e8027b88c290569ab0e0f747b5ba36b">XDPTX_PHY_VOLTAGE_DIFF_LANE_2</a> 0x0228</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#518c1a46ae6ade901965e78a54882fea">XDPTX_PHY_VOLTAGE_DIFF_LANE_3</a> 0x022C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#7b86ba2c2f902fde88dd84f52b09118c">XDPTX_PHY_TRANSMIT_PRBS7</a> 0x0230</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#be90ee3d19c62383bbfc51ac5dabc96f">XDPTX_PHY_CLOCK_SELECT</a> 0x0234</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#096993419705dd1135ac7e4b21274e53">XDPTX_TX_PHY_POWER_DOWN</a> 0x0238</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#19e1749f366474f7da5f87cb3ff9c9e3">XDPTX_PHY_PRECURSOR_LANE_0</a> 0x023C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#30a02b0fd830a3197850481e5e86e675">XDPTX_PHY_PRECURSOR_LANE_1</a> 0x0240</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#216134c361c24e629c019f185e721e66">XDPTX_PHY_PRECURSOR_LANE_2</a> 0x0244</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#a66bb78a8cf218c5ad880e42a0c6c10b">XDPTX_PHY_PRECURSOR_LANE_3</a> 0x0248</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#f3060020b46a5ad369644d526f170b84">XDPTX_PHY_POSTCURSOR_LANE_0</a> 0x024C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#0f36af19a92afc612f2d0f2452291d08">XDPTX_PHY_POSTCURSOR_LANE_1</a> 0x0250</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#62cc76b68fd47462665537c30eaf39fe">XDPTX_PHY_POSTCURSOR_LANE_2</a> 0x0254</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#70d04a6bce7d560384db2588c1dfb381">XDPTX_PHY_POSTCURSOR_LANE_3</a> 0x0258</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#493791382f79a9be3f47d4e7b5340e80">XDPTX_PHY_STATUS</a> 0x0280</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#08e43a348bf05477f71646320ab41ddd">XDPTX_GT_DRP_COMMAND</a> 0x02A0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#a6cde0bad8b7159e38fa7355fada8de2">XDPTX_GT_DRP_READ_DATA</a> 0x02A4</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#a20e3869a077ed56257240989c3afcc3">XDPTX_GT_DRP_CHANNEL_STATUS</a> 0x02A8</td></tr>
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<tr><td colspan="2"><br><h2>DPTX core registers: DisplayPort audio.</h2></td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#a28e1ea3ef3152ca819c7893fcd9fa4b">XDPTX_TX_AUDIO_CONTROL</a> 0x0300</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#5a3a6ac16e1faba90f96d7d850424fe4">XDPTX_TX_AUDIO_CHANNELS</a> 0x0304</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#64589b203a159f299715dd3e4ae1df56">XDPTX_TX_AUDIO_INFO_DATA</a> 0x0308</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#7ccf54c25f75ee26602d38a279ecbf3a">XDPTX_TX_AUDIO_MAUD</a> 0x0328</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#eb93a2349291f47bd5bbeb24607c64c3">XDPTX_TX_AUDIO_NAUD</a> 0x032C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#212b5791abb835f33378baa4ec18b421">XDPTX_TX_AUDIO_EXT_DATA</a> 0x0330</td></tr>
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<tr><td colspan="2"><br><h2>DPTX core registers: Main stream attributes for MST STREAM2.</h2></td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#ef48a266f054385cf86f912e126520d7">XDPTX_MAIN_STREAM2_HTOTAL</a> 0x0500</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#bdcd20a010573d90375bd43f69f2ba54">XDPTX_MAIN_STREAM2_VTOTAL</a> 0x0504</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#117649d7b694fab8be20c6a596b109ae">XDPTX_MAIN_STREAM2_POLARITY</a> 0x0508</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#966d622a53206dcba94f0641da0c81ae">XDPTX_MAIN_STREAM2_HSWIDTH</a> 0x050C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#f1fef5dcbfe789148efb369091ced173">XDPTX_MAIN_STREAM2_VSWIDTH</a> 0x0510</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#6aa815567de15595bc2c907e09b8a1fe">XDPTX_MAIN_STREAM2_HRES</a> 0x0514</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#f9324cd568ed4ed4b01fd3070f9f0e70">XDPTX_MAIN_STREAM2_VRES</a> 0x0518</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#474d6c09bb8e6f09ca1449453cf4e8f0">XDPTX_MAIN_STREAM2_HSTART</a> 0x051C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#4319bb6f14f32430554c585cea30d2a5">XDPTX_MAIN_STREAM2_VSTART</a> 0x0520</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#63e49897330f42a7e28d0f8d79af93ec">XDPTX_MAIN_STREAM2_MISC0</a> 0x0524</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#438879bd482fc4002babe1af5712d24f">XDPTX_MAIN_STREAM2_MISC1</a> 0x0528</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#4acb1978e0041fc4022d497fd2520621">XDPTX_M_VID_STREAM2</a> 0x052C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#92aa475f7ccf50bcb509c77100aab0bd">XDPTX_TU_SIZE_STREAM2</a> 0x0530</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#2f2bdba8ccff7ceb3dd204aa3e5ac431">XDPTX_N_VID_STREAM2</a> 0x0534</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#457fc6f90e33915ca75ad82f94da5050">XDPTX_USER_PIXEL_WIDTH_STREAM2</a> 0x0538</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#a5af5a5f055696b339ddeaf044fed403">XDPTX_USER_DATA_COUNT_PER_LANE_STREAM2</a> 0x053C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#48a0382a45befba184376efd909005d1">XDPTX_MAIN_STREAM2_INTERLACED</a> 0x0540</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#f8f0c17ce672e22823f9491d01ad7ec1">XDPTX_MIN_BYTES_PER_TU_STREAM2</a> 0x0544</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#fddde4423debc9ec29910b1ed3facbaa">XDPTX_FRAC_BYTES_PER_TU_STREAM2</a> 0x0548</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#ccf526ba0e103be0995dedca80048c02">XDPTX_INIT_WAIT_STREAM2</a> 0x054C</td></tr>
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<tr><td colspan="2"><br><h2>DPTX core registers: Main stream attributes for MST STREAM3.</h2></td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#7f958ef8d238836c4029902c1351a3d8">XDPTX_MAIN_STREAM3_HTOTAL</a> 0x0550</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#8a4a9ee1a554e468f8acd898a2a4f05e">XDPTX_MAIN_STREAM3_VTOTAL</a> 0x0554</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#2e913728d484fbac51da0d7890cb0b1e">XDPTX_MAIN_STREAM3_POLARITY</a> 0x0558</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#1923d5ab298ed485533719a2112da2eb">XDPTX_MAIN_STREAM3_HSWIDTH</a> 0x055C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#2e9c9ab94753ac98dda3c7c84f678745">XDPTX_MAIN_STREAM3_VSWIDTH</a> 0x0560</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#457a77ecbfd4772cc44a6b0132c06379">XDPTX_MAIN_STREAM3_HRES</a> 0x0564</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#978d25b2362a197b9ca898269db79228">XDPTX_MAIN_STREAM3_VRES</a> 0x0568</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#c96c991c1e20c7c6ac77cca1604945a2">XDPTX_MAIN_STREAM3_HSTART</a> 0x056C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#1e882bb71e0c4fc28df7094eb71e9cb7">XDPTX_MAIN_STREAM3_VSTART</a> 0x0570</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#9056a672a41e96f011682a7b6541d219">XDPTX_MAIN_STREAM3_MISC0</a> 0x0574</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#b2932134b860b0ed96ae50c907992d12">XDPTX_MAIN_STREAM3_MISC1</a> 0x0578</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#b481b051aad87e35201d8300ea67057a">XDPTX_M_VID_STREAM3</a> 0x057C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#67b1aefaa452753a7056f5057ecf7181">XDPTX_TU_SIZE_STREAM3</a> 0x0580</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#3611385c5f33e89665600ec184379a64">XDPTX_N_VID_STREAM3</a> 0x0584</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#4fb4c3f07ac791b9f371cdb8b1c6f59b">XDPTX_USER_PIXEL_WIDTH_STREAM3</a> 0x0588</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#aa45192aef3af89d6594014b1b23638a">XDPTX_USER_DATA_COUNT_PER_LANE_STREAM3</a> 0x058C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#f1301d5b3d2776744c8096c5083b9c75">XDPTX_MAIN_STREAM3_INTERLACED</a> 0x0590</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#32b32343be316740cb86394cf2e08c26">XDPTX_MIN_BYTES_PER_TU_STREAM3</a> 0x0594</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#ffd96279b5c5adbdc828494d8874cb1f">XDPTX_FRAC_BYTES_PER_TU_STREAM3</a> 0x0598</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#d70718dd1cc46d29e49075d2b627f5d5">XDPTX_INIT_WAIT_STREAM3</a> 0x059C</td></tr>
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<tr><td colspan="2"><br><h2>DPTX core registers: Main stream attributes for MST STREAM4.</h2></td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#a02d8272a69befd5d7b975901f01c534">XDPTX_MAIN_STREAM4_HTOTAL</a> 0x05A0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#9322eed516b4bfa9ce46682242c4a69e">XDPTX_MAIN_STREAM4_VTOTAL</a> 0x05A4</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#312989efe8f3ba8290097d6846c8b5ef">XDPTX_MAIN_STREAM4_POLARITY</a> 0x05A8</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#8e7819f37013442eddbcff048baec9dc">XDPTX_MAIN_STREAM4_HSWIDTH</a> 0x05AC</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#f6811d6467288d07aea07ce48b8d8580">XDPTX_MAIN_STREAM4_VSWIDTH</a> 0x05B0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#6d5e7b6ddfbd7258d77faa3bc0ec64b4">XDPTX_MAIN_STREAM4_HRES</a> 0x05B4</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#1af1a6cb3951de2c9bf51956459813e7">XDPTX_MAIN_STREAM4_VRES</a> 0x05B8</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#2cdcc6a966f153d1c14575312e273b31">XDPTX_MAIN_STREAM4_HSTART</a> 0x05BC</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#7b1d7ad61f116016ec3b39d58d8c937a">XDPTX_MAIN_STREAM4_VSTART</a> 0x05C0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#b4bc0a28e5333428467362927a13cf0d">XDPTX_MAIN_STREAM4_MISC0</a> 0x05C4</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#e37188c1160e0f759a89625f17d720ea">XDPTX_MAIN_STREAM4_MISC1</a> 0x05C8</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#d9c92eb6bed17caa75b6fd5c15549956">XDPTX_M_VID_STREAM4</a> 0x05CC</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#8bf8b8cba8c2b4db28c2b19410c7932c">XDPTX_TU_SIZE_STREAM4</a> 0x05D0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#9f7111b1c39155300faa506156766c11">XDPTX_N_VID_STREAM4</a> 0x05D4</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#964f50348a330c54e3f9385df764bb5d">XDPTX_USER_PIXEL_WIDTH_STREAM4</a> 0x05D8</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#f597927a708ab606d66eb00829ca4ad0">XDPTX_USER_DATA_COUNT_PER_LANE_STREAM4</a> 0x05DC</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#8c446424d4e5c3fdfe87526a96c2cbf2">XDPTX_MAIN_STREAM4_INTERLACED</a> 0x05E0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#d8c7d9f06d6216deb311df6d729e7d88">XDPTX_MIN_BYTES_PER_TU_STREAM4</a> 0x05E4</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#1d5749c5e5ab95ab3fd450948314cb1c">XDPTX_FRAC_BYTES_PER_TU_STREAM4</a> 0x05E8</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#fe33b3121271a205a639b915ef818f8e">XDPTX_INIT_WAIT_STREAM4</a> 0x05EC</td></tr>
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<tr><td colspan="2"><br><h2>DPTX core masks, shifts, and register values.</h2></td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#454eb694a138971aaa149fef42d861ab">XDPTX_LINK_BW_SET_162GBPS</a> 0x06</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#566bc035e7e996a54088c06e6ba780c8">XDPTX_LINK_BW_SET_270GBPS</a> 0x0A</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#65a9feaa560d6328003d8223407ec2ae">XDPTX_LINK_BW_SET_540GBPS</a> 0x14</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#47a32150d890b4990105454f66661a7d">XDPTX_TRAINING_PATTERN_SET_OFF</a> 0x0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#0028aec42575496731849818fd2dabfc">XDPTX_TRAINING_PATTERN_SET_TP1</a> 0x1</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#838017c480af7c66ba05ff52eb4943c3">XDPTX_TRAINING_PATTERN_SET_TP2</a> 0x2</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#4e53269bd85479366d39f17fd1df053a">XDPTX_TRAINING_PATTERN_SET_TP3</a> 0x3</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#8fb818d85a1d645a6d423b04e81998f5">XDPTX_LINK_QUAL_PATTERN_SET_OFF</a> 0x0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#b40635c4316ab7748efb0ba0fe32e571">XDPTX_LINK_QUAL_PATTERN_SET_D102_TEST</a> 0x1</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#a0719eccb59a1855439deefb105a67ed">XDPTX_LINK_QUAL_PATTERN_SET_SER_MES</a> 0x2</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#e2e63c51f29bff2ce1254d5ca84ec9d8">XDPTX_LINK_QUAL_PATTERN_SET_PRBS7</a> 0x3</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#037c22e295d3f8b26fcddff580293cc6">XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK</a> 0x00000001</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#974d191e058d55981244a170102bfb2a">XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK</a> 0x00000002</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#98c15ede26e0e404a68298f665693276">XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK</a> 0x00000004</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#7a9059fd1dedbcdd95831b97c8b8e4df">XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK</a> 0x00000008</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#a42b3c0d8bb96f522f7d3c1e16c1ba5d">XDPTX_SOFT_RESET_AUX_MASK</a> 0x00000080</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#b3f82673e49bafb86e6200e25737e799">XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK</a> 0x0000000F</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#e3dfe9adbe046867b3dd662933c6cfe5">XDPTX_TX_MST_CONFIG_MST_EN_MASK</a> 0x00000001</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#a6ee400aabb4c568145283eecd1b0a2c">XDPTX_TX_MST_CONFIG_VCP_UPDATED_MASK</a> 0x00000002</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#93b403c56404d4ed676f2deb14dcbfad">XDPTX_VERSION_INTER_REV_MASK</a> 0x0000000F</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#4f961fb9b541d128e7d7ddd4cf937d8c">XDPTX_VERSION_CORE_PATCH_MASK</a> 0x00000030</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#0043eefcacbbd52840d16b54ad877360">XDPTX_VERSION_CORE_PATCH_SHIFT</a> 8</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#43b70a12b91cf4eb65095955225505b1">XDPTX_VERSION_CORE_VER_REV_MASK</a> 0x000000C0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#a57773a7ec75d2abe17e232a459bf73b">XDPTX_VERSION_CORE_VER_REV_SHIFT</a> 12</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#91636a250112453f44827b1c267035a4">XDPTX_VERSION_CORE_VER_MNR_MASK</a> 0x00000F00</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#12530407a38f1797c571cec54956ca4d">XDPTX_VERSION_CORE_VER_MNR_SHIFT</a> 16</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#5e8a58c4333013d122753116e2b632ec">XDPTX_VERSION_CORE_VER_MJR_MASK</a> 0x0000F000</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#a8692843543715a53090dc8015d1854b">XDPTX_VERSION_CORE_VER_MJR_SHIFT</a> 24</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#768c41baf0f19de032e8951f606a0dcf">XDPTX_CORE_ID_TYPE_MASK</a> 0x0000000F</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#a3286f7a30712bf5556860deb2165c9e">XDPTX_CORE_ID_TYPE_TX</a> 0x0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#fc831ef5eb6d5ac9eec6537478ade75d">XDPTX_CORE_ID_TYPE_RX</a> 0x1</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#4849053e05562d60e19e26bb5d2fb843">XDPTX_CORE_ID_DP_REV_MASK</a> 0x000000F0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#268fa71b51b61450b7422ddce2b2e6df">XDPTX_CORE_ID_DP_REV_SHIFT</a> 8</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#599eff5e2d775c9eef905351446d23d5">XDPTX_CORE_ID_DP_MNR_VER_MASK</a> 0x00000F00</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#79e16c199c23e4bde7d3abbcfd6c3fbf">XDPTX_CORE_ID_DP_MNR_VER_SHIFT</a> 16</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#2c7093b7bf7dea2056c9225d82af1ee5">XDPTX_CORE_ID_DP_MJR_VER_MASK</a> 0x0000F000</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#b043766862fa12d137764416ee8ce9f1">XDPTX_CORE_ID_DP_MJR_VER_SHIFT</a> 24</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#b3699ad8b3dffb732877d1b003777470">XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK</a> 0x0000000F</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#e38656cb5fe9c89ec42fc4d0a8b74174">XDPTX_AUX_CMD_MASK</a> 0x00000F00</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#7ac3c631d9e567afb2466c5a50f103da">XDPTX_AUX_CMD_SHIFT</a> 8</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#2b914586da1b26b29fa11aec81b6b2e3">XDPTX_AUX_CMD_I2C_WRITE</a> 0x0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#dfd4bbff847bf0c3a083fe6c05ecb626">XDPTX_AUX_CMD_I2C_READ</a> 0x1</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#25250484dd7954a6eb39889c74119de0">XDPTX_AUX_CMD_I2C_WRITE_STATUS</a> 0x2</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#807a8c6ccd715728a3caf292fb5df034">XDPTX_AUX_CMD_I2C_WRITE_MOT</a> 0x4</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#92c34660206277eaf2dcefd505ac4537">XDPTX_AUX_CMD_I2C_READ_MOT</a> 0x5</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#5466247825ee799cc7faf452f63d29f3">XDPTX_AUX_CMD_I2C_WRITE_STATUS_MOT</a> 0x6</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#4b2805752a412e73833779c41cb4f17b">XDPTX_AUX_CMD_WRITE</a> 0x8</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#1836926b53df692b59876306435c7d03">XDPTX_AUX_CMD_READ</a> 0x9</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#420d72406cb1b8421237aac5655528e1">XDPTX_AUX_CMD_ADDR_ONLY_TRANSFER_EN</a> 0x00001000</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#8819e8da1e6aa14d99c7d73d29e863bc">XDPTX_AUX_CLK_DIVIDER_VAL_MASK</a> 0x0000000F</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#b889c393389b474415c281874cd1ae28">XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK</a> 0x00000F00</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#669e3215c0f00e476f26e18bd94369af">XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT</a> 8</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#97bafe03ef5703095f172353e91b1b9c">XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK</a> 0x00000001</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#4798b0b7e9252a02809e2e41a3a21f3f">XDPTX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK</a> 0x00000002</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#bc637346b936c9495ff5df3e472473e8">XDPTX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK</a> 0x00000004</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#9e0d33482951f4d8e7aeaaeefb195470">XDPTX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK</a> 0x00000008</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#6eca179bae00fac66c5f8a30adf7de32">XDPTX_AUX_REPLY_CODE_ACK</a> 0x0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#daa9483abbaa31663bf8899d9f01c2c1">XDPTX_AUX_REPLY_CODE_I2C_ACK</a> 0x0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#dbd3cf045752bbc663eaf2f3accc8817">XDPTX_AUX_REPLY_CODE_NACK</a> 0x1</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#9693f57d4148d21319e1eecd3a18b1e1">XDPTX_AUX_REPLY_CODE_DEFER</a> 0x2</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#9cc1c08d4d0747a7dfc076ada0549305">XDPTX_AUX_REPLY_CODE_I2C_NACK</a> 0x4</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#d57160df752279c8ab85ac993198e8d9">XDPTX_AUX_REPLY_CODE_I2C_DEFER</a> 0x8</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#283c90a2f0c3f04323effb5a07471bd8">XDPTX_INTERRUPT_STATUS_HPD_IRQ_MASK</a> 0x00000001</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#61e1f96b8cf7d48ed558849370894d2c">XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK</a> 0x00000002</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#82f787c0109ef901db1b7d6145d566fb">XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK</a> 0x00000004</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#f30bec15befd3e0c2fbbeebbfbb8f9a1">XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK</a> 0x00000008</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#88b6d5d033b66d8691fb8c4366b0a86e">XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK</a> 0x00000010</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#dc4b6a9b2f4535d439bf0aefc809a778">XDPTX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK</a> 0x00000020</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#342fbd216da88f57d452b7612f75e309">XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK</a> 0x00000001</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#9712eee88e7dcaf4fe5662c3fa189880">XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK</a> 0x00000002</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#c7ce69287202628c1a776ac652c1fb6a">XDPTX_INTERRUPT_MASK_REPLY_RECEIVED_MASK</a> 0x00000004</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#cfab396c7df81acf9057f20707367be2">XDPTX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK</a> 0x00000008</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#eb049a92f1acc648fc5b3a7262f3e277">XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK</a> 0x00000010</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#7a43357c2c39e14a30c127775906b93e">XDPTX_INTERRUPT_MASK_EXT_PKT_TXD_MASK</a> 0x00000020</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#763daa97667f07ffbd3c94eef9e0f5aa">XDPTX_REPLY_STATUS_REPLY_RECEIVED_MASK</a> 0x00000001</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#1ca3f1ab7e3d36698fd1eb723e3974b6">XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK</a> 0x00000002</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#3a890eeacb3f8acfd9202413cb04ca8b">XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK</a> 0x00000004</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#6a56b5d431c98ea5b2ba0370dcded113">XDPTX_REPLY_STATUS_REPLY_ERROR_MASK</a> 0x00000008</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#ee67e335775bd954e6509576977e45be">XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_MASK</a> 0x00000FF0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#be3af3d8dab5f5fe9127a6d0681fce30">XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT</a> 4</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#2eaf9f11789d40c04fb868b0d8c80319">XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK</a> 0x00000001</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#b175eaedce85c047e38e6ff17d9d45fe">XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK</a> 0x00000002</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#1a50b240b33c499a4271db5ee4d4bb62">XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT</a> 1</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#a4ee76b5454cd8392610ed7a06ce2193">XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK</a> 0x00000001</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#3306278e2b87c95f0ae63974d7a56d84">XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK</a> 0x00000006</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#6e5f82be31861955b92a8a42658dfb42">XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT</a> 1</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#eb6dd490bad27ce5ad098e46ad4111d3">XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK</a> 0x00000008</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#661865c7d99aa8f711358bff3d833637">XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT</a> 3</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#9f138b31437fa297ba83d4f01f21f73c">XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK</a> 0x00000010</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#1177e0fd748b9418cb31ddc1b7169e41">XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT</a> 4</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#6c60d2c05b864c6a49ea6876e31db142">XDPTX_MAIN_STREAMX_MISC0_BDC_MASK</a> 0x000000E0</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#e7e4bc849d33b98ff35a9f4e2f6ea62b">XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT</a> 5</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#f802c8609a40622525ca35cdfb28c4f3">XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK</a> 0x00000001</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#d977ec41edb1df1927260b06a67b4722">XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK</a> 0x00000006</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#e1cde89ba2f6c3fdcef7fc5e8aa9c1d9">XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT</a> 1</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#4d6874faa811cb8d358248cd4ae0f011">XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK</a> 0x0010000</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#66bf9327b2f5c4d4d6b26025e59b4d36">XDPTX_PHY_CONFIG_PHY_RESET_MASK</a> 0x0010001</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#845b6767c137fa2f95b7015d806cff8c">XDPTX_PHY_CONFIG_GTTX_RESET_MASK</a> 0x0010002</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#e0a33037770384173f8c3bc28186c566">XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK</a> 0x0010100</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#7c229eef22f7effcbed81403a683e9b2">XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK</a> 0x0010200</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#ce37aefbbab4d22b4799d8dd39297a9e">XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK</a> 0x0010400</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#b887bdc93d976cd87cc6c0f057fb8558">XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK</a> 0x0011000</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#15fd7d4ca93314bb32381adc0a2b3885">XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK</a> 0x001E000</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#1ee16a2b678d6cc1546a8bf902bb7c89">XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK</a> 0x0010003</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#6ac3cdf80aaf65cf24bfe278100da978">XDPTX_PHY_CLOCK_SELECT_162GBPS</a> 0x1</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#8cac44ea4f4829449e1264b25750c7ac">XDPTX_PHY_CLOCK_SELECT_270GBPS</a> 0x3</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#9485063d8eff980d1a49baf0f07e45cf">XDPTX_PHY_CLOCK_SELECT_540GBPS</a> 0x5</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#f359f44b5d2763ed0536e9a89d2771e0">XDPTX_VS_LEVEL_0</a> 0x2</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#bd02990d70c63a0b7598fcb6ce1b867e">XDPTX_VS_LEVEL_1</a> 0x5</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#e0a4c903dcc0de3fd56378ea721534a2">XDPTX_VS_LEVEL_2</a> 0x8</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#5d28772a94530d91c12e8aa054380280">XDPTX_VS_LEVEL_3</a> 0xF</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#7852023a12302535fd5aef02adf966a2">XDPTX_VS_LEVEL_OFFSET</a> 0x4</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#19051dad4d1c1c265327291bfe33ad94">XDPTX_PE_LEVEL_0</a> 0x00</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#4f3feed57f50675f0965ac1c1146d616">XDPTX_PE_LEVEL_1</a> 0x0E</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#ba543f6ecab546207f84032b4c338bb6">XDPTX_PE_LEVEL_2</a> 0x14</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#aac90ae320ce119fa0ea0a49d0eccbc6">XDPTX_PE_LEVEL_3</a> 0x1B</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#a4ce045c9d26a9b77376c6806d639830">XDPTX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK</a> 0x00000003</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#17fcce23d900de4708b5bf9120b785a4">XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK</a> 0x0000000C</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#c3e7d53ee9205ba8a1c522398a47e160">XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK</a> 0x00000010</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#2300cd50a0b23cb2f52ee91e1be2c9e8">XDPTX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK</a> 0x00000020</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#a25c98082d5eee6d6e311d68467b64a0">XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK</a> 0x00000020</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#00d5b32392d1c89ed0c4daf09f9161ab">XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK</a> 0x00030000</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#886dba9465eac92595f45a13bedc5b3d">XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT</a> 16</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#7a585a1375bd0679925e4de48c3bf1a0">XDPTX_PHY_STATUS_TX_ERROR_LANE_0_MASK</a> 0x000C0000</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#e6bfe8d2903cd48c7af1d3e0c9ce4d40">XDPTX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT</a> 18</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#a3d8c074bbf11cf62abcf387fdc66b45">XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK</a> 0x00300000</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#96b4be332f8a4c4b588f733f50977b1a">XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT</a> 20</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#ee437175211f97081b831d0ad3c89d44">XDPTX_PHY_STATUS_TX_ERROR_LANE_1_MASK</a> 0x00C00000</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#e14ada4aa4ae075a05e45fa19df859be">XDPTX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT</a> 22</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#bf9d5735d3057d83ebc0fbb88a5fb0b8">XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK</a> 0x03000000</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#3c2331a45bc9e1826e3ba530fd0457a8">XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT</a> 24</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#51fa6263682e7fc7480dd9906827ece6">XDPTX_PHY_STATUS_TX_ERROR_LANE_2_MASK</a> 0x0C000000</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#767df1a30d971c2c0c2995678fc6082a">XDPTX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT</a> 26</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#e2fc6f4cf25bd93b2dce7982c5fd74bc">XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK</a> 0x30000000</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#af9fe61b50e185574b688a501c44a3ab">XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT</a> 28</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#5c43185dc4229494b406dc0bcaacbd93">XDPTX_PHY_STATUS_TX_ERROR_LANE_3_MASK</a> 0xC0000000</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#2cc33338ea15b08e0ce0525a07ebca04">XDPTX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT</a> 30</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#9efe7932d92c6d29ebad9f04638a93bd">XDPTX_PHY_STATUS_ALL_LANES_READY_MASK</a> 0x0000003F</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#71984c5e6a07054b91b40b96cee3a75f">XDPTX_GT_DRP_COMMAND_DRP_ADDR_MASK</a> 0x000F</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#33a926f9648fed96fbae39b04ba6ff0f">XDPTX_GT_DRP_COMMAND_DRP_RW_CMD_MASK</a> 0x0080</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#a3bef14c6a38acb99fb84d734237d79d">XDPTX_GT_DRP_COMMAND_DRP_W_DATA_MASK</a> 0xFF00</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#e65f3ee3bc014d237e1d62ef84fc4a6b">XDPTX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT</a> 16</td></tr>
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<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#011ee90104e02971fe66441090536110">XDPTX_VC_PAYLOAD_BUFFER_ADDR</a> 0x0800</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#b9ae114efe97122a7a212baf3a27d5fe">XDptx_ReadReg</a>(BaseAddress, RegOffset) XDptx_In32((BaseAddress) + (RegOffset))</td></tr>
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<tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="xdptx__hw_8h.html#740519ee4cc95e492351ad8cf9085632">XDptx_WriteReg</a>(BaseAddress, RegOffset, Data) XDptx_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
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</table>
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<hr><h2>Define Documentation</h2>
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<a class="anchor" name="f52ee8f253e0d90f456e57b99956d39b"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_ADDRESS" ref="f52ee8f253e0d90f456e57b99956d39b" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<td class="memname">#define XDPTX_AUX_ADDRESS 0x0108 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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Specifies the address of current AUX command.
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</div>
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</div><p>
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<a class="anchor" name="bf2869e5451d401fcaefafc818884742"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_CLK_DIVIDER" ref="bf2869e5451d401fcaefafc818884742" args="" -->
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<div class="memitem">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_AUX_CLK_DIVIDER 0x010C </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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Clock divider value for generating the internal 1MHz clock.
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</div>
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</div><p>
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<a class="anchor" name="b889c393389b474415c281874cd1ae28"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK" ref="b889c393389b474415c281874cd1ae28" args="" -->
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<div class="memitem">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0x00000F00 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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|
AUX (noise) signal width filter.
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|
</div>
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</div><p>
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|
<a class="anchor" name="669e3215c0f00e476f26e18bd94369af"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT" ref="669e3215c0f00e476f26e18bd94369af" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT 8 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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|
Shift bits for AUX signal width filter.
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|
</div>
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|
</div><p>
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|
<a class="anchor" name="8819e8da1e6aa14d99c7d73d29e863bc"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_CLK_DIVIDER_VAL_MASK" ref="8819e8da1e6aa14d99c7d73d29e863bc" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_AUX_CLK_DIVIDER_VAL_MASK 0x0000000F </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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|
Clock divider value.
|
|
</div>
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|
</div><p>
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|
<a class="anchor" name="ca3cbd1da75b9c1ad84c29caa94aa1c6"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_CMD" ref="ca3cbd1da75b9c1ad84c29caa94aa1c6" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_AUX_CMD 0x0100 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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|
Initiates AUX commands.
|
|
</div>
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|
</div><p>
|
|
<a class="anchor" name="420d72406cb1b8421237aac5655528e1"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_CMD_ADDR_ONLY_TRANSFER_EN" ref="420d72406cb1b8421237aac5655528e1" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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|
<td class="memname">#define XDPTX_AUX_CMD_ADDR_ONLY_TRANSFER_EN 0x00001000 </td>
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</tr>
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</table>
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|
</div>
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<div class="memdoc">
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<p>
|
|
Address only transfer enable (STOP will be sent after command).
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="dfd4bbff847bf0c3a083fe6c05ecb626"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_CMD_I2C_READ" ref="dfd4bbff847bf0c3a083fe6c05ecb626" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_AUX_CMD_I2C_READ 0x1 </td>
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</tr>
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</table>
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|
</div>
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|
<div class="memdoc">
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<p>
|
|
I2C-over-AUX read command.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="92c34660206277eaf2dcefd505ac4537"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_CMD_I2C_READ_MOT" ref="92c34660206277eaf2dcefd505ac4537" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_AUX_CMD_I2C_READ_MOT 0x5 </td>
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</tr>
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</table>
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|
</div>
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|
<div class="memdoc">
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|
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<p>
|
|
I2C-over-AUX read MOT (middle-of-transaction) command.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="2b914586da1b26b29fa11aec81b6b2e3"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_CMD_I2C_WRITE" ref="2b914586da1b26b29fa11aec81b6b2e3" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_AUX_CMD_I2C_WRITE 0x0 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
|
|
I2C-over-AUX write command.
|
|
</div>
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|
</div><p>
|
|
<a class="anchor" name="807a8c6ccd715728a3caf292fb5df034"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_CMD_I2C_WRITE_MOT" ref="807a8c6ccd715728a3caf292fb5df034" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_AUX_CMD_I2C_WRITE_MOT 0x4 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
|
|
I2C-over-AUX write MOT (middle-of-transaction) command.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="25250484dd7954a6eb39889c74119de0"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_CMD_I2C_WRITE_STATUS" ref="25250484dd7954a6eb39889c74119de0" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_AUX_CMD_I2C_WRITE_STATUS 0x2 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
|
|
I2C-over-AUX write status command.
|
|
</div>
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|
</div><p>
|
|
<a class="anchor" name="5466247825ee799cc7faf452f63d29f3"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_CMD_I2C_WRITE_STATUS_MOT" ref="5466247825ee799cc7faf452f63d29f3" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_AUX_CMD_I2C_WRITE_STATUS_MOT 0x6 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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|
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<p>
|
|
I2C-over-AUX write status MOT (middle-of- transaction) command.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="e38656cb5fe9c89ec42fc4d0a8b74174"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_CMD_MASK" ref="e38656cb5fe9c89ec42fc4d0a8b74174" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_AUX_CMD_MASK 0x00000F00 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
|
|
AUX command.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="b3699ad8b3dffb732877d1b003777470"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK" ref="b3699ad8b3dffb732877d1b003777470" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK 0x0000000F </td>
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</tr>
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</table>
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</div>
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|
<div class="memdoc">
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|
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<p>
|
|
Number of bytes to transfer with the current AUX command.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="1836926b53df692b59876306435c7d03"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_CMD_READ" ref="1836926b53df692b59876306435c7d03" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_AUX_CMD_READ 0x9 </td>
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</tr>
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</table>
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|
</div>
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<div class="memdoc">
|
|
|
|
<p>
|
|
AUX read command.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="7ac3c631d9e567afb2466c5a50f103da"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_CMD_SHIFT" ref="7ac3c631d9e567afb2466c5a50f103da" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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|
<tr>
|
|
<td class="memname">#define XDPTX_AUX_CMD_SHIFT 8 </td>
|
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</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for command.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="4b2805752a412e73833779c41cb4f17b"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_CMD_WRITE" ref="4b2805752a412e73833779c41cb4f17b" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
|
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<td class="memname">#define XDPTX_AUX_CMD_WRITE 0x8 </td>
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</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
AUX write command.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="8680af673f3229e41eca23d54f4dbbed"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_REPLY_CODE" ref="8680af673f3229e41eca23d54f4dbbed" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
|
|
<td class="memname">#define XDPTX_AUX_REPLY_CODE 0x0138 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Reply code received from the most recent AUX command.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="6eca179bae00fac66c5f8a30adf7de32"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_REPLY_CODE_ACK" ref="6eca179bae00fac66c5f8a30adf7de32" args="" -->
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<div class="memitem">
|
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<div class="memproto">
|
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<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_AUX_REPLY_CODE_ACK 0x0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
AUX command ACKed.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="9693f57d4148d21319e1eecd3a18b1e1"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_REPLY_CODE_DEFER" ref="9693f57d4148d21319e1eecd3a18b1e1" args="" -->
|
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<div class="memitem">
|
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<div class="memproto">
|
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<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_AUX_REPLY_CODE_DEFER 0x2 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
AUX command deferred.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="daa9483abbaa31663bf8899d9f01c2c1"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_REPLY_CODE_I2C_ACK" ref="daa9483abbaa31663bf8899d9f01c2c1" args="" -->
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<div class="memitem">
|
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<div class="memproto">
|
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<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_AUX_REPLY_CODE_I2C_ACK 0x0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
I2C-over-AUX command not ACKed.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="d57160df752279c8ab85ac993198e8d9"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_REPLY_CODE_I2C_DEFER" ref="d57160df752279c8ab85ac993198e8d9" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
|
|
<td class="memname">#define XDPTX_AUX_REPLY_CODE_I2C_DEFER 0x8 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
I2C-over-AUX command deferred.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="9cc1c08d4d0747a7dfc076ada0549305"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_REPLY_CODE_I2C_NACK" ref="9cc1c08d4d0747a7dfc076ada0549305" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_AUX_REPLY_CODE_I2C_NACK 0x4 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
I2C-over-AUX command not ACKed.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="dbd3cf045752bbc663eaf2f3accc8817"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_REPLY_CODE_NACK" ref="dbd3cf045752bbc663eaf2f3accc8817" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_AUX_REPLY_CODE_NACK 0x1 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
AUX command not ACKed.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="8e8272c15321880111c6a5c253a21d5a"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_REPLY_COUNT" ref="8e8272c15321880111c6a5c253a21d5a" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_AUX_REPLY_COUNT 0x013C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of reply transactions receieved over AUX.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="c3a7fc3419105d0db69c67ba2b48a1d5"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_REPLY_DATA" ref="c3a7fc3419105d0db69c67ba2b48a1d5" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_AUX_REPLY_DATA 0x0134 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Reply data received during the AUX reply.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="17b9eb2badecaf2e252834db0e9fb454"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_AUX_WRITE_FIFO" ref="17b9eb2badecaf2e252834db0e9fb454" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_AUX_WRITE_FIFO 0x0104 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Write data for the current AUX command.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="fe16c5bc7cdf55f7851c23e27e0fad65"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_CORE_ID" ref="fe16c5bc7cdf55f7851c23e27e0fad65" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_CORE_ID 0x00FC </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
DisplayPort revision.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="2c7093b7bf7dea2056c9225d82af1ee5"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_CORE_ID_DP_MJR_VER_MASK" ref="2c7093b7bf7dea2056c9225d82af1ee5" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_CORE_ID_DP_MJR_VER_MASK 0x0000F000 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
DisplayPort protocol major version.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="b043766862fa12d137764416ee8ce9f1"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_CORE_ID_DP_MJR_VER_SHIFT" ref="b043766862fa12d137764416ee8ce9f1" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_CORE_ID_DP_MJR_VER_SHIFT 24 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for DisplayPort protocol major version.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="599eff5e2d775c9eef905351446d23d5"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_CORE_ID_DP_MNR_VER_MASK" ref="599eff5e2d775c9eef905351446d23d5" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_CORE_ID_DP_MNR_VER_MASK 0x00000F00 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
DisplayPort protocol minor version.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="79e16c199c23e4bde7d3abbcfd6c3fbf"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_CORE_ID_DP_MNR_VER_SHIFT" ref="79e16c199c23e4bde7d3abbcfd6c3fbf" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_CORE_ID_DP_MNR_VER_SHIFT 16 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for DisplayPort protocol major version.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="4849053e05562d60e19e26bb5d2fb843"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_CORE_ID_DP_REV_MASK" ref="4849053e05562d60e19e26bb5d2fb843" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_CORE_ID_DP_REV_MASK 0x000000F0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
DisplayPort protocol revision.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="268fa71b51b61450b7422ddce2b2e6df"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_CORE_ID_DP_REV_SHIFT" ref="268fa71b51b61450b7422ddce2b2e6df" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_CORE_ID_DP_REV_SHIFT 8 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for DisplayPort protocol revision.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="768c41baf0f19de032e8951f606a0dcf"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_CORE_ID_TYPE_MASK" ref="768c41baf0f19de032e8951f606a0dcf" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_CORE_ID_TYPE_MASK 0x0000000F </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Core type.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="fc831ef5eb6d5ac9eec6537478ade75d"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_CORE_ID_TYPE_RX" ref="fc831ef5eb6d5ac9eec6537478ade75d" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_CORE_ID_TYPE_RX 0x1 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Core is a receiver.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="a3286f7a30712bf5556860deb2165c9e"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_CORE_ID_TYPE_TX" ref="a3286f7a30712bf5556860deb2165c9e" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_CORE_ID_TYPE_TX 0x0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Core is a transmitter.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="dadb6bd439c17cd13d8fa0fc9ac5187d"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_DOWNSPREAD_CTRL" ref="dadb6bd439c17cd13d8fa0fc9ac5187d" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_DOWNSPREAD_CTRL 0x0018 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Enable a 0.5% spreading of the clock.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="59794e061554b270d02fad1a8aaa37a3"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_ENABLE" ref="59794e061554b270d02fad1a8aaa37a3" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_ENABLE 0x0080 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Enable the basic operations of the transmitter or output stuffing symbols if disabled.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="191c735a2ebed97d890953adcdec2d39"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_ENABLE_MAIN_STREAM" ref="191c735a2ebed97d890953adcdec2d39" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_ENABLE_MAIN_STREAM 0x0084 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Enable transmission of main link video info.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="73580ca967b5973c7e1fbce580863441"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_ENABLE_SEC_STREAM" ref="73580ca967b5973c7e1fbce580863441" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_ENABLE_SEC_STREAM 0x0088 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Enable the transmission of secondary link info.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="2505aad381cb4ca9d1c970523229934b"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_ENHANCED_FRAME_EN" ref="2505aad381cb4ca9d1c970523229934b" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_ENHANCED_FRAME_EN 0x0008 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Enable enhanced framing symbol sequence.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="5217c3a80875b6dcda385d57c2116551"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_FORCE_SCRAMBLER_RESET" ref="5217c3a80875b6dcda385d57c2116551" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_FORCE_SCRAMBLER_RESET 0x00C0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Force a scrambler reset.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="95e419cf6d2c09a29e29584e26120376"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_FRAC_BYTES_PER_TU" ref="95e419cf6d2c09a29e29584e26120376" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_FRAC_BYTES_PER_TU 0x01C8 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register value.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="fddde4423debc9ec29910b1ed3facbaa"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_FRAC_BYTES_PER_TU_STREAM2" ref="fddde4423debc9ec29910b1ed3facbaa" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_FRAC_BYTES_PER_TU_STREAM2 0x0548 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register value.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="ffd96279b5c5adbdc828494d8874cb1f"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_FRAC_BYTES_PER_TU_STREAM3" ref="ffd96279b5c5adbdc828494d8874cb1f" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_FRAC_BYTES_PER_TU_STREAM3 0x0598 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register value.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="1d5749c5e5ab95ab3fd450948314cb1c"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_FRAC_BYTES_PER_TU_STREAM4" ref="1d5749c5e5ab95ab3fd450948314cb1c" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_FRAC_BYTES_PER_TU_STREAM4 0x05E8 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
The fractional component when calculated the XDPTX_MIN_BYTES_PER_TU register value.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="a20e3869a077ed56257240989c3afcc3"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_GT_DRP_CHANNEL_STATUS" ref="a20e3869a077ed56257240989c3afcc3" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_GT_DRP_CHANNEL_STATUS 0x02A8 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Provides access to GT DRP channel status.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="08e43a348bf05477f71646320ab41ddd"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_GT_DRP_COMMAND" ref="08e43a348bf05477f71646320ab41ddd" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_GT_DRP_COMMAND 0x02A0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Provides acces to the GT DRP ports.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="71984c5e6a07054b91b40b96cee3a75f"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_GT_DRP_COMMAND_DRP_ADDR_MASK" ref="71984c5e6a07054b91b40b96cee3a75f" args="" -->
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<div class="memitem">
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|
<div class="memproto">
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|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_GT_DRP_COMMAND_DRP_ADDR_MASK 0x000F </td>
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|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
DRP address.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="33a926f9648fed96fbae39b04ba6ff0f"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_GT_DRP_COMMAND_DRP_RW_CMD_MASK" ref="33a926f9648fed96fbae39b04ba6ff0f" args="" -->
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|
<div class="memitem">
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|
<div class="memproto">
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|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_GT_DRP_COMMAND_DRP_RW_CMD_MASK 0x0080 </td>
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|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
DRP read/write command (Read=0, Write=1).
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="a3bef14c6a38acb99fb84d734237d79d"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_GT_DRP_COMMAND_DRP_W_DATA_MASK" ref="a3bef14c6a38acb99fb84d734237d79d" args="" -->
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|
<div class="memitem">
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|
<div class="memproto">
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|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_MASK 0xFF00 </td>
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|
</tr>
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|
</table>
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|
</div>
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|
<div class="memdoc">
|
|
|
|
<p>
|
|
DRP write data.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="e65f3ee3bc014d237e1d62ef84fc4a6b"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT" ref="e65f3ee3bc014d237e1d62ef84fc4a6b" args="" -->
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<div class="memitem">
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|
<div class="memproto">
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|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT 16 </td>
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|
</tr>
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|
</table>
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|
</div>
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|
<div class="memdoc">
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|
|
|
<p>
|
|
Shift bits for DRP write data.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="a6cde0bad8b7159e38fa7355fada8de2"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_GT_DRP_READ_DATA" ref="a6cde0bad8b7159e38fa7355fada8de2" args="" -->
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<div class="memitem">
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<div class="memproto">
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|
<table class="memname">
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|
<tr>
|
|
<td class="memname">#define XDPTX_GT_DRP_READ_DATA 0x02A4 </td>
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</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Provides access to GT DRP read data.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="17f41514d28ecba0cd98d2e3605c725c"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_HPD_DURATION" ref="17f41514d28ecba0cd98d2e3605c725c" args="" -->
|
|
<div class="memitem">
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|
<div class="memproto">
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|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_HPD_DURATION 0x0150 </td>
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|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Duration of the HPD pulse in microseconds.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="5a2bc7766152ab752d2a3821c439740f"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INIT_WAIT" ref="5a2bc7766152ab752d2a3821c439740f" args="" -->
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|
<div class="memitem">
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|
<div class="memproto">
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|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INIT_WAIT 0x01CC </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="ccf526ba0e103be0995dedca80048c02"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INIT_WAIT_STREAM2" ref="ccf526ba0e103be0995dedca80048c02" args="" -->
|
|
<div class="memitem">
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|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INIT_WAIT_STREAM2 0x054C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="d70718dd1cc46d29e49075d2b627f5d5"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INIT_WAIT_STREAM3" ref="d70718dd1cc46d29e49075d2b627f5d5" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INIT_WAIT_STREAM3 0x059C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="fe33b3121271a205a639b915ef818f8e"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INIT_WAIT_STREAM4" ref="fe33b3121271a205a639b915ef818f8e" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INIT_WAIT_STREAM4 0x05EC </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="27c315c49cfa0c9659403e5378cf3acb"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_MASK" ref="27c315c49cfa0c9659403e5378cf3acb" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_MASK 0x0144 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Masks the specified interrupt sources.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="7a43357c2c39e14a30c127775906b93e"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_MASK_EXT_PKT_TXD_MASK" ref="7a43357c2c39e14a30c127775906b93e" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_MASK_EXT_PKT_TXD_MASK 0x00000020 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Mask extended packet transmit interrupt.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="9712eee88e7dcaf4fe5662c3fa189880"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK" ref="9712eee88e7dcaf4fe5662c3fa189880" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK 0x00000002 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Mask HPD event interrupt.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="342fbd216da88f57d452b7612f75e309"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK" ref="342fbd216da88f57d452b7612f75e309" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK 0x00000001 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Mask HPD IRQ interrupt.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="eb049a92f1acc648fc5b3a7262f3e277"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK" ref="eb049a92f1acc648fc5b3a7262f3e277" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK 0x00000010 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Mask HPD pulse detected interrupt.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="c7ce69287202628c1a776ac652c1fb6a"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_MASK_REPLY_RECEIVED_MASK" ref="c7ce69287202628c1a776ac652c1fb6a" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_MASK_REPLY_RECEIVED_MASK 0x00000004 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Mask reply received interrupt.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="cfab396c7df81acf9057f20707367be2"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK" ref="cfab396c7df81acf9057f20707367be2" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK 0x00000008 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Mask reply received interrupt.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="0f779ac12934252a5548f520e776b1e8"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_SIG_STATE" ref="0f779ac12934252a5548f520e776b1e8" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_SIG_STATE 0x0130 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
The raw signal values for interupt events.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="97bafe03ef5703095f172353e91b1b9c"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK" ref="97bafe03ef5703095f172353e91b1b9c" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK 0x00000001 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Raw state of the HPD pin on the DP connector.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="bc637346b936c9495ff5df3e472473e8"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK" ref="bc637346b936c9495ff5df3e472473e8" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK 0x00000004 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
A reply is currently being received.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="9e0d33482951f4d8e7aeaaeefb195470"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK" ref="9e0d33482951f4d8e7aeaaeefb195470" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK 0x00000008 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
A reply timeout has occurred.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="4798b0b7e9252a02809e2e41a3a21f3f"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK" ref="4798b0b7e9252a02809e2e41a3a21f3f" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK 0x00000002 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
A request is currently being sent.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="2864b992eaaffb92419a1d5c4287553a"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_STATUS" ref="2864b992eaaffb92419a1d5c4287553a" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_STATUS 0x0140 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Status for interrupt events.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="dc4b6a9b2f4535d439bf0aefc809a778"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK" ref="dc4b6a9b2f4535d439bf0aefc809a778" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK 0x00000020 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Extended packet has been transmitted and the core is ready to accept a new packet.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="61e1f96b8cf7d48ed558849370894d2c"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK" ref="61e1f96b8cf7d48ed558849370894d2c" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK 0x00000002 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Detected the presence of the HPD signal.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="283c90a2f0c3f04323effb5a07471bd8"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_STATUS_HPD_IRQ_MASK" ref="283c90a2f0c3f04323effb5a07471bd8" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_STATUS_HPD_IRQ_MASK 0x00000001 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Detected an IRQ framed with the proper timing on the HPD signal.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="88b6d5d033b66d8691fb8c4366b0a86e"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK" ref="88b6d5d033b66d8691fb8c4366b0a86e" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK 0x00000010 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
A pulse on the HPD line was detected.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="82f787c0109ef901db1b7d6145d566fb"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK" ref="82f787c0109ef901db1b7d6145d566fb" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK 0x00000004 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
An AUX reply transaction has been detected.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="f30bec15befd3e0c2fbbeebbfbb8f9a1"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK" ref="f30bec15befd3e0c2fbbeebbfbb8f9a1" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK 0x00000008 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
A reply timeout has occurred.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="f0852cab2ae824fe3dfd71c8d093f143"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_LANE_COUNT_SET" ref="f0852cab2ae824fe3dfd71c8d093f143" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_LANE_COUNT_SET 0x0004 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Set lane count setting.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="5b1fe80c1adb3f1744a83f19854fb7b4"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_LINK_BW_SET" ref="5b1fe80c1adb3f1744a83f19854fb7b4" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_LINK_BW_SET 0x0000 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Set main link bandwidth setting.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="454eb694a138971aaa149fef42d861ab"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_LINK_BW_SET_162GBPS" ref="454eb694a138971aaa149fef42d861ab" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_LINK_BW_SET_162GBPS 0x06 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
1.62 Gbps link rate.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="566bc035e7e996a54088c06e6ba780c8"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_LINK_BW_SET_270GBPS" ref="566bc035e7e996a54088c06e6ba780c8" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_LINK_BW_SET_270GBPS 0x0A </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
2.70 Gbps link rate.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="65a9feaa560d6328003d8223407ec2ae"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_LINK_BW_SET_540GBPS" ref="65a9feaa560d6328003d8223407ec2ae" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_LINK_BW_SET_540GBPS 0x14 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
5.40 Gbps link rate.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="5359209ff45ece205f47013ac8f8b481"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_LINK_QUAL_PATTERN_SET" ref="5359209ff45ece205f47013ac8f8b481" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_LINK_QUAL_PATTERN_SET 0x0010 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Transmit the link quality pattern.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="b40635c4316ab7748efb0ba0fe32e571"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_LINK_QUAL_PATTERN_SET_D102_TEST" ref="b40635c4316ab7748efb0ba0fe32e571" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_LINK_QUAL_PATTERN_SET_D102_TEST 0x1 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
D10.2 unscrambled test pattern transmitted.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="8fb818d85a1d645a6d423b04e81998f5"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_LINK_QUAL_PATTERN_SET_OFF" ref="8fb818d85a1d645a6d423b04e81998f5" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_LINK_QUAL_PATTERN_SET_OFF 0x0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Link quality test pattern not transmitted.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="e2e63c51f29bff2ce1254d5ca84ec9d8"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_LINK_QUAL_PATTERN_SET_PRBS7" ref="e2e63c51f29bff2ce1254d5ca84ec9d8" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_LINK_QUAL_PATTERN_SET_PRBS7 0x3 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Pseudo random bit sequence 7 transmitted.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="a0719eccb59a1855439deefb105a67ed"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_LINK_QUAL_PATTERN_SET_SER_MES" ref="a0719eccb59a1855439deefb105a67ed" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_LINK_QUAL_PATTERN_SET_SER_MES 0x2 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Symbol error rate measurement pattern transmitted.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="a9bdd81b87727fd34d2a7980d3bb8024"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_M_VID" ref="a9bdd81b87727fd34d2a7980d3bb8024" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_M_VID 0x01AC </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="4acb1978e0041fc4022d497fd2520621"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_M_VID_STREAM2" ref="4acb1978e0041fc4022d497fd2520621" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_M_VID_STREAM2 0x052C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="b481b051aad87e35201d8300ea67057a"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_M_VID_STREAM3" ref="b481b051aad87e35201d8300ea67057a" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_M_VID_STREAM3 0x057C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="d9c92eb6bed17caa75b6fd5c15549956"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_M_VID_STREAM4" ref="d9c92eb6bed17caa75b6fd5c15549956" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_M_VID_STREAM4 0x05CC </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
M value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="6aa815567de15595bc2c907e09b8a1fe"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM2_HRES" ref="6aa815567de15595bc2c907e09b8a1fe" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM2_HRES 0x0514 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of active pixels per line (the horizontal resolution).
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="474d6c09bb8e6f09ca1449453cf4e8f0"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM2_HSTART" ref="474d6c09bb8e6f09ca1449453cf4e8f0" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM2_HSTART 0x051C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of clocks between the leading edge of the horizontal sync and the start of active data.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="966d622a53206dcba94f0641da0c81ae"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM2_HSWIDTH" ref="966d622a53206dcba94f0641da0c81ae" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM2_HSWIDTH 0x050C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Width of the horizontal sync pulse.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="ef48a266f054385cf86f912e126520d7"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM2_HTOTAL" ref="ef48a266f054385cf86f912e126520d7" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM2_HTOTAL 0x0500 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Total number of clocks in the horizontal framing period.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="48a0382a45befba184376efd909005d1"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM2_INTERLACED" ref="48a0382a45befba184376efd909005d1" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM2_INTERLACED 0x0540 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Video is interlaced.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="63e49897330f42a7e28d0f8d79af93ec"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM2_MISC0" ref="63e49897330f42a7e28d0f8d79af93ec" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM2_MISC0 0x0524 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Miscellaneous stream attributes.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="438879bd482fc4002babe1af5712d24f"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM2_MISC1" ref="438879bd482fc4002babe1af5712d24f" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM2_MISC1 0x0528 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Miscellaneous stream attributes.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="117649d7b694fab8be20c6a596b109ae"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM2_POLARITY" ref="117649d7b694fab8be20c6a596b109ae" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM2_POLARITY 0x0508 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Polarity for the video sync signals.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="f9324cd568ed4ed4b01fd3070f9f0e70"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM2_VRES" ref="f9324cd568ed4ed4b01fd3070f9f0e70" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM2_VRES 0x0518 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of active lines (the vertical resolution).
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="4319bb6f14f32430554c585cea30d2a5"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM2_VSTART" ref="4319bb6f14f32430554c585cea30d2a5" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM2_VSTART 0x0520 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of lines between the leading edge of the vertical sync and the first line of active data.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="f1fef5dcbfe789148efb369091ced173"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM2_VSWIDTH" ref="f1fef5dcbfe789148efb369091ced173" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM2_VSWIDTH 0x0510 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Width of the vertical sync pulse.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="bdcd20a010573d90375bd43f69f2ba54"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM2_VTOTAL" ref="bdcd20a010573d90375bd43f69f2ba54" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM2_VTOTAL 0x0504 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Total number of lines in the video frame.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="457a77ecbfd4772cc44a6b0132c06379"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM3_HRES" ref="457a77ecbfd4772cc44a6b0132c06379" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM3_HRES 0x0564 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of active pixels per line (the horizontal resolution).
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="c96c991c1e20c7c6ac77cca1604945a2"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM3_HSTART" ref="c96c991c1e20c7c6ac77cca1604945a2" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM3_HSTART 0x056C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of clocks between the leading edge of the horizontal sync and the start of active data.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="1923d5ab298ed485533719a2112da2eb"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM3_HSWIDTH" ref="1923d5ab298ed485533719a2112da2eb" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM3_HSWIDTH 0x055C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Width of the horizontal sync pulse.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="7f958ef8d238836c4029902c1351a3d8"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM3_HTOTAL" ref="7f958ef8d238836c4029902c1351a3d8" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM3_HTOTAL 0x0550 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Total number of clocks in the horizontal framing period.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="f1301d5b3d2776744c8096c5083b9c75"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM3_INTERLACED" ref="f1301d5b3d2776744c8096c5083b9c75" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM3_INTERLACED 0x0590 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Video is interlaced.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="9056a672a41e96f011682a7b6541d219"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM3_MISC0" ref="9056a672a41e96f011682a7b6541d219" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM3_MISC0 0x0574 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Miscellaneous stream attributes.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="b2932134b860b0ed96ae50c907992d12"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM3_MISC1" ref="b2932134b860b0ed96ae50c907992d12" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM3_MISC1 0x0578 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Miscellaneous stream attributes.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="2e913728d484fbac51da0d7890cb0b1e"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM3_POLARITY" ref="2e913728d484fbac51da0d7890cb0b1e" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM3_POLARITY 0x0558 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Polarity for the video sync signals.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="978d25b2362a197b9ca898269db79228"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM3_VRES" ref="978d25b2362a197b9ca898269db79228" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM3_VRES 0x0568 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of active lines (the vertical resolution).
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="1e882bb71e0c4fc28df7094eb71e9cb7"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM3_VSTART" ref="1e882bb71e0c4fc28df7094eb71e9cb7" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM3_VSTART 0x0570 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of lines between the leading edge of the vertical sync and the first line of active data.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="2e9c9ab94753ac98dda3c7c84f678745"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM3_VSWIDTH" ref="2e9c9ab94753ac98dda3c7c84f678745" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM3_VSWIDTH 0x0560 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Width of the vertical sync pulse.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="8a4a9ee1a554e468f8acd898a2a4f05e"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM3_VTOTAL" ref="8a4a9ee1a554e468f8acd898a2a4f05e" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM3_VTOTAL 0x0554 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Total number of lines in the video frame.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="6d5e7b6ddfbd7258d77faa3bc0ec64b4"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM4_HRES" ref="6d5e7b6ddfbd7258d77faa3bc0ec64b4" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM4_HRES 0x05B4 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of active pixels per line (the horizontal resolution).
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="2cdcc6a966f153d1c14575312e273b31"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM4_HSTART" ref="2cdcc6a966f153d1c14575312e273b31" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM4_HSTART 0x05BC </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of clocks between the leading edge of the horizontal sync and the start of active data.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="8e7819f37013442eddbcff048baec9dc"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM4_HSWIDTH" ref="8e7819f37013442eddbcff048baec9dc" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM4_HSWIDTH 0x05AC </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Width of the horizontal sync pulse.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="a02d8272a69befd5d7b975901f01c534"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM4_HTOTAL" ref="a02d8272a69befd5d7b975901f01c534" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM4_HTOTAL 0x05A0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Total number of clocks in the horizontal framing period.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="8c446424d4e5c3fdfe87526a96c2cbf2"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM4_INTERLACED" ref="8c446424d4e5c3fdfe87526a96c2cbf2" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM4_INTERLACED 0x05E0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Video is interlaced.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="b4bc0a28e5333428467362927a13cf0d"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM4_MISC0" ref="b4bc0a28e5333428467362927a13cf0d" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM4_MISC0 0x05C4 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Miscellaneous stream attributes.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="e37188c1160e0f759a89625f17d720ea"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM4_MISC1" ref="e37188c1160e0f759a89625f17d720ea" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM4_MISC1 0x05C8 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Miscellaneous stream attributes.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="312989efe8f3ba8290097d6846c8b5ef"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM4_POLARITY" ref="312989efe8f3ba8290097d6846c8b5ef" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM4_POLARITY 0x05A8 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Polarity for the video sync signals.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="1af1a6cb3951de2c9bf51956459813e7"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM4_VRES" ref="1af1a6cb3951de2c9bf51956459813e7" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM4_VRES 0x05B8 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of active lines (the vertical resolution).
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="7b1d7ad61f116016ec3b39d58d8c937a"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM4_VSTART" ref="7b1d7ad61f116016ec3b39d58d8c937a" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM4_VSTART 0x05C0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of lines between the leading edge of the vertical sync and the first line of active data.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="f6811d6467288d07aea07ce48b8d8580"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM4_VSWIDTH" ref="f6811d6467288d07aea07ce48b8d8580" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM4_VSWIDTH 0x05B0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Width of the vertical sync pulse.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="9322eed516b4bfa9ce46682242c4a69e"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM4_VTOTAL" ref="9322eed516b4bfa9ce46682242c4a69e" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM4_VTOTAL 0x05A4 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Total number of lines in the video frame.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="f7dbf65764896c37d62a1be149cae2f8"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM_HRES" ref="f7dbf65764896c37d62a1be149cae2f8" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM_HRES 0x0194 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of active pixels per line (the horizontal resolution).
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="6878375b4d3054a6438d6c120f7aee92"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM_HSTART" ref="6878375b4d3054a6438d6c120f7aee92" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM_HSTART 0x019C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of clocks between the leading edge of the horizontal sync and the start of active data.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="c68242b93975b27a4dd5f5424edca7c4"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM_HSWIDTH" ref="c68242b93975b27a4dd5f5424edca7c4" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM_HSWIDTH 0x018C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Width of the horizontal sync pulse.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="71148ad51c2dcde442f3661ac23b1c8a"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM_HTOTAL" ref="71148ad51c2dcde442f3661ac23b1c8a" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM_HTOTAL 0x0180 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Total number of clocks in the horizontal framing period.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="feb884273648457f2af0709b75df4928"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM_INTERLACED" ref="feb884273648457f2af0709b75df4928" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM_INTERLACED 0x01C0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Video is interlaced.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="ec12e1b6482a3af5aefc43344ed3bb3d"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM_MISC0" ref="ec12e1b6482a3af5aefc43344ed3bb3d" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM_MISC0 0x01A4 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Miscellaneous stream attributes.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="dae3820b7afc1aa4e0f71b6daad496a9"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM_MISC1" ref="dae3820b7afc1aa4e0f71b6daad496a9" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM_MISC1 0x01A8 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Miscellaneous stream attributes.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="5021184f173d31eaf40914c08aa67c70"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM_POLARITY" ref="5021184f173d31eaf40914c08aa67c70" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM_POLARITY 0x0188 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Polarity for the video sync signals.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="c4442cbc0e52f8ba741a7becd59b7264"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM_VRES" ref="c4442cbc0e52f8ba741a7becd59b7264" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM_VRES 0x0198 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of active lines (the vertical resolution).
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="59f96811362a03af568f526087d813c2"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM_VSTART" ref="59f96811362a03af568f526087d813c2" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM_VSTART 0x01A0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Number of lines between the leading edge of the vertical sync and the first line of active data.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="80c45e2a27ace9e4b0750311c0ef84a9"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM_VSWIDTH" ref="80c45e2a27ace9e4b0750311c0ef84a9" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM_VSWIDTH 0x0190 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Width of the vertical sync pulse.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="72ccb4478dc0844d4564fd883595894f"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAM_VTOTAL" ref="72ccb4478dc0844d4564fd883595894f" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAM_VTOTAL 0x0184 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Total number of lines in the video frame.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="6c60d2c05b864c6a49ea6876e31db142"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAMX_MISC0_BDC_MASK" ref="6c60d2c05b864c6a49ea6876e31db142" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAMX_MISC0_BDC_MASK 0x000000E0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Bit depth per color component (BDC).
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="e7e4bc849d33b98ff35a9f4e2f6ea62b"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT" ref="e7e4bc849d33b98ff35a9f4e2f6ea62b" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT 5 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for BDC.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="3306278e2b87c95f0ae63974d7a56d84"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK" ref="3306278e2b87c95f0ae63974d7a56d84" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK 0x00000006 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Component format.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="6e5f82be31861955b92a8a42658dfb42"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT" ref="6e5f82be31861955b92a8a42658dfb42" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT 1 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for component format.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="eb6dd490bad27ce5ad098e46ad4111d3"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK" ref="eb6dd490bad27ce5ad098e46ad4111d3" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK 0x00000008 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Dynamic range.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="661865c7d99aa8f711358bff3d833637"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT" ref="661865c7d99aa8f711358bff3d833637" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT 3 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for dynamic range.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="a4ee76b5454cd8392610ed7a06ce2193"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK" ref="a4ee76b5454cd8392610ed7a06ce2193" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK 0x00000001 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Synchronous clock.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="9f138b31437fa297ba83d4f01f21f73c"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK" ref="9f138b31437fa297ba83d4f01f21f73c" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK 0x00000010 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
YCbCr colorimetry.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="1177e0fd748b9418cb31ddc1b7169e41"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT" ref="1177e0fd748b9418cb31ddc1b7169e41" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT 4 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for YCbCr colorimetry.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="f802c8609a40622525ca35cdfb28c4f3"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK" ref="f802c8609a40622525ca35cdfb28c4f3" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK 0x00000001 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Interlaced vertical total even.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="d977ec41edb1df1927260b06a67b4722"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK" ref="d977ec41edb1df1927260b06a67b4722" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK 0x00000006 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Stereo video attribute.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="e1cde89ba2f6c3fdcef7fc5e8aa9c1d9"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT" ref="e1cde89ba2f6c3fdcef7fc5e8aa9c1d9" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT 1 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for stereo video attribute.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="2eaf9f11789d40c04fb868b0d8c80319"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK" ref="2eaf9f11789d40c04fb868b0d8c80319" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK 0x00000001 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Polarity of the horizontal sync pulse.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="b175eaedce85c047e38e6ff17d9d45fe"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK" ref="b175eaedce85c047e38e6ff17d9d45fe" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK 0x00000002 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Polarity of the vertical sync pulse.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="1a50b240b33c499a4271db5ee4d4bb62"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT" ref="1a50b240b33c499a4271db5ee4d4bb62" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT 1 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for polarity of the vertical sync pulse.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="c0d71f16f11b0debe9e20c47442208bf"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MIN_BYTES_PER_TU" ref="c0d71f16f11b0debe9e20c47442208bf" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MIN_BYTES_PER_TU 0x01C4 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
The minimum number of bytes per transfer unit.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="f8f0c17ce672e22823f9491d01ad7ec1"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MIN_BYTES_PER_TU_STREAM2" ref="f8f0c17ce672e22823f9491d01ad7ec1" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MIN_BYTES_PER_TU_STREAM2 0x0544 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
The minimum number of bytes per transfer unit.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="32b32343be316740cb86394cf2e08c26"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MIN_BYTES_PER_TU_STREAM3" ref="32b32343be316740cb86394cf2e08c26" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MIN_BYTES_PER_TU_STREAM3 0x0594 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
The minimum number of bytes per transfer unit.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="d8c7d9f06d6216deb311df6d729e7d88"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_MIN_BYTES_PER_TU_STREAM4" ref="d8c7d9f06d6216deb311df6d729e7d88" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_MIN_BYTES_PER_TU_STREAM4 0x05E4 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
The minimum number of bytes per transfer unit.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="246df330b0d3f6ea5d05fd95089e9f99"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_N_VID" ref="246df330b0d3f6ea5d05fd95089e9f99" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_N_VID 0x01B4 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="2f2bdba8ccff7ceb3dd204aa3e5ac431"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_N_VID_STREAM2" ref="2f2bdba8ccff7ceb3dd204aa3e5ac431" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_N_VID_STREAM2 0x0534 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="3611385c5f33e89665600ec184379a64"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_N_VID_STREAM3" ref="3611385c5f33e89665600ec184379a64" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_N_VID_STREAM3 0x0584 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="9f7111b1c39155300faa506156766c11"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_N_VID_STREAM4" ref="9f7111b1c39155300faa506156766c11" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_N_VID_STREAM4 0x05D4 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
N value for the video stream as computed by the source core in asynchronous clock mode. Must be written in synchronous mode.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="19051dad4d1c1c265327291bfe33ad94"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PE_LEVEL_0" ref="19051dad4d1c1c265327291bfe33ad94" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PE_LEVEL_0 0x00 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Pre-emphasis level 0.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="4f3feed57f50675f0965ac1c1146d616"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PE_LEVEL_1" ref="4f3feed57f50675f0965ac1c1146d616" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PE_LEVEL_1 0x0E </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Pre-emphasis level 1.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="ba543f6ecab546207f84032b4c338bb6"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PE_LEVEL_2" ref="ba543f6ecab546207f84032b4c338bb6" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PE_LEVEL_2 0x14 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Pre-emphasis level 2.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="aac90ae320ce119fa0ea0a49d0eccbc6"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PE_LEVEL_3" ref="aac90ae320ce119fa0ea0a49d0eccbc6" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PE_LEVEL_3 0x1B </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Pre-emphasis level 3.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="be90ee3d19c62383bbfc51ac5dabc96f"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_CLOCK_SELECT" ref="be90ee3d19c62383bbfc51ac5dabc96f" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_CLOCK_SELECT 0x0234 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Instructs the PHY PLL to generate the proper clock frequency for the required link rate.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="6ac3cdf80aaf65cf24bfe278100da978"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_CLOCK_SELECT_162GBPS" ref="6ac3cdf80aaf65cf24bfe278100da978" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_CLOCK_SELECT_162GBPS 0x1 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
1.62 Gbps link.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="8cac44ea4f4829449e1264b25750c7ac"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_CLOCK_SELECT_270GBPS" ref="8cac44ea4f4829449e1264b25750c7ac" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_CLOCK_SELECT_270GBPS 0x3 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
2.70 Gbps link.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="9485063d8eff980d1a49baf0f07e45cf"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_CLOCK_SELECT_540GBPS" ref="9485063d8eff980d1a49baf0f07e45cf" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_CLOCK_SELECT_540GBPS 0x5 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
5.40 Gbps link.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="487854c0977ce9c4e9c4e58039986124"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_CONFIG" ref="487854c0977ce9c4e9c4e58039986124" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_CONFIG 0x0200 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Transceiver PHY reset and configuration.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="1ee16a2b678d6cc1546a8bf902bb7c89"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK" ref="1ee16a2b678d6cc1546a8bf902bb7c89" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_CONFIG_GT_ALL_RESET_MASK 0x0010003 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Rest GT and PHY.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="845b6767c137fa2f95b7015d806cff8c"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_CONFIG_GTTX_RESET_MASK" ref="845b6767c137fa2f95b7015d806cff8c" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_CONFIG_GTTX_RESET_MASK 0x0010002 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Hold GTTXRESET in reset.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="4d6874faa811cb8d358248cd4ae0f011"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK" ref="4d6874faa811cb8d358248cd4ae0f011" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK 0x0010000 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Release reset.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="66bf9327b2f5c4d4d6b26025e59b4d36"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_CONFIG_PHY_RESET_MASK" ref="66bf9327b2f5c4d4d6b26025e59b4d36" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_CONFIG_PHY_RESET_MASK 0x0010001 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Hold the PHY in reset.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="15fd7d4ca93314bb32381adc0a2b3885"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK" ref="15fd7d4ca93314bb32381adc0a2b3885" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK 0x001E000 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Set TX_PHY_LOOPBACK.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="7c229eef22f7effcbed81403a683e9b2"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK" ref="7c229eef22f7effcbed81403a683e9b2" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK 0x0010200 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
HOLD TX_PHY_PCS reset.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="e0a33037770384173f8c3bc28186c566"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK" ref="e0a33037770384173f8c3bc28186c566" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK 0x0010100 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Hold TX_PHY_PMA reset.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="ce37aefbbab4d22b4799d8dd39297a9e"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK" ref="ce37aefbbab4d22b4799d8dd39297a9e" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK 0x0010400 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Set TX_PHY_POLARITY.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="b887bdc93d976cd87cc6c0f057fb8558"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK" ref="b887bdc93d976cd87cc6c0f057fb8558" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK 0x0011000 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Set TX_PHY_PRBSFORCEERR.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="f3060020b46a5ad369644d526f170b84"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_POSTCURSOR_LANE_0" ref="f3060020b46a5ad369644d526f170b84" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_POSTCURSOR_LANE_0 0x024C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Controls the post-cursor level.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="0f36af19a92afc612f2d0f2452291d08"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_POSTCURSOR_LANE_1" ref="0f36af19a92afc612f2d0f2452291d08" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_POSTCURSOR_LANE_1 0x0250 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Controls the post-cursor level.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="62cc76b68fd47462665537c30eaf39fe"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_POSTCURSOR_LANE_2" ref="62cc76b68fd47462665537c30eaf39fe" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_POSTCURSOR_LANE_2 0x0254 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Controls the post-cursor level.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="70d04a6bce7d560384db2588c1dfb381"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_POSTCURSOR_LANE_3" ref="70d04a6bce7d560384db2588c1dfb381" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_POSTCURSOR_LANE_3 0x0258 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Controls the post-cursor level.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="19e1749f366474f7da5f87cb3ff9c9e3"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_PRECURSOR_LANE_0" ref="19e1749f366474f7da5f87cb3ff9c9e3" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_PRECURSOR_LANE_0 0x023C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Controls the pre-cursor level.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="30a02b0fd830a3197850481e5e86e675"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_PRECURSOR_LANE_1" ref="30a02b0fd830a3197850481e5e86e675" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_PRECURSOR_LANE_1 0x0240 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Controls the pre-cursor level.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="216134c361c24e629c019f185e721e66"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_PRECURSOR_LANE_2" ref="216134c361c24e629c019f185e721e66" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_PRECURSOR_LANE_2 0x0244 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Controls the pre-cursor level.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="a66bb78a8cf218c5ad880e42a0c6c10b"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_PRECURSOR_LANE_3" ref="a66bb78a8cf218c5ad880e42a0c6c10b" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_PRECURSOR_LANE_3 0x0248 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Controls the pre-cursor level.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="493791382f79a9be3f47d4e7b5340e80"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS" ref="493791382f79a9be3f47d4e7b5340e80" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS 0x0280 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Current PHY status.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="9efe7932d92c6d29ebad9f04638a93bd"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_ALL_LANES_READY_MASK" ref="9efe7932d92c6d29ebad9f04638a93bd" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_ALL_LANES_READY_MASK 0x0000003F </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
All lanes are ready.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="a25c98082d5eee6d6e311d68467b64a0"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK" ref="a25c98082d5eee6d6e311d68467b64a0" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_PLL_FABRIC_LOCK_MASK 0x00000020 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
FPGA fabric clock PLL locked.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="c3e7d53ee9205ba8a1c522398a47e160"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK" ref="c3e7d53ee9205ba8a1c522398a47e160" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK 0x00000010 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
PLL locked for lanes 0 and 1.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="2300cd50a0b23cb2f52ee91e1be2c9e8"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK" ref="2300cd50a0b23cb2f52ee91e1be2c9e8" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK 0x00000020 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
PLL locked for lanes 2 and 3.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="a4ce045c9d26a9b77376c6806d639830"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK" ref="a4ce045c9d26a9b77376c6806d639830" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK 0x00000003 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Reset done for lanes 0 and 1.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="17fcce23d900de4708b5bf9120b785a4"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK" ref="17fcce23d900de4708b5bf9120b785a4" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK 0x0000000C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Reset done for lanes 2 and 3.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="00d5b32392d1c89ed0c4daf09f9161ab"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK" ref="00d5b32392d1c89ed0c4daf09f9161ab" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK 0x00030000 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
TX buffer status lane 0.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="886dba9465eac92595f45a13bedc5b3d"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT" ref="886dba9465eac92595f45a13bedc5b3d" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT 16 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for TX buffer status lane 0.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="a3d8c074bbf11cf62abcf387fdc66b45"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK" ref="a3d8c074bbf11cf62abcf387fdc66b45" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK 0x00300000 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
TX buffer status lane 1.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="96b4be332f8a4c4b588f733f50977b1a"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT" ref="96b4be332f8a4c4b588f733f50977b1a" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT 20 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for TX buffer status lane 1.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="bf9d5735d3057d83ebc0fbb88a5fb0b8"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK" ref="bf9d5735d3057d83ebc0fbb88a5fb0b8" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK 0x03000000 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
TX buffer status lane 2.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="3c2331a45bc9e1826e3ba530fd0457a8"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT" ref="3c2331a45bc9e1826e3ba530fd0457a8" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT 24 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for TX buffer status lane 2.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="e2fc6f4cf25bd93b2dce7982c5fd74bc"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK" ref="e2fc6f4cf25bd93b2dce7982c5fd74bc" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK 0x30000000 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
TX buffer status lane 3.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="af9fe61b50e185574b688a501c44a3ab"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT" ref="af9fe61b50e185574b688a501c44a3ab" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT 28 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for TX buffer status lane 3.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="7a585a1375bd0679925e4de48c3bf1a0"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_TX_ERROR_LANE_0_MASK" ref="7a585a1375bd0679925e4de48c3bf1a0" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_MASK 0x000C0000 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
TX error on lane 0.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="e6bfe8d2903cd48c7af1d3e0c9ce4d40"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT" ref="e6bfe8d2903cd48c7af1d3e0c9ce4d40" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT 18 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for TX error on lane 0.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="ee437175211f97081b831d0ad3c89d44"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_TX_ERROR_LANE_1_MASK" ref="ee437175211f97081b831d0ad3c89d44" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_MASK 0x00C00000 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
TX error on lane 1.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="e14ada4aa4ae075a05e45fa19df859be"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT" ref="e14ada4aa4ae075a05e45fa19df859be" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT 22 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for TX error on lane 1.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="51fa6263682e7fc7480dd9906827ece6"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_TX_ERROR_LANE_2_MASK" ref="51fa6263682e7fc7480dd9906827ece6" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_MASK 0x0C000000 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
TX error on lane 2.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="767df1a30d971c2c0c2995678fc6082a"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT" ref="767df1a30d971c2c0c2995678fc6082a" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT 26 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for TX error on lane 2.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="5c43185dc4229494b406dc0bcaacbd93"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_TX_ERROR_LANE_3_MASK" ref="5c43185dc4229494b406dc0bcaacbd93" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_MASK 0xC0000000 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
TX error on lane 3.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="2cc33338ea15b08e0ce0525a07ebca04"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT" ref="2cc33338ea15b08e0ce0525a07ebca04" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT 30 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for TX error on lane 3.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="7b86ba2c2f902fde88dd84f52b09118c"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_TRANSMIT_PRBS7" ref="7b86ba2c2f902fde88dd84f52b09118c" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_TRANSMIT_PRBS7 0x0230 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Enable pseudo random bit sequence 7 pattern transmission for link quality assessment.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="4079f5af02adffbfb20e539e2d07e24e"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_VOLTAGE_DIFF_LANE_0" ref="4079f5af02adffbfb20e539e2d07e24e" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
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<td class="memname">#define XDPTX_PHY_VOLTAGE_DIFF_LANE_0 0x0220 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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|
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<p>
|
|
Controls the differential voltage swing.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="ba11c9397ca6e296d47c91d7771be137"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_VOLTAGE_DIFF_LANE_1" ref="ba11c9397ca6e296d47c91d7771be137" args="" -->
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<div class="memitem">
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<div class="memproto">
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|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_VOLTAGE_DIFF_LANE_1 0x0224 </td>
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|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Controls the differential voltage swing.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="9e8027b88c290569ab0e0f747b5ba36b"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_VOLTAGE_DIFF_LANE_2" ref="9e8027b88c290569ab0e0f747b5ba36b" args="" -->
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<div class="memitem">
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|
<div class="memproto">
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|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_VOLTAGE_DIFF_LANE_2 0x0228 </td>
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|
</tr>
|
|
</table>
|
|
</div>
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|
<div class="memdoc">
|
|
|
|
<p>
|
|
Controls the differential voltage swing.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="518c1a46ae6ade901965e78a54882fea"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_PHY_VOLTAGE_DIFF_LANE_3" ref="518c1a46ae6ade901965e78a54882fea" args="" -->
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<div class="memitem">
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<div class="memproto">
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|
<table class="memname">
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|
<tr>
|
|
<td class="memname">#define XDPTX_PHY_VOLTAGE_DIFF_LANE_3 0x022C </td>
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</tr>
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|
</table>
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|
</div>
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|
<div class="memdoc">
|
|
|
|
<p>
|
|
Controls the differential voltage swing.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="b9ae114efe97122a7a212baf3a27d5fe"></a><!-- doxytag: member="xdptx_hw.h::XDptx_ReadReg" ref="b9ae114efe97122a7a212baf3a27d5fe" args="(BaseAddress, RegOffset)" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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|
<tr>
|
|
<td class="memname">#define XDptx_ReadReg </td>
|
|
<td>(</td>
|
|
<td class="paramtype">BaseAddress, <tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">RegOffset </td>
|
|
<td class="paramname"> </td>
|
|
<td> ) </td>
|
|
<td width="100%"> XDptx_In32((BaseAddress) + (RegOffset))</td>
|
|
</tr>
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|
</table>
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|
</div>
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|
<div class="memdoc">
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|
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|
<p>
|
|
This is a low-level function that reads from the specified register.<p>
|
|
<dl compact><dt><b>Parameters:</b></dt><dd>
|
|
<table border="0" cellspacing="2" cellpadding="0">
|
|
<tr><td valign="top"></td><td valign="top"><em>BaseAddress</em> </td><td>is the base address of the device. </td></tr>
|
|
<tr><td valign="top"></td><td valign="top"><em>RegOffset</em> </td><td>is the register offset to be read from.</td></tr>
|
|
</table>
|
|
</dl>
|
|
<dl compact><dt><b>Returns:</b></dt><dd>The 32-bit value of the specified register.</dd></dl>
|
|
<dl compact><dt><b>Note:</b></dt><dd>C-style signature: u32 <a class="el" href="xdptx__hw_8h.html#b9ae114efe97122a7a212baf3a27d5fe">XDptx_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>
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|
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="96d63a4878d267090ed96df9276d25b1"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_REPLY_DATA_COUNT" ref="96d63a4878d267090ed96df9276d25b1" args="" -->
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<div class="memitem">
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<div class="memproto">
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|
<table class="memname">
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|
<tr>
|
|
<td class="memname">#define XDPTX_REPLY_DATA_COUNT 0x0148 </td>
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|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Total number of data bytes actually received during a transaction.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="862f248407790107b10e27b095ccde28"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_REPLY_STATUS" ref="862f248407790107b10e27b095ccde28" args="" -->
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<div class="memitem">
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<div class="memproto">
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|
<table class="memname">
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|
<tr>
|
|
<td class="memname">#define XDPTX_REPLY_STATUS 0x014C </td>
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|
</tr>
|
|
</table>
|
|
</div>
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|
<div class="memdoc">
|
|
|
|
<p>
|
|
Reply status of most recent AUX transaction.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="6a56b5d431c98ea5b2ba0370dcded113"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_REPLY_STATUS_REPLY_ERROR_MASK" ref="6a56b5d431c98ea5b2ba0370dcded113" args="" -->
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|
<div class="memitem">
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<div class="memproto">
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|
<table class="memname">
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|
<tr>
|
|
<td class="memname">#define XDPTX_REPLY_STATUS_REPLY_ERROR_MASK 0x00000008 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Detected an error in the AUX reply of the most recent transaction.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="1ca3f1ab7e3d36698fd1eb723e3974b6"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK" ref="1ca3f1ab7e3d36698fd1eb723e3974b6" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK 0x00000002 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
AUX reply is currently being received.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="763daa97667f07ffbd3c94eef9e0f5aa"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_REPLY_STATUS_REPLY_RECEIVED_MASK" ref="763daa97667f07ffbd3c94eef9e0f5aa" args="" -->
|
|
<div class="memitem">
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|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_REPLY_STATUS_REPLY_RECEIVED_MASK 0x00000001 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
AUX transaction is complete and a valid reply transaction received.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="ee67e335775bd954e6509576977e45be"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_MASK" ref="ee67e335775bd954e6509576977e45be" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_MASK 0x00000FF0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Internal AUX reply state machine status bits.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="be3af3d8dab5f5fe9127a6d0681fce30"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT" ref="be3af3d8dab5f5fe9127a6d0681fce30" args="" -->
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|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT 4 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Shift bits for the internal AUX reply state machine status.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="3a890eeacb3f8acfd9202413cb04ca8b"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK" ref="3a890eeacb3f8acfd9202413cb04ca8b" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK 0x00000004 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
AUX request is currently being transmitted.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="245e3300cb64b18ae8b5a2c05a2726a5"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_SCRAMBLING_DISABLE" ref="245e3300cb64b18ae8b5a2c05a2726a5" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_SCRAMBLING_DISABLE 0x0014 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Disable scrambler and transmit all symbols.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="d67b688fb3c16c3aa74b8c6f5a6b4967"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_SOFT_RESET" ref="d67b688fb3c16c3aa74b8c6f5a6b4967" args="" -->
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|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_SOFT_RESET 0x001C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Software reset.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="a42b3c0d8bb96f522f7d3c1e16c1ba5d"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_SOFT_RESET_AUX_MASK" ref="a42b3c0d8bb96f522f7d3c1e16c1ba5d" args="" -->
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|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_SOFT_RESET_AUX_MASK 0x00000080 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Reset AUX logic.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="037c22e295d3f8b26fcddff580293cc6"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK" ref="037c22e295d3f8b26fcddff580293cc6" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_SOFT_RESET_VIDEO_STREAM1_MASK 0x00000001 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Reset video logic.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="974d191e058d55981244a170102bfb2a"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK" ref="974d191e058d55981244a170102bfb2a" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_SOFT_RESET_VIDEO_STREAM2_MASK 0x00000002 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Reset video logic.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="98c15ede26e0e404a68298f665693276"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK" ref="98c15ede26e0e404a68298f665693276" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_SOFT_RESET_VIDEO_STREAM3_MASK 0x00000004 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Reset video logic.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="7a9059fd1dedbcdd95831b97c8b8e4df"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK" ref="7a9059fd1dedbcdd95831b97c8b8e4df" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_SOFT_RESET_VIDEO_STREAM4_MASK 0x00000008 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Reset video logic.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="b3f82673e49bafb86e6200e25737e799"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK" ref="b3f82673e49bafb86e6200e25737e799" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK 0x0000000F </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Reset video logic for all streams.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="192b3ac947426e2781f599d9aed2be57"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_STREAM0" ref="192b3ac947426e2781f599d9aed2be57" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_STREAM0 0x01D0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Average stream symbol timeslots per MTP config.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="3d5adff92f22f4916380275fcb78aca2"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_STREAM1" ref="3d5adff92f22f4916380275fcb78aca2" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_STREAM1 0x01D4 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Average stream symbol timeslots per MTP config.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="abbb86cc9a2f8bb9dae29262b6d60b2b"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_STREAM2" ref="abbb86cc9a2f8bb9dae29262b6d60b2b" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_STREAM2 0x01D8 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Average stream symbol timeslots per MTP config.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="c9c2cc3ea5a63b843a362b6df260b8e5"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_STREAM3" ref="c9c2cc3ea5a63b843a362b6df260b8e5" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_STREAM3 0x01DC </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Average stream symbol timeslots per MTP config.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="80266896bc3c68c7109deba44db4fcac"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TRAINING_PATTERN_SET" ref="80266896bc3c68c7109deba44db4fcac" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TRAINING_PATTERN_SET 0x000C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Set the link training pattern.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="47a32150d890b4990105454f66661a7d"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TRAINING_PATTERN_SET_OFF" ref="47a32150d890b4990105454f66661a7d" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TRAINING_PATTERN_SET_OFF 0x0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Training off.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="0028aec42575496731849818fd2dabfc"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TRAINING_PATTERN_SET_TP1" ref="0028aec42575496731849818fd2dabfc" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TRAINING_PATTERN_SET_TP1 0x1 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Training pattern 1 used for clock recovery.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="838017c480af7c66ba05ff52eb4943c3"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TRAINING_PATTERN_SET_TP2" ref="838017c480af7c66ba05ff52eb4943c3" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TRAINING_PATTERN_SET_TP2 0x2 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Training pattern 2 used for channel equalization.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="4e53269bd85479366d39f17fd1df053a"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TRAINING_PATTERN_SET_TP3" ref="4e53269bd85479366d39f17fd1df053a" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TRAINING_PATTERN_SET_TP3 0x3 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Training pattern 3 used for channel equalization for cores with DP v1.2.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="630b1bfbcebf8469d72b29b80e5cf9ef"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TU_SIZE" ref="630b1bfbcebf8469d72b29b80e5cf9ef" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TU_SIZE 0x01B0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Size of a transfer unit in the framing logic.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="92aa475f7ccf50bcb509c77100aab0bd"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TU_SIZE_STREAM2" ref="92aa475f7ccf50bcb509c77100aab0bd" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TU_SIZE_STREAM2 0x0530 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Size of a transfer unit in the framing logic.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="67b1aefaa452753a7056f5057ecf7181"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TU_SIZE_STREAM3" ref="67b1aefaa452753a7056f5057ecf7181" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TU_SIZE_STREAM3 0x0580 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Size of a transfer unit in the framing logic.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="8bf8b8cba8c2b4db28c2b19410c7932c"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TU_SIZE_STREAM4" ref="8bf8b8cba8c2b4db28c2b19410c7932c" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TU_SIZE_STREAM4 0x05D0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Size of a transfer unit in the framing logic.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="5a3a6ac16e1faba90f96d7d850424fe4"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TX_AUDIO_CHANNELS" ref="5a3a6ac16e1faba90f96d7d850424fe4" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TX_AUDIO_CHANNELS 0x0304 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Used to input active channel count.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="a28e1ea3ef3152ca819c7893fcd9fa4b"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TX_AUDIO_CONTROL" ref="a28e1ea3ef3152ca819c7893fcd9fa4b" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TX_AUDIO_CONTROL 0x0300 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Enables audio stream packets in main link and buffer control.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="212b5791abb835f33378baa4ec18b421"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TX_AUDIO_EXT_DATA" ref="212b5791abb835f33378baa4ec18b421" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TX_AUDIO_EXT_DATA 0x0330 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Word formatted as per extension packet.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="64589b203a159f299715dd3e4ae1df56"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TX_AUDIO_INFO_DATA" ref="64589b203a159f299715dd3e4ae1df56" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TX_AUDIO_INFO_DATA 0x0308 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Word formatted as per CEA 861-C info frame.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="7ccf54c25f75ee26602d38a279ecbf3a"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TX_AUDIO_MAUD" ref="7ccf54c25f75ee26602d38a279ecbf3a" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TX_AUDIO_MAUD 0x0328 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
M value of audio stream as computed by the transmitter when audio clock and link clock are synchronous.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="eb93a2349291f47bd5bbeb24607c64c3"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TX_AUDIO_NAUD" ref="eb93a2349291f47bd5bbeb24607c64c3" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TX_AUDIO_NAUD 0x032C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
N value of audio stream as computed by the transmitter when audio clock and link clock are synchronous.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="3d5b09f9d08691a1e9de0d7b5677a5fc"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TX_MST_CONFIG" ref="3d5b09f9d08691a1e9de0d7b5677a5fc" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TX_MST_CONFIG 0x00D0 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Enable MST.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="e3dfe9adbe046867b3dd662933c6cfe5"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TX_MST_CONFIG_MST_EN_MASK" ref="e3dfe9adbe046867b3dd662933c6cfe5" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TX_MST_CONFIG_MST_EN_MASK 0x00000001 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Enable MST.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="a6ee400aabb4c568145283eecd1b0a2c"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TX_MST_CONFIG_VCP_UPDATED_MASK" ref="a6ee400aabb4c568145283eecd1b0a2c" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TX_MST_CONFIG_VCP_UPDATED_MASK 0x00000002 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
The VC payload has been updated in the sink.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="096993419705dd1135ac7e4b21274e53"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TX_PHY_POWER_DOWN" ref="096993419705dd1135ac7e4b21274e53" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TX_PHY_POWER_DOWN 0x0238 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Controls PHY power down.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="22adbb477c55f0ca7fc3740f53d69fed"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_TX_USER_FIFO_OVERFLOW" ref="22adbb477c55f0ca7fc3740f53d69fed" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_TX_USER_FIFO_OVERFLOW 0x0110 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Indicates an overflow in user FIFO.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="59420080445456a7bae12e8cdebbec5d"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_USER_DATA_COUNT_PER_LANE" ref="59420080445456a7bae12e8cdebbec5d" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_USER_DATA_COUNT_PER_LANE 0x01BC </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Used to translate the number of pixels per line to the native internal 16-bit datapath.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="a5af5a5f055696b339ddeaf044fed403"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_USER_DATA_COUNT_PER_LANE_STREAM2" ref="a5af5a5f055696b339ddeaf044fed403" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM2 0x053C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Used to translate the number of pixels per line to the native internal 16-bit datapath.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="aa45192aef3af89d6594014b1b23638a"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_USER_DATA_COUNT_PER_LANE_STREAM3" ref="aa45192aef3af89d6594014b1b23638a" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM3 0x058C </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Used to translate the number of pixels per line to the native internal 16-bit datapath.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="f597927a708ab606d66eb00829ca4ad0"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_USER_DATA_COUNT_PER_LANE_STREAM4" ref="f597927a708ab606d66eb00829ca4ad0" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM4 0x05DC </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Used to translate the number of pixels per line to the native internal 16-bit datapath.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="2eccd9b84a12fae6acf5fa0fb7e8963d"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_USER_PIXEL_WIDTH" ref="2eccd9b84a12fae6acf5fa0fb7e8963d" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_USER_PIXEL_WIDTH 0x01B8 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Selects the width of the user data input port.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="457fc6f90e33915ca75ad82f94da5050"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_USER_PIXEL_WIDTH_STREAM2" ref="457fc6f90e33915ca75ad82f94da5050" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_USER_PIXEL_WIDTH_STREAM2 0x0538 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Selects the width of the user data input port.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="4fb4c3f07ac791b9f371cdb8b1c6f59b"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_USER_PIXEL_WIDTH_STREAM3" ref="4fb4c3f07ac791b9f371cdb8b1c6f59b" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_USER_PIXEL_WIDTH_STREAM3 0x0588 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Selects the width of the user data input port.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="964f50348a330c54e3f9385df764bb5d"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_USER_PIXEL_WIDTH_STREAM4" ref="964f50348a330c54e3f9385df764bb5d" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_USER_PIXEL_WIDTH_STREAM4 0x05D8 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Selects the width of the user data input port.
|
|
</div>
|
|
</div><p>
|
|
<a class="anchor" name="011ee90104e02971fe66441090536110"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_VC_PAYLOAD_BUFFER_ADDR" ref="011ee90104e02971fe66441090536110" args="" -->
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">#define XDPTX_VC_PAYLOAD_BUFFER_ADDR 0x0800 </td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<div class="memdoc">
|
|
|
|
<p>
|
|
Virtual channel payload table (0xFF bytes).
|
|
</div>
|
|
</div><p>
|
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<a class="anchor" name="e92176c8f7b15bf84f9aa8e25100e15c"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_VERSION" ref="e92176c8f7b15bf84f9aa8e25100e15c" args="" -->
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<div class="memitem">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_VERSION 0x00F8 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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Core version.
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</div>
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</div><p>
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<a class="anchor" name="4f961fb9b541d128e7d7ddd4cf937d8c"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_VERSION_CORE_PATCH_MASK" ref="4f961fb9b541d128e7d7ddd4cf937d8c" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_VERSION_CORE_PATCH_MASK 0x00000030 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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Core patch details.
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</div>
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</div><p>
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<a class="anchor" name="0043eefcacbbd52840d16b54ad877360"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_VERSION_CORE_PATCH_SHIFT" ref="0043eefcacbbd52840d16b54ad877360" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_VERSION_CORE_PATCH_SHIFT 8 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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Shift bits for core patch details.
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</div>
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</div><p>
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<a class="anchor" name="5e8a58c4333013d122753116e2b632ec"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_VERSION_CORE_VER_MJR_MASK" ref="5e8a58c4333013d122753116e2b632ec" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_VERSION_CORE_VER_MJR_MASK 0x0000F000 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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Core major version.
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</div>
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</div><p>
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<a class="anchor" name="a8692843543715a53090dc8015d1854b"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_VERSION_CORE_VER_MJR_SHIFT" ref="a8692843543715a53090dc8015d1854b" args="" -->
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_VERSION_CORE_VER_MJR_SHIFT 24 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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Shift bits for core major version.
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</div>
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</div><p>
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<a class="anchor" name="91636a250112453f44827b1c267035a4"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_VERSION_CORE_VER_MNR_MASK" ref="91636a250112453f44827b1c267035a4" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_VERSION_CORE_VER_MNR_MASK 0x00000F00 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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Core minor version.
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</div>
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</div><p>
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<a class="anchor" name="12530407a38f1797c571cec54956ca4d"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_VERSION_CORE_VER_MNR_SHIFT" ref="12530407a38f1797c571cec54956ca4d" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_VERSION_CORE_VER_MNR_SHIFT 16 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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Shift bits for core minor version.
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</div>
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</div><p>
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<a class="anchor" name="43b70a12b91cf4eb65095955225505b1"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_VERSION_CORE_VER_REV_MASK" ref="43b70a12b91cf4eb65095955225505b1" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_VERSION_CORE_VER_REV_MASK 0x000000C0 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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Core version revision.
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</div>
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</div><p>
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<a class="anchor" name="a57773a7ec75d2abe17e232a459bf73b"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_VERSION_CORE_VER_REV_SHIFT" ref="a57773a7ec75d2abe17e232a459bf73b" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_VERSION_CORE_VER_REV_SHIFT 12 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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Shift bits for core version revision.
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</div>
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</div><p>
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<a class="anchor" name="93b403c56404d4ed676f2deb14dcbfad"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_VERSION_INTER_REV_MASK" ref="93b403c56404d4ed676f2deb14dcbfad" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_VERSION_INTER_REV_MASK 0x0000000F </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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Internal revision.
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</div>
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</div><p>
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<a class="anchor" name="f359f44b5d2763ed0536e9a89d2771e0"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_VS_LEVEL_0" ref="f359f44b5d2763ed0536e9a89d2771e0" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_VS_LEVEL_0 0x2 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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Voltage swing level 0.
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</div>
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</div><p>
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<a class="anchor" name="bd02990d70c63a0b7598fcb6ce1b867e"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_VS_LEVEL_1" ref="bd02990d70c63a0b7598fcb6ce1b867e" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_VS_LEVEL_1 0x5 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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Voltage swing level 1.
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</div>
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</div><p>
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<a class="anchor" name="e0a4c903dcc0de3fd56378ea721534a2"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_VS_LEVEL_2" ref="e0a4c903dcc0de3fd56378ea721534a2" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_VS_LEVEL_2 0x8 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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Voltage swing level 2.
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</div>
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</div><p>
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<a class="anchor" name="5d28772a94530d91c12e8aa054380280"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_VS_LEVEL_3" ref="5d28772a94530d91c12e8aa054380280" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_VS_LEVEL_3 0xF </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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Voltage swing level 3.
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</div>
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</div><p>
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<a class="anchor" name="7852023a12302535fd5aef02adf966a2"></a><!-- doxytag: member="xdptx_hw.h::XDPTX_VS_LEVEL_OFFSET" ref="7852023a12302535fd5aef02adf966a2" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define XDPTX_VS_LEVEL_OFFSET 0x4 </td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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Voltage swing compensation offset used when there's no redriver in display path.
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</div>
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</div><p>
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<a class="anchor" name="740519ee4cc95e492351ad8cf9085632"></a><!-- doxytag: member="xdptx_hw.h::XDptx_WriteReg" ref="740519ee4cc95e492351ad8cf9085632" args="(BaseAddress, RegOffset, Data)" -->
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<td class="memname">#define XDptx_WriteReg </td>
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<td>(</td>
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<td class="paramtype">BaseAddress, <tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">RegOffset, <tr>
|
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<td class="paramkey"></td>
|
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<td></td>
|
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<td class="paramtype">Data </td>
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<td class="paramname"> </td>
|
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<td> ) </td>
|
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<td width="100%"> XDptx_Out32((BaseAddress) + (RegOffset), (Data))</td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>
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This is a low-level function that writes to the specified register.<p>
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<dl compact><dt><b>Parameters:</b></dt><dd>
|
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<table border="0" cellspacing="2" cellpadding="0">
|
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<tr><td valign="top"></td><td valign="top"><em>BaseAddress</em> </td><td>is the base address of the device. </td></tr>
|
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<tr><td valign="top"></td><td valign="top"><em>RegOffset</em> </td><td>is the register offset to write to. </td></tr>
|
|
<tr><td valign="top"></td><td valign="top"><em>Data</em> </td><td>is the 32-bit data to write to the specified register.</td></tr>
|
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</table>
|
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</dl>
|
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<dl compact><dt><b>Note:</b></dt><dd>C-style signature: void <a class="el" href="xdptx__hw_8h.html#740519ee4cc95e492351ad8cf9085632">XDptx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>
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</div>
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</div><p>
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Copyright @ 1995-2014 Xilinx, Inc. All rights reserved.
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