fe2c47e815
Added functionality that reorders the sink list such that topologies containing tiled display(s) will have the contained sinks reordered in a consistent manner. The need for such functionality exists because not all tiled displays will have the same internal topologies. It was observed that two 4k2k MST based monitors (tiled display, 2 sinks) from different manufacturers would have the left and right images swapped using identical stream-to-sink mappings. Thus, the need to obtain the tiled display topology information of all sinks and their relative tile location is required to send the correct stream to the desired sink. Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
894 lines
36 KiB
C
894 lines
36 KiB
C
/*******************************************************************************
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*
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* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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*******************************************************************************/
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/******************************************************************************/
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/**
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*
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* @file xdptx.h
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*
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* The Xilinx DisplayPort transmitter (DPTX) driver. This driver supports the
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* Xilinx DisplayPort soft IP core in source (TX) mode. This driver follows the
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* DisplayPort 1.2a specification.
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*
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* The Xilinx DisplayPort soft IP supports the following features:
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* - 1, 2, or 4 lanes.
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* - A link rate of 1.62, 2.70, or 5.40Gbps per lane.
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* - 1, 2, or 4 pixel-wide video interfaces.
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* - RGB and YCbCr color space.
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* - Up to 16 bits per component.
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* - Up to 4Kx2K monitor resolution.
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* - Auto lane rate and width negotiation.
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* - I2C over a 1Mb/s AUX channel.
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* - Secondary channel audio support (2 channels).
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* - 4 independent video multi-streams.
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*
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* The Xilinx DisplayPort soft IP does not support the following features:
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* - The automated test feature.
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* - Audio (3-8 channel).
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* - FAUX.
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* - Bridging function.
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* - MST audio.
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* - eDP optional features.
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* - iDP.
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* - GTC.
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*
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* <b>DisplayPort overview</b>
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*
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* A DisplayPort link consists of:
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* - A unidirectional main link which is used to transport isochronous data
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* streams such as video and audio. The main link may use 1, 2, or 4
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* lanes at a link rate of 1.62, 2.70, or 5.40Gbps per lane. The link
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* needs to be trained prior to sending streams.
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* - An auxiliary (AUX) channel is a 1MBps bidirectional channel used for
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* link training, link management, and device control.
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* - A hot-plug-detect (HPD) signal line is used to determine whether a
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* DisplayPort connection exists between the DisplayPort TX connector and
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* an RX device. It is serves as an interrupt request by the RX device.
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*
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* <b>Driver description</b>
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*
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* The device driver enables higher-level software (e.g., an application) to
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* configure and control a DisplayPort TX soft IP, communicate and control an
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* RX device/sink monitor over the AUX channel, and to initialize and transmit
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* data streams over the main link.
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*
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* This driver implements link layer functionality: a Link Policy Maker (LPM)
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* and a Stream Policy Maker (SPM) as per the DisplayPort 1.2a specification.
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* - The LPM manages the main link and is responsible for keeping the link
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* synchronized. It will establish a link with a downstream RX device by
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* undergoing a link training sequence which consists of:
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* - Clock recovery: The clock needs to be recovered and PLLs need to be
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* locked for all lanes.
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* - Channel equalization: All lanes need to achieve channel equalization
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* and and symbol lock, as well as for interlane alignment to take place.
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* - The SPM manages transportation of an isochronous stream. That is, it will
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* initialize and maintain a video stream, establish a virtual channel to a
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* sink monitor, and transmit the stream.
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*
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* Using AUX transactions to read/write from/to the sink's DisplayPort
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* Configuration Data (DPCD) address space, the LPM obtains the link
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* capabilities, obtains link configuration and link and sink status, and
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* configures and controls the link and sink. The main link is trained this way.
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*
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* I2C-over-AUX transactions are used to obtain the sink's Extended Display
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* Identification Data (EDID) which give information on the display capabilities
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* of the monitor. The SPM may use this information to determine what available
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* screen resolutions and video timing are possible.
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*
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* <b>Device configuration</b>
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*
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* The device can be configured in various ways during the FPGA implementation
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* process. Configuration parameters are stored in the xdptx_g.c file which is
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* generated when compiling the board support package (BSP). A table is defined
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* where each entry contains configuration information for the DisplayPort
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* instances present in the system. This information includes parameters that
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* are defined in the driver's data/dptx.tcl file such as the base address of
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* the memory-mapped device and the maximum number of lanes, maximum link rate,
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* and video interface that the DisplayPort instance supports, among others.
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*
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* <b>Interrupt processing</b>
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*
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* DisplayPort interrupts occur on the HPD signal line when the DisplayPort
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* cable is connected/disconnected or when the RX device sends a pulse. The user
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* hardware design must contain an interrupt controller which the DisplayPort
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* TX instance's interrupt signal is connected to. The user application must
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* enable interrupts in the system and set up the interrupt controller such that
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* the XDptx_HpdInterruptHandler handler will service DisplayPort interrupts.
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* When the XDptx_HpdInterruptHandler function is invoked, the handler will
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* identify what type of DisplayPort interrupt has occurred, and will call
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* either the HPD event handler function or the HPD pulse handler function,
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* depending on whether a an HPD event on an HPD pulse event occurred.
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*
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* The DisplayPort TX's XDPTX_INTERRUPT_STATUS register indicates the type of
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* interrupt that has occured, and the XDptx_HpdInterruptHandler will use this
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* information to decide which handler to call. An HPD event is identified if
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* bit XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is
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* identified from the XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit.
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*
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* The HPD event handler may be set up by using the XDptx_SetHpdEventHandler
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* function and, for the HPD pulse handler, the XDptx_SetHpdPulseHandler
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* function.
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*
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* <b>Multi-stream transport (MST) mode</b>
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*
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* The driver handles MST mode functionality, including sideband messaging,
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* topology discovery, virtual channel payload ID table management, and
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* directing streams to different sinks.
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*
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* MST testing has been done at 5.40Gbps per 4 lanes, with 4 sinks in a daisy-
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* chain configuration, with each stream having the same resolution. Testing has
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* been done at the following resolutions: 640x480, 720x480, 800x600, 848x480,
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* 1024x768, 1280x720, 1280x1024, 1080p, and UHD (UHD/2 on 2 streams). Each
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* resolutions was tested at 24 bits per pixel using 1, 2, 3, and 4 streams.
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* Color depths of 18, 30, 36, and 48 bits per pixel were also tested.
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*
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* <b>Audio</b>
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*
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* The driver does not handle audio. For an example as to how to configure and
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* transmit audio, dptx_v2_0/examples/xdptx_audio_example.c illustrates the
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* required sequence. The user will need to configure the audio source connected
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* to the Displayport TX instance and set up the audio info frame as per user
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* requirements.
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*
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* <b>Asserts</b>
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*
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* Asserts are used within all Xilinx drivers to enforce constraints on argument
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* values. Asserts can be turned off on a system-wide basis by defining, at
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* compile time, the NDEBUG identifier. By default, asserts are turned on and
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* it is recommended that application developers leave asserts on during
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* development.
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*
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* <b>Limitations and known issues</b>
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*
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* - For MST mode to correctly display, the current version of the driver
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* requires that each of the DisplayPort TX streams be allocated without
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* skipping streams (i.e. assign stream 1, stream 2, and stream 3 - problems
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* were experienced if skipping stream 2 and assigning stream 4 instead).
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* skipping monitors in a daisy chain is OK as long as they are assigned to
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* streams in order.
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* - In MST mode, the current version of the driver does not support removal of
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* an allocated stream from the virtual channel payload ID table without
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* clearing the entire table.
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* - Some sideband messages have not been implemented in the current version of
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* the driver for MST mode. Notably, reception of a CONNECTION_STATUS_NOTIFY
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* sideband message.
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* - The driver does not handle audio. See the audio example in the driver
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* examples directory for the required sequence for enabling audio.
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*
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* @note For a 5.4Gbps link rate, a high performance 7 series FPGA is
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* required with a speed grade of -2 or -3.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.0 als 05/17/14 Initial release.
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* als 08/03/14 Initial MST addition.
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* 2.0 als 09/21/14 Added XDptx_DiscoverTopology function and changed
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* XDptx_IsConnected from macro to function.
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* </pre>
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*
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*******************************************************************************/
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#ifndef XDPTX_H_
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/* Prevent circular inclusions by using protection macros. */
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#define XDPTX_H_
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/******************************* Include Files ********************************/
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#include "xdptx_hw.h"
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#include "xil_assert.h"
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#include "xil_types.h"
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/****************************** Type Definitions ******************************/
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/**
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* This typedef enumerates the list of available standard display monitor
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* timings as specified in the mode_table.c file. The naming format is:
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*
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* XDPTX_VM_<RESOLUTION>_<REFRESH RATE (HZ)>_<P|RB>
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*
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* Where RB stands for reduced blanking.
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*/
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typedef enum {
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XDPTX_VM_640x480_60_P,
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XDPTX_VM_800x600_60_P,
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XDPTX_VM_848x480_60_P,
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XDPTX_VM_1024x768_60_P,
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XDPTX_VM_1280x768_60_P_RB,
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XDPTX_VM_1280x768_60_P,
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XDPTX_VM_1280x800_60_P_RB,
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XDPTX_VM_1280x800_60_P,
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XDPTX_VM_1280x960_60_P,
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XDPTX_VM_1280x1024_60_P,
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XDPTX_VM_1360x768_60_P,
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XDPTX_VM_1400x1050_60_P_RB,
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XDPTX_VM_1400x1050_60_P,
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XDPTX_VM_1440x900_60_P_RB,
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XDPTX_VM_1440x900_60_P,
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XDPTX_VM_1600x1200_60_P,
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XDPTX_VM_1680x1050_60_P_RB,
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XDPTX_VM_1680x1050_60_P,
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XDPTX_VM_1792x1344_60_P,
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XDPTX_VM_1856x1392_60_P,
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XDPTX_VM_1920x1200_60_P_RB,
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XDPTX_VM_1920x1200_60_P,
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XDPTX_VM_1920x1440_60_P,
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XDPTX_VM_2560x1600_60_P_RB,
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XDPTX_VM_2560x1600_60_P,
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XDPTX_VM_800x600_56_P,
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XDPTX_VM_1600x1200_65_P,
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XDPTX_VM_1600x1200_70_P,
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XDPTX_VM_1024x768_70_P,
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XDPTX_VM_640x480_72_P,
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XDPTX_VM_800x600_72_P,
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XDPTX_VM_640x480_75_P,
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XDPTX_VM_800x600_75_P,
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XDPTX_VM_1024x768_75_P,
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XDPTX_VM_1152x864_75_P,
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XDPTX_VM_1280x768_75_P,
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XDPTX_VM_1280x800_75_P,
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XDPTX_VM_1280x1024_75_P,
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XDPTX_VM_1400x1050_75_P,
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XDPTX_VM_1440x900_75_P,
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XDPTX_VM_1600x1200_75_P,
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XDPTX_VM_1680x1050_75_P,
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XDPTX_VM_1792x1344_75_P,
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XDPTX_VM_1856x1392_75_P,
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XDPTX_VM_1920x1200_75_P,
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XDPTX_VM_1920x1440_75_P,
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XDPTX_VM_2560x1600_75_P,
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XDPTX_VM_640x350_85_P,
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XDPTX_VM_640x400_85_P,
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XDPTX_VM_720x400_85_P,
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XDPTX_VM_640x480_85_P,
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XDPTX_VM_800x600_85_P,
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XDPTX_VM_1024x768_85_P,
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XDPTX_VM_1280x768_85_P,
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XDPTX_VM_1280x800_85_P,
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XDPTX_VM_1280x960_85_P,
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XDPTX_VM_1280x1024_85_P,
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XDPTX_VM_1400x1050_85_P,
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XDPTX_VM_1440x900_85_P,
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XDPTX_VM_1600x1200_85_P,
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XDPTX_VM_1680x1050_85_P,
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XDPTX_VM_1920x1200_85_P,
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XDPTX_VM_2560x1600_85_P,
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XDPTX_VM_800x600_120_P_RB,
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XDPTX_VM_1024x768_120_P_RB,
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XDPTX_VM_1280x768_120_P_RB,
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XDPTX_VM_1280x800_120_P_RB,
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XDPTX_VM_1280x960_120_P_RB,
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XDPTX_VM_1280x1024_120_P_RB,
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XDPTX_VM_1360x768_120_P_RB,
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XDPTX_VM_1400x1050_120_P_RB,
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XDPTX_VM_1440x900_120_P_RB,
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XDPTX_VM_1600x1200_120_P_RB,
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XDPTX_VM_1680x1050_120_P_RB,
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XDPTX_VM_1792x1344_120_P_RB,
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XDPTX_VM_1856x1392_120_P_RB,
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XDPTX_VM_1920x1200_120_P_RB,
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XDPTX_VM_1920x1440_120_P_RB,
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XDPTX_VM_2560x1600_120_P_RB,
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XDPTX_VM_1366x768_60_P,
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XDPTX_VM_1920x1080_60_P,
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XDPTX_VM_UHD_30_P,
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XDPTX_VM_720_60_P,
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XDPTX_VM_480_60_P,
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XDPTX_VM_UHD2_60_P,
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XDPTX_VM_UHD_60,
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XDPTX_VM_USE_EDID_PREFERRED,
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XDPTX_VM_LAST = XDPTX_VM_USE_EDID_PREFERRED
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} XDptx_VideoMode;
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/**
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* This typedef contains configuration information for the DisplayPort TX core.
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*/
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typedef struct {
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u16 DeviceId; /**< Device instance ID. */
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u32 BaseAddr; /**< The base address of the core instance. */
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u32 SAxiClkHz; /**< The clock frequency of the core instance's
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S_AXI_ACLK port. */
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u8 MaxLaneCount; /**< The maximum lane count supported by this
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core instance. */
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u8 MaxLinkRate; /**< The maximum link rate supported by this
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core instance. */
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u8 MaxBitsPerColor; /**< The maximum bits/color supported by this
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core instance*/
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u8 QuadPixelEn; /**< Quad pixel support by this core
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instance. */
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u8 DualPixelEn; /**< Dual pixel support by this core
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instance. */
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u8 YCrCbEn; /**< YCrCb format support by this core
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instance. */
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u8 YOnlyEn; /**< YOnly format support by this core
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instance. */
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u8 PayloadDataWidth; /**< The payload data width used by this core
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instance. */
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u8 SecondaryChEn; /**< This core instance supports audio packets
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being sent by the secondary channel. */
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u8 NumAudioChs; /**< The number of audio channels supported by
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this core instance. */
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u8 MstSupport; /**< Multi-stream transport (MST) mode is
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enabled by this core instance. */
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u8 NumMstStreams; /**< The total number of MST streams supported
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by this core instance. */
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u8 DpProtocol; /**< The DisplayPort protocol version that this
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core instance is configured for.
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0 = v1.1a, 1 = v1.2. */
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} XDptx_Config;
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/**
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* This typedef contains configuration information about the RX device.
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*/
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typedef struct {
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u8 DpcdRxCapsField[XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE];
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/**< The raw capabilities field
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of the RX device's DisplayPort
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Configuration Data (DPCD). */
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u8 LaneStatusAdjReqs[6]; /**< This is a raw read of the
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RX device's status registers.
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The first 4 bytes correspond to
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the lane status associated with
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clock recovery, channel
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equalization, symbol lock, and
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interlane alignment. The
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remaining 2 bytes represent the
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pre-emphasis and voltage swing
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level adjustments requested by
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the RX device. */
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} XDptx_SinkConfig;
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/**
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* This typedef contains configuration information about the main link settings.
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*/
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typedef struct {
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u8 LaneCount; /**< The current lane count of the main
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link. */
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u8 LinkRate; /**< The current link rate of the main
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link. */
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u8 ScramblerEn; /**< Symbol scrambling is currently in
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use over the main link. */
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u8 EnhancedFramingMode; /**< Enhanced frame mode is currently in
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use over the main link. */
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u8 DownspreadControl; /**< Downspread control is currently in
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use over the main link. */
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u8 MaxLaneCount; /**< The maximum lane count of the main
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link. */
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u8 MaxLinkRate; /**< The maximum link rate of the main
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link. */
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u8 SupportEnhancedFramingMode; /**< Enhanced frame mode is supported by
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the RX device. */
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u8 SupportDownspreadControl; /**< Downspread control is supported by
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the RX device. */
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u8 VsLevel; /**< The current voltage swing level for
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each lane. */
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u8 PeLevel; /**< The current pre-emphasis/cursor
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level for each lane. */
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u8 Pattern; /**< The current pattern currently in
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use over the main link. */
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} XDptx_LinkConfig;
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/**
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* This typedef contains the display monitor timing attributes for a video mode.
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*/
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typedef struct {
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XDptx_VideoMode VideoMode; /**< Enumerated key. */
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u8 DmtId; /**< Standard Display Monitor Timing
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(DMT) ID number. */
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u16 HResolution; /**< Horizontal resolution (in
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pixels). */
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u16 VResolution; /**< Vertical resolution (in lines). */
|
|
u32 PixelClkKhz; /**< Pixel frequency (in KHz). This is
|
|
also the M value for the video
|
|
stream (MVid). */
|
|
u8 Interlaced; /**< Input stream interlaced scan
|
|
(0=non-interlaced/
|
|
1=interlaced). */
|
|
u8 HSyncPolarity; /**< Horizontal synchronization polarity
|
|
(0=positive/1=negative). */
|
|
u8 VSyncPolarity; /**< Vertical synchronization polarity
|
|
(0=positive/1=negative). */
|
|
u32 HFrontPorch; /**< Horizontal front porch (in
|
|
pixels). */
|
|
u32 HSyncPulseWidth; /**< Horizontal synchronization time
|
|
(pulse width in pixels). */
|
|
u32 HBackPorch; /**< Horizontal back porch (in
|
|
pixels). */
|
|
u32 VFrontPorch; /**< Vertical front porch (in lines). */
|
|
u32 VSyncPulseWidth; /**< Vertical synchronization time
|
|
(pulse width in lines). */
|
|
u32 VBackPorch; /**< Vertical back porch (in lines). */
|
|
} XDptx_DmtMode;
|
|
|
|
/**
|
|
* This typedef contains the main stream attributes which determine how the
|
|
* video will be displayed.
|
|
*/
|
|
typedef struct {
|
|
XDptx_DmtMode Dmt; /**< Holds the set of Display Mode
|
|
Timing (DMT) attributes that
|
|
correspond to the information
|
|
stored in the XDptx_DmtModes
|
|
table. */
|
|
u32 HClkTotal; /**< Horizontal total time (in
|
|
pixels). */
|
|
u32 VClkTotal; /**< Vertical total time (in pixels). */
|
|
u32 HStart; /**< Horizontal blank start (in
|
|
pixels). */
|
|
u32 VStart; /**< Vertical blank start (in lines). */
|
|
u32 Misc0; /**< Miscellaneous stream attributes 0
|
|
as specified by the DisplayPort
|
|
1.2 specification. */
|
|
u32 Misc1; /**< Miscellaneous stream attributes 1
|
|
as specified by the DisplayPort
|
|
1.2 specification. */
|
|
u32 NVid; /**< N value for the video stream. */
|
|
u32 UserPixelWidth; /**< The width of the user data input
|
|
port. */
|
|
u32 DataPerLane; /**< Used to translate the number of
|
|
pixels per line to the native
|
|
internal 16-bit datapath. */
|
|
u32 AvgBytesPerTU; /**< Average number of bytes per
|
|
transfer unit, scaled up by a
|
|
factor of 1000. */
|
|
u32 TransferUnitSize; /**< Size of the transfer unit in the
|
|
framing logic. In MST mode, this
|
|
is also the number of time slots
|
|
that are alloted in the payload
|
|
ID table. */
|
|
u32 InitWait; /**< Number of initial wait cycles at
|
|
the start of a new line by
|
|
the framing logic. */
|
|
u32 BitsPerColor; /**< Number of bits per color
|
|
component. */
|
|
u8 ComponentFormat; /**< The component format currently in
|
|
use by the video stream. */
|
|
u8 DynamicRange; /**< The dynamic range currently in use
|
|
by the video stream. */
|
|
u8 YCbCrColorimetry; /**< The YCbCr colorimetry currently in
|
|
use by the video stream. */
|
|
u8 SynchronousClockMode; /**< Synchronous clock mode is currently
|
|
in use by the video stream. */
|
|
u8 OverrideUserPixelWidth; /**< If set to 1, the value stored for
|
|
UserPixelWidth will be used as
|
|
the pixel width. */
|
|
} XDptx_MainStreamAttributes;
|
|
|
|
/**
|
|
* This typedef describes a stream when the driver is running in multi-stream
|
|
* transport (MST) mode.
|
|
*/
|
|
typedef struct {
|
|
u8 LinkCountTotal; /** The total number of DisplayPort
|
|
links from the DisplayPort TX to
|
|
the sink device that this MST
|
|
stream is targeting.*/
|
|
u8 RelativeAddress[15]; /** The relative address from the
|
|
DisplayPort TX to the sink
|
|
device that this MST stream is
|
|
targeting.*/
|
|
u16 MstPbn; /**< Payload bandwidth number used to
|
|
allocate bandwidth for the MST
|
|
stream. */
|
|
u8 MstStreamEnable; /**< In MST mode, enables the
|
|
corresponding stream for this
|
|
MSA configuration. */
|
|
} XDptx_MstStream;
|
|
|
|
/**
|
|
* This typedef describes some board characteristics information that affects
|
|
* link training.
|
|
*/
|
|
typedef struct {
|
|
u8 HasRedriverInPath; /**< Redriver in path requires different voltage
|
|
swing and pre-emphasis. */
|
|
u8 TxVsLevels[4]; /**< The voltage swing levels to be used by the
|
|
DisplayPort TX. */
|
|
u8 TxPeLevels[4]; /**< The pre-emphasis/cursor level to be used by
|
|
the DisplayPort TX. */
|
|
u8 TxVsOffset; /**< Voltage swing compensation offset used when
|
|
pre-emphasis is used. */
|
|
} XDptx_BoardChar;
|
|
|
|
/**
|
|
* This typedef describes a downstream DisplayPort device when the driver is
|
|
* running in multi-stream transport (MST) mode.
|
|
*/
|
|
typedef struct {
|
|
u32 Guid[4]; /**< The global unique identifier (GUID)
|
|
of the device. */
|
|
u8 RelativeAddress[15]; /**< The relative address from the
|
|
DisplayPort TX to this
|
|
device. */
|
|
u8 DeviceType; /**< The type of DisplayPort device.
|
|
Either a branch or sink. */
|
|
u8 LinkCountTotal; /**< The total number of DisplayPort
|
|
links connecting this device to
|
|
the DisplayPort TX. */
|
|
u8 DpcdRev; /**< The revision of the device's
|
|
DisplayPort Configuration Data
|
|
(DPCD). For this device to
|
|
support MST features, this value
|
|
must represent a protocl version
|
|
greater or equal to 1.2. */
|
|
u8 MsgCapStatus; /**< This device is capable of sending
|
|
and receiving sideband
|
|
messages. */
|
|
} XDptx_TopologyNode;
|
|
|
|
/**
|
|
* This typedef describes a the entire topology of connected downstream
|
|
* DisplayPort devices (from the DisplayPort TX) when the driver is operating
|
|
* in multi-stream transport (MST) mode.
|
|
*/
|
|
typedef struct {
|
|
u8 NodeTotal; /**< The total number of nodes that were
|
|
found in the MST topology. */
|
|
XDptx_TopologyNode NodeTable[63]; /**< A table listing all the nodes in
|
|
the MST topology. */
|
|
u8 SinkTotal; /**< The total number of sinks in the
|
|
MST topology. */
|
|
XDptx_TopologyNode *SinkList[63]; /**< A pointer list of sinks in the
|
|
MST topology. The entries will
|
|
point to the sinks in the
|
|
NodeTable. */
|
|
} XDptx_Topology;
|
|
|
|
/**
|
|
* This typedef describes a port that is connected to a DisplayPort branch
|
|
* device. This structure is used when the driver is operating in multi-stream
|
|
* transport (MST) mode.
|
|
*/
|
|
typedef struct {
|
|
u8 InputPort; /**< Specifies that this port is an
|
|
input port. */
|
|
u8 PeerDeviceType; /**< Specifies the device type connected
|
|
to this port. */
|
|
u8 PortNum; /**< The port number of this port. */
|
|
u8 MsgCapStatus; /**< This port or the device at this
|
|
port can send and receive MST
|
|
messages. */
|
|
u8 DpDevPlugStatus; /**< There is a device connected to this
|
|
port. */
|
|
|
|
u8 LegacyDevPlugStatus; /**< This port is connected to a legacy
|
|
device. */
|
|
u8 DpcdRev; /**< The DisplayPort Configuration Data
|
|
(DPCD) revision of the device
|
|
connected to this port. */
|
|
u32 Guid[4]; /**< The global unique identifier (GUID)
|
|
of the device connected to this
|
|
port. */
|
|
u8 NumSdpStreams; /**< The total number of Secondary-Data
|
|
Packet (SDP) streams that this
|
|
port can handle. */
|
|
u8 NumSdpStreamSinks; /**< The number of SDP streams
|
|
associated with this port. */
|
|
} XDptx_SbMsgLinkAddressReplyPortDetail;
|
|
|
|
/**
|
|
* This typedef describes a DisplayPort branch device. This structure is used
|
|
* when the driver is operating in multi-stream transport (MST) mode.
|
|
*/
|
|
typedef struct {
|
|
u8 ReplyType; /**< The reply type of the sideband
|
|
message. A value of 1 indicates
|
|
that the request wasn't
|
|
successful and the return data
|
|
will give the reason for a
|
|
negative-acknowledge (NACK). */
|
|
u8 RequestId; /**< The request identifier of the
|
|
reply. This should correspond to
|
|
the request identifier for the
|
|
LINK_ADDRESS sideband message
|
|
request. */
|
|
u32 Guid[4]; /**< The global unique identifier (GUID)
|
|
of the branch device. */
|
|
u8 NumPorts; /**< The number of ports associated with
|
|
this branch device. */
|
|
XDptx_SbMsgLinkAddressReplyPortDetail PortDetails[16]; /**< An array
|
|
describing all ports attached to
|
|
this branch device. */
|
|
} XDptx_SbMsgLinkAddressReplyDeviceInfo;
|
|
|
|
/******************************************************************************/
|
|
/**
|
|
* Callback type which represents a custom timer wait handler. This is only
|
|
* used for Microblaze since it doesn't have a native sleep function. To avoid
|
|
* dependency on a hardware timer, the default wait functionality is implemented
|
|
* using loop iterations; this isn't too accurate. If a custom timer handler is
|
|
* used, the user may implement their own wait implementation using a hardware
|
|
* timer (see example/) for better accuracy.
|
|
*
|
|
* @param InstancePtr is a pointer to the XDptx instance.
|
|
* @param MicroSeconds is the number of microseconds to be passed to the
|
|
* timer function.
|
|
*
|
|
* @note None.
|
|
*
|
|
*******************************************************************************/
|
|
typedef void (*XDptx_TimerHandler)(void *InstancePtr, u32 MicroSeconds);
|
|
|
|
/******************************************************************************/
|
|
/**
|
|
* Callback type which represents the handler for a Hot-Plug-Detect (HPD) event
|
|
* interrupt.
|
|
*
|
|
* @param InstancePtr is a pointer to the XDptx instance.
|
|
*
|
|
* @note None.
|
|
*
|
|
*******************************************************************************/
|
|
typedef void (*XDptx_HpdEventHandler)(void *InstancePtr);
|
|
|
|
/******************************************************************************/
|
|
/**
|
|
* Callback type which represents the handler for a Hot-Plug-Detect (HPD) pulse
|
|
* interrupt.
|
|
*
|
|
* @param InstancePtr is a pointer to the XDptx instance.
|
|
*
|
|
* @note None.
|
|
*
|
|
*******************************************************************************/
|
|
typedef void (*XDptx_HpdPulseHandler)(void *InstancePtr);
|
|
|
|
/**
|
|
* The XDptx driver instance data. The user is required to allocate a variable
|
|
* of this type for every XDptx device in the system. A pointer to a variable of
|
|
* this type is then passed to the driver API functions.
|
|
*/
|
|
typedef struct {
|
|
u32 MstEnable; /**< Multi-stream transport
|
|
(MST) mode. Enables
|
|
functionality, allowing
|
|
multiple streams to be
|
|
sent over the main
|
|
link. */
|
|
u32 IsReady; /**< Device is initialized and
|
|
ready. */
|
|
u8 TrainAdaptive; /**< Downshift lane count and
|
|
link rate if necessary
|
|
during training. */
|
|
XDptx_Config Config; /**< Configuration structure for
|
|
the DisplayPort TX
|
|
core. */
|
|
XDptx_SinkConfig RxConfig; /**< Configuration structure for
|
|
the RX device. */
|
|
XDptx_LinkConfig LinkConfig; /**< Configuration structure for
|
|
the main link. */
|
|
XDptx_BoardChar BoardChar; /**< Some board characteristics
|
|
information that affects
|
|
link training. */
|
|
XDptx_MainStreamAttributes MsaConfig[4]; /**< Configuration structure
|
|
for the main stream
|
|
attributes (MSA). Each
|
|
stream has its own set
|
|
of attributes. When MST
|
|
mode is disabled, only
|
|
MsaConfig[0] is used. */
|
|
XDptx_MstStream MstStreamConfig[4]; /**< Configuration structure
|
|
for a multi-stream
|
|
transport (MST)
|
|
stream. */
|
|
XDptx_Topology Topology; /**< The topology of connected
|
|
downstream DisplayPort
|
|
devices when the driver
|
|
is running in MST
|
|
mode. */
|
|
u32 AuxDelayUs; /**< Amount of latency in micro-
|
|
seconds to use between
|
|
AUX transactions. */
|
|
u32 SbMsgDelayUs; /**< Amount of latency in micro-
|
|
seconds to use between
|
|
sideband messages for
|
|
multi-stream transport
|
|
(MST) mode. */
|
|
XDptx_TimerHandler UserTimerWaitUs; /**< Custom user function for
|
|
delay/sleep. */
|
|
void *UserTimerPtr; /**< Pointer to a timer instance
|
|
used by the custom user
|
|
delay/sleep function. */
|
|
XDptx_HpdEventHandler HpdEventHandler; /**< Callback function for Hot-
|
|
Plug-Detect (HPD) event
|
|
interrupts. */
|
|
void *HpdEventCallbackRef; /**< A pointer to the user data
|
|
passed to the HPD event
|
|
callback function. */
|
|
XDptx_HpdPulseHandler HpdPulseHandler; /**< Callback function for Hot-
|
|
Plug-Detect (HPD) pulse
|
|
interrupts. */
|
|
void *HpdPulseCallbackRef; /**< A pointer to the user data
|
|
passed to the HPD pulse
|
|
callback function. */
|
|
} XDptx;
|
|
|
|
/*************************** Variable Declarations ****************************/
|
|
|
|
extern XDptx_DmtMode XDptx_DmtModes[];
|
|
|
|
/**************************** Function Prototypes *****************************/
|
|
|
|
/* xdptx.c: Setup and initialization functions. */
|
|
u32 XDptx_InitializeTx(XDptx *InstancePtr);
|
|
void XDptx_CfgInitialize(XDptx *InstancePtr, XDptx_Config *ConfigPtr,
|
|
u32 EffectiveAddr);
|
|
u32 XDptx_GetRxCapabilities(XDptx *InstancePtr);
|
|
|
|
/* xdptx.c: Link policy maker functions. */
|
|
u32 XDptx_CfgMainLinkMax(XDptx *InstancePtr);
|
|
u32 XDptx_EstablishLink(XDptx *InstancePtr);
|
|
u32 XDptx_CheckLinkStatus(XDptx *InstancePtr, u8 LaneCount);
|
|
void XDptx_EnableTrainAdaptive(XDptx *InstancePtr, u8 Enable);
|
|
void XDptx_SetHasRedriverInPath(XDptx *InstancePtr, u8 Set);
|
|
void XDptx_CfgTxVsOffset(XDptx *InstancePtr, u8 Offset);
|
|
void XDptx_CfgTxVsLevel(XDptx *InstancePtr, u8 Level, u8 TxLevel);
|
|
void XDptx_CfgTxPeLevel(XDptx *InstancePtr, u8 Level, u8 TxLevel);
|
|
|
|
/* xdptx.c: AUX transaction functions. */
|
|
u32 XDptx_AuxRead(XDptx *InstancePtr, u32 Address, u32 BytesToRead,
|
|
void *ReadData);
|
|
u32 XDptx_AuxWrite(XDptx *InstancePtr, u32 Address, u32 BytesToWrite,
|
|
void *WriteData);
|
|
u32 XDptx_IicRead(XDptx *InstancePtr, u8 IicAddress, u16 Offset,
|
|
u16 BytesToRead, void *ReadData);
|
|
u32 XDptx_IicWrite(XDptx *InstancePtr, u8 IicAddress, u8 BytesToWrite,
|
|
void *WriteData);
|
|
|
|
/* xdptx.c: Functions for controlling the link configuration. */
|
|
u32 XDptx_SetDownspread(XDptx *InstancePtr, u8 Enable);
|
|
u32 XDptx_SetEnhancedFrameMode(XDptx *InstancePtr, u8 Enable);
|
|
u32 XDptx_SetLaneCount(XDptx *InstancePtr, u8 LaneCount);
|
|
u32 XDptx_SetLinkRate(XDptx *InstancePtr, u8 LinkRate);
|
|
u32 XDptx_SetScrambler(XDptx *InstancePtr, u8 Enable);
|
|
|
|
/* xdptx.c: General usage functions. */
|
|
u32 XDptx_IsConnected(XDptx *InstancePtr);
|
|
void XDptx_EnableMainLink(XDptx *InstancePtr);
|
|
void XDptx_DisableMainLink(XDptx *InstancePtr);
|
|
void XDptx_ResetPhy(XDptx *InstancePtr, u32 Reset);
|
|
void XDptx_WaitUs(XDptx *InstancePtr, u32 MicroSeconds);
|
|
void XDptx_SetUserTimerHandler(XDptx *InstancePtr,
|
|
XDptx_TimerHandler CallbackFunc, void *CallbackRef);
|
|
|
|
/* xdptx_spm.c: Stream policy maker functions. */
|
|
void XDptx_CfgMsaRecalculate(XDptx *InstancePtr, u8 Stream);
|
|
void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr, u8 Stream,
|
|
XDptx_VideoMode VideoMode);
|
|
void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr, u8 Stream,
|
|
u8 *Edid);
|
|
void XDptx_CfgMsaUseCustom(XDptx *InstancePtr, u8 Stream,
|
|
XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate);
|
|
void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 Stream, u8 BitsPerColor);
|
|
void XDptx_CfgMsaEnSynchClkMode(XDptx *InstancePtr, u8 Stream, u8 Enable);
|
|
void XDptx_SetVideoMode(XDptx *InstancePtr, u8 Stream);
|
|
void XDptx_ClearMsaValues(XDptx *InstancePtr, u8 Stream);
|
|
void XDptx_SetMsaValues(XDptx *InstancePtr, u8 Stream);
|
|
|
|
/* xdptx_intr.c: Interrupt handling functions. */
|
|
void XDptx_SetHpdEventHandler(XDptx *InstancePtr,
|
|
XDptx_HpdEventHandler CallbackFunc, void *CallbackRef);
|
|
void XDptx_SetHpdPulseHandler(XDptx *InstancePtr,
|
|
XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef);
|
|
void XDptx_HpdInterruptHandler(XDptx *InstancePtr);
|
|
|
|
/* xdptx_selftest.c: Self test function. */
|
|
u32 XDptx_SelfTest(XDptx *InstancePtr);
|
|
|
|
/* xdptx_sinit.c: Configuration extraction function.*/
|
|
XDptx_Config *XDptx_LookupConfig(u16 DeviceId);
|
|
|
|
/* xdptx_mst.c: Multi-stream transport (MST) functions for enabling or disabling
|
|
* MST mode. */
|
|
void XDptx_MstCfgModeEnable(XDptx *InstancePtr);
|
|
void XDptx_MstCfgModeDisable(XDptx *InstancePtr);
|
|
u32 XDptx_MstCapable(XDptx *InstancePtr);
|
|
u32 XDptx_MstEnable(XDptx *InstancePtr);
|
|
u32 XDptx_MstDisable(XDptx *InstancePtr);
|
|
|
|
/* xdptx_mst.c: Multi-stream transport (MST) functions for enabling or disabling
|
|
* MST streams and selecting their associated target sinks. */
|
|
void XDptx_MstCfgStreamEnable(XDptx *InstancePtr, u8 Stream);
|
|
void XDptx_MstCfgStreamDisable(XDptx *InstancePtr, u8 Stream);
|
|
u8 XDptx_MstStreamIsEnabled(XDptx *InstancePtr, u8 Stream);
|
|
void XDptx_SetStreamSelectFromSinkList(XDptx *InstancePtr, u8 Stream, u8
|
|
SinkNum);
|
|
void XDptx_SetStreamSinkRad(XDptx *InstancePtr, u8 Stream, u8 LinkCountTotal,
|
|
u8 *RelativeAddress);
|
|
|
|
/* xdptx_mst.c: Multi-stream transport (MST) functions related to MST topology
|
|
* discovery and management. */
|
|
u32 XDptx_DiscoverTopology(XDptx *InstancePtr);
|
|
u32 XDptx_FindAccessibleDpDevices(XDptx *InstancePtr, u8 LinkCountTotal,
|
|
u8 *RelativeAddress);
|
|
void XDptx_TopologySwapSinks(XDptx *InstancePtr, u8 Index0, u8 Index1);
|
|
u32 XDptx_TopologySortSinksByTiling(XDptx *InstancePtr);
|
|
|
|
/* xdptx_mst.c: Multi-stream transport (MST) functions for communicating
|
|
* with downstream DisplayPort devices. */
|
|
u32 XDptx_RemoteDpcdRead(XDptx *InstancePtr, u8 LinkCountTotal,
|
|
u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData);
|
|
u32 XDptx_RemoteDpcdWrite(XDptx *InstancePtr, u8 LinkCountTotal,
|
|
u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData);
|
|
u32 XDptx_RemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal,
|
|
u8 *RelativeAddress, u8 IicAddress, u16 Offset, u16 BytesToRead,
|
|
u8 *ReadData);
|
|
u32 XDptx_RemoteIicWrite(XDptx *InstancePtr, u8 LinkCountTotal,
|
|
u8 *RelativeAddress, u8 IicAddress, u8 BytesToWrite, u8 *WriteData);
|
|
|
|
/* xdptx_mst.c: Multi-stream transport (MST) functions related to MST stream
|
|
* allocation. */
|
|
u32 XDptx_AllocatePayloadStreams(XDptx *InstancePtr);
|
|
u32 XDptx_AllocatePayloadVcIdTable(XDptx *InstancePtr, u8 VcId, u8 Ts);
|
|
u32 XDptx_ClearPayloadVcIdTable(XDptx *InstancePtr);
|
|
|
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/* xdptx_mst.c: Multi-stream transport (MST) functions for issuing sideband
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* messages. */
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u32 XDptx_SendSbMsgRemoteDpcdWrite(XDptx *InstancePtr, u8 LinkCountTotal,
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u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData);
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u32 XDptx_SendSbMsgRemoteDpcdRead(XDptx *InstancePtr, u8 LinkCountTotal,
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u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData);
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u32 XDptx_SendSbMsgRemoteIicWrite(XDptx *InstancePtr, u8 LinkCountTotal,
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u8 *RelativeAddress, u8 IicDeviceId, u8 BytesToWrite, u8 *WriteData);
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u32 XDptx_SendSbMsgRemoteIicRead(XDptx *InstancePtr, u8 LinkCountTotal,
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u8 *RelativeAddress, u8 IicDeviceId, u8 Offset, u8 BytesToRead,
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u8 *ReadData);
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u32 XDptx_SendSbMsgLinkAddress(XDptx *InstancePtr, u8 LinkCountTotal,
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u8 *RelativeAddress, XDptx_SbMsgLinkAddressReplyDeviceInfo *DeviceInfo);
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u32 XDptx_SendSbMsgEnumPathResources(XDptx *InstancePtr, u8 LinkCountTotal,
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u8 *RelativeAddress, u16 *AvailPbn, u16 *FullPbn);
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u32 XDptx_SendSbMsgAllocatePayload(XDptx *InstancePtr, u8 LinkCountTotal,
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u8 *RelativeAddress, u8 VcId, u16 Pbn);
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u32 XDptx_SendSbMsgClearPayloadIdTable(XDptx *InstancePtr);
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/* xdptx_mst.c: Multi-stream transport (MST) utility functions. */
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void XDptx_WriteGuid(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress,
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u32 Guid[4]);
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void XDptx_GetGuid(XDptx *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress,
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u32 *Guid);
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/* xdptx_edid.c: EDID utility functions. */
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u32 XDptx_GetEdid(XDptx *InstancePtr, u8 *Edid);
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u32 XDptx_GetRemoteEdid(XDptx *InstancePtr, u8 LinkCountTotal,
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u8 *RelativeAddress, u8 *Edid);
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u32 XDptx_GetEdidBlock(XDptx *InstancePtr, u8 *Data, u8 BlockNum);
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u32 XDptx_GetRemoteEdidBlock(XDptx *InstancePtr, u8 *Data, u8 BlockNum,
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u8 LinkCountTotal, u8 *RelativeAddress);
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u32 XDptx_GetRemoteEdidDispIdExt(XDptx *InstancePtr, u8 *Data,
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u8 LinkCountTotal, u8 *RelativeAddress);
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u32 XDptx_GetDispIdDataBlock(u8 *DisplayIdRaw, u8 SectionTag,
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u8 **DataBlockPtr);
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u32 XDptx_GetRemoteTiledDisplayDb(XDptx *InstancePtr, u8 *EdidExt,
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u8 LinkCountTotal, u8 *RelativeAddress, u8 **DataBlockPtr);
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#endif /* XDPTX_H_ */
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