fixed copy&paste bug and moved cpu initialization in cpu_init()
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9b47b3ef45
commit
403c529e8b
2 changed files with 16 additions and 35 deletions
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@ -387,12 +387,14 @@ void smp_start(uint32_t id)
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kprintf("Application processor %d is entering its idle task\n", apic_cpu_id());
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kprintf("Application processor %d is entering its idle task\n", apic_cpu_id());
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// initialize default cpu features
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#ifdef CONFIG_X86_32
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// initialization for x86_64 is done in smp_entry()
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cpu_init();
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cpu_init();
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#endif
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// use the same gdt like the boot processors
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// use the same gdt like the boot processors
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gdt_flush();
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gdt_flush();
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// install IDT
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// install IDT
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idt_install();
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idt_install();
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@ -99,18 +99,8 @@ ALIGN 8
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%if MAX_CORES > 1
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%if MAX_CORES > 1
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global smp_entry
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global smp_entry
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smp_entry:
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smp_entry:
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; enable caching, disable paging and fpu emulation
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; initialize cpu features
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and eax, 0x1ffffffb
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call cpu_init
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; ...and turn on FPU exceptions
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or eax, 0x22
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mov cr0, eax
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; clears the current pgd entry
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xor eax, eax
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mov cr3, eax
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; at this stage, we disable the SSE support
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mov eax, cr4
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and eax, 0xfffbf9ff
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mov cr4, eax
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; initialize page table
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; initialize page table
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mov edi, boot_pml4
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mov edi, boot_pml4
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@ -169,10 +159,7 @@ L3:
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pop ebp
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pop ebp
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ret
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ret
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ALIGN 4
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cpu_init:
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stublet:
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mov esp, startup_stack-4
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push ebx ; save pointer to the multiboot structure
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mov eax, cr0
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mov eax, cr0
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; enable caching, disable paging and fpu emulation
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; enable caching, disable paging and fpu emulation
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and eax, 0x1ffffffb
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and eax, 0x1ffffffb
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@ -186,6 +173,15 @@ stublet:
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mov eax, cr4
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mov eax, cr4
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and eax, 0xfffbf9ff
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and eax, 0xfffbf9ff
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mov cr4, eax
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mov cr4, eax
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ret
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ALIGN 4
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stublet:
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mov esp, startup_stack
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; save pointer to the multiboot structure
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push ebx
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; initialize cpu features
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call cpu_init
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; do we have the instruction cpuid?
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; do we have the instruction cpuid?
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pushfd
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pushfd
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pop eax
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pop eax
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@ -389,23 +385,6 @@ smp_start64:
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jmp $
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jmp $
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%endif
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%endif
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global cpu_init
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cpu_init:
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; mov eax, cr0
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; enable caching, disable paging and fpu emulation
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; and eax, 0x1ffffffb
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; ...and turn on FPU exceptions
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; or eax, 0x22
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; mov cr0, eax
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; clears the current pgd entry
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; xor eax, eax
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; mov cr3, eax
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; at this stage, we disable the SSE support
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; mov eax, cr4
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; and eax, 0xfffbf9ff
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; mov cr4, eax
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; ret
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; This will set up our new segment registers and is declared in
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; This will set up our new segment registers and is declared in
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; C as 'extern void gdt_flush();'
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; C as 'extern void gdt_flush();'
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global gdt_flush
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global gdt_flush
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