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testing global interrupt controller

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Generic account for RWTHAachen Students 2011-08-10 00:21:21 -07:00
parent d7175a72a9
commit 4b03e27a37
2 changed files with 44 additions and 34 deletions
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29
arch/x86/kernel/irq.c
View file

@ -33,8 +33,17 @@
#include <asm/idt.h>
#include <asm/isrs.h>
#include <asm/apic.h>
#include <asm/RCCE.h>
#define FPGA_BASE 0xf9000000
#define IRQ_STATUS 0xD000
#define IRQ_MASK 0xD200
#define IRQ_RESET 0xD400
#define IRQ_REQUEST 0xD600
#define IRQ_CONFIG 0xD800
static int my_ue;
/*
* These are our own ISRs that point to our special IRQ handler
* instead of the regular 'fault_handler' function
@ -211,6 +220,8 @@ int irq_init(void)
isrs_install();
irq_install();
my_ue = RCCE_ue();
return 0;
}
@ -234,21 +245,21 @@ void irq_handler(struct state *s)
{
/* This is a blank function pointer */
void (*handler) (struct state * s);
if( s->int_no != 123 ) kprintf( "irq_num = %d\n", s->int_no );
// at first, we check our work queues
if( s->int_no == 124 ) {
kprintf( "hello from rem_interrupt\n" );
check_workqueues();
/* determine interrupt source */
volatile int* irq_status = (volatile int*)(FPGA_BASE + IRQ_STATUS + my_ue*8);
kprintf( "irq_status_1: %x\n", *irq_status );
irq_status += 4;
kprintf( "irq_status_2: %x\n", *irq_status );
}
int status_reg1 = FPGA_BASE + 0xD008;
int comp = (1<<5);
int core_num = -1;
if( *((volatile int*)status_reg1) & comp ) {
kprintf( "Interrupt from core 1\n" );
}
/*
* Find out if we have a custom handler to run for this
* IRQ and then finally, run it

49
arch/x86/scc/icc.c
View file

@ -172,27 +172,26 @@ int icc_init(void)
// unmask interrupts
int irq_mask = FPGA_BASE + IRQ_MASK + my_ue*8;
*(int*)irq_mask &= 0;
volatile int* irq_mask = (volatile int*)(FPGA_BASE + IRQ_MASK + my_ue*8);
*irq_mask &= 0;
irq_mask += 4;
*(int*)irq_mask &= 0;
*irq_mask &= 0;
// reset interrupt reg
int irq_reset = FPGA_BASE + IRQ_RESET + my_ue*8;
*(int*)irq_reset &= 0;
volatile int* irq_reset = (volatile int*)(FPGA_BASE + IRQ_RESET + my_ue*8);
*irq_reset = 0xffff;
irq_reset += 4;
*(int*)irq_reset &= 0;
*irq_reset = 0xffff;
kprintf( "irq_request = %x\n", *(int*)(FPGA_BASE + IRQ_REQUEST + my_ue*8));
//int irq_request = FPGA_BASE + IRQ_REQUEST + my_ue*8;
//*(int*) irq_request = 1;
kprintf( "irq_request = %x\n", *(int*)(FPGA_BASE + IRQ_REQUEST + my_ue*8));
// set remote interrupts to LINT 0
volatile int* irq_config = (volatile int*)(FPGA_BASE + IRQ_CONFIG + my_ue*4);
*irq_config = 0;
kprintf( "irq_mask = %x\n", *(int*)(FPGA_BASE + IRQ_MASK + my_ue*8) );
kprintf( "LUT = %x\n", *(int*)(FPGA_BASE + IRQ_CONFIG + my_ue*4) );
kprintf( "reset_reg = %x\n", *(int*)(FPGA_BASE + IRQ_RESET + my_ue*8) );
kprintf( "status_reg = %x\n", *(int*)(FPGA_BASE + IRQ_STATUS + my_ue*8) );
volatile int* irq_status = (volatile int*)(FPGA_BASE + IRQ_STATUS + my_ue*8);
kprintf( "irq_mask = %x\n", *irq_mask );
kprintf( "irq_config = %x\n", *irq_config );
kprintf( "status_reg = %x\n", *irq_status );
kputs("Now, the SCC is initialized!\n");
return 0;
@ -232,21 +231,20 @@ int icc_halt(void)
int icc_send_spec_irq(int core_num) {
unsigned int addr = FPGA_BASE+IRQ_REQUEST+8*my_ue;
volatile int* addr = (volatile int*)(FPGA_BASE+IRQ_REQUEST+8*core_num);
unsigned int bit_pos;
// determine bit position and set according bit
if( my_ue < 32 ) {
unsigned int tmp;
kprintf( "*addr = %x\n", addr ) ;
tmp = ReadConfigReg(addr);
tmp |= 2;
kprintf( "tmp = %x\n", tmp );
SetConfigReg(addr, tmp);
kprintf( "request_reg_addr = %x\n", addr );
kprintf( "request_reg = %x\n", *(unsigned int*)addr );
bit_pos = 1 << my_ue;
}
else {
bit_pos = 1 << (my_ue - 32);
}
bit_pos = 0x8001;
kprintf( "bit_pos = 0x%x\n", bit_pos );
*addr = bit_pos;
return 0;
}
@ -257,6 +255,7 @@ int icc_irq_ping()
if( my_ue != 0 ) return -1;
icc_send_spec_irq(1);
kprintf( "my_ue = %d\n", my_ue );
kprintf( "sending irq to 1!\n");
return 0;
}