fix bugs in initialization of RCCE
at first, we have to enable paging and to disable caching for the configuration registers
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parent
31d14370c4
commit
9918db81ec
4 changed files with 34 additions and 88 deletions
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@ -32,22 +32,6 @@ extern "C" {
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#endif
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#ifdef CONFIG_ROCKCREEK
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/*#define SCC_PMEM_REGIONS 2
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typedef struct {
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uint32_t low;
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uint32_t high;
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} mem_region_t;
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typedef struct {
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uint32_t pid;
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uint32_t tile_frequency; // in MHz
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uint32_t router_frequency; // in MHz
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mem_region_t private_mem[SCC_PMEM_REGIONS];
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} scc_info_t;
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extern scc_info_t scc_info;*/
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int scc_init(void);
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#endif
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@ -158,9 +142,6 @@ uint32_t read_eip(void);
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inline static int system_init(void)
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{
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#ifdef CONFIG_ROCKCREEK
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scc_init();
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#endif
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gdt_install();
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apic_init();
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#ifdef CONFIG_PCI
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@ -30,6 +30,10 @@
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#include <metalsvm/errno.h>
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#include <asm/irq.h>
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#include <asm/multiboot.h>
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#ifdef CONFIG_ROCKCREEK
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#include <asm/RCCE_lib.h>
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#include <asm/SCC_API.h>
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#endif
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/*
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* Virtual Memory Layout of the standard configuration
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@ -675,6 +679,16 @@ int arch_paging_init(void)
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}
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#endif
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#ifdef CONFIG_ROCKCREEK
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// map SCC's configuration registers
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viraddr = map_region(CRB_X0_Y0, CRB_X0_Y0, (CRB_OWN-CRB_X0_Y0+16*1024*1024)/PAGE_SIZE, MAP_KERNEL_SPACE|MAP_NO_CACHE);
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kprintf("Map configuration registers at 0x%x\n", viraddr);
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// map SCC's configuration registers
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viraddr = map_region(MPB_X0_Y0, MPB_X0_Y0, (MPB_OWN-MPB_X0_Y0+16*1024*1024)/PAGE_SIZE, MAP_KERNEL_SPACE);
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kprintf("Map message passing buffers at 0x%x\n", viraddr);
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#endif
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/* enable paging */
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write_cr3((uint32_t) &boot_pgd);
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i = read_cr0();
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@ -51,7 +51,7 @@
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// GLOBAL VARIABLES USED BY THE LIBRARY
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//......................................................................................
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int RCCE_NP; // number of participating cores
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int RC_REFCLOCKMHZ=533; // baseline CPU frequency (MHz)
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int RC_REFCLOCKMHZ; // baseline CPU frequency (MHz)
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int RC_MY_COREID; // physical ID of calling core
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int RC_COREID[RCCE_MAXNP]; // array of physical core IDs for all participating
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// cores, sorted by rank
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@ -232,7 +232,7 @@ int RCCE_init(
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unsigned int RCCE_SHM_BUFFER_offset ,result, rd_slot_nbr, wr_slot_nbr;
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#endif
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void *nothing = NULL;
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#ifdef SCC
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// Copperridge specific initialization...
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InitAPI(0); //fflush(0)
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@ -27,22 +27,23 @@
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#ifdef CONFIG_ROCKCREEK
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#define CCR_INTR_ACTIVE 0x02
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//scc_info_t scc_info;
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static char* rcce_argv[] = {"MetalSVM", "1", "533", "0"};
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/*
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* Workaround to create a suitable argv array
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*/
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static char* argv_strings[] = {"MetalSVM", "1", "533", "0"};
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static char* argv[4] = {[0 ... 3] = NULL};
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static char** rcce_argv = argv;
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static int rcce_argc = 4;
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/*
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* This is a modified MPB program, which is part of the RCCE distribution (src/mpb.c).
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* This is the modified MPB program, which is part of the RCCE distribution (src/mpb.c).
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*
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* This function clears the local MPB and resets the test&set register.
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*/
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static int scc_reset(void)
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static int scc_clear(void)
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{
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int tmp, x, y, z, offset;
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// Initialize API
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InitAPI(0);
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// Find out who I am...
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tmp=ReadConfigReg(CRB_OWN+MYTILEID);
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x=(tmp>>3) & 0x0f; // bits 06:03
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@ -69,14 +70,12 @@ static int scc_reset(void)
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int scc_init(void)
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{
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// uint32_t x, y, z;
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// uint32_t tmp;
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int num_ranks;
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int my_rank;
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return 0;
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int i, my_rank;
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kprintf("Initialize Rock Creek!\n");
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for(i=0; i<rcce_argc; i++)
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argv[i] = argv_strings[i];
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if (RCCE_init(&rcce_argc, &rcce_argv) != RCCE_SUCCESS)
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return -ENODEV;
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@ -84,59 +83,11 @@ int scc_init(void)
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num_ranks = RCCE_num_ues();
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kprintf("Got rank %d of %d ranks\n", my_rank, num_ranks);
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i = ReadConfigReg(CRB_OWN+GLCFG0);
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kprintf("glcfg0 0x%x\n", i);
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/* synchronize before starting MetalSVM: */
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RCCE_barrier(&RCCE_COMM_WORLD);
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/*tmp = *((uint32_t*) (CRB_OWN+MYTILEID));
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x=(tmp>>3) & 0x0f; // bits 06:03
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y=(tmp>>7) & 0x0f; // bits 10:07
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z=(tmp ) & 0x07; // bits 02:00
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scc_info.pid = PID(x, y, z);
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kprintf("SCC Processor Id: %u (%u,%u,%u)\n", scc_info.pid, x, y, z);
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*/
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/* default values for 16 GB system */
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/*scc_info.private_mem[0].low = 0x00;
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scc_info.private_mem[0].high = 0x13FFFFFF;
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scc_info.private_mem[1].low = 0xFF000000;
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scc_info.private_mem[1].high = 0xFFFFFFFF;
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*/
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// tmp = *((uint32_t*) (CRB_OWN+GCBCFG));
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// tmp = (tmp & 0x3FFFFFF) >> 7;
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//kprintf("Own GCBCFG is 0x%x\n", tmp);
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/* if (tmp == 0x70E1) {
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scc_info.tile_frequency = 800;
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scc_info.router_frequency = 1600;
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} else {
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scc_info.tile_frequency = 533;
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scc_info.router_frequency = 800;
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}
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*/
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/* kprintf("The default tile frequency is %u MHz\nThe default router frequency is %u MHz\n",
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scc_info.tile_frequency, scc_info.router_frequency);
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if (z == 0)
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tmp = *((uint32_t*) (CRB_OWN+GLCFG0));
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else if (z == 1)
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tmp = *((uint32_t*) (CRB_OWN+GLCFG1));
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else
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tmp = 0;
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*/
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/* set INTR to enable maskable interrupts */
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/* tmp = tmp | CCR_INTR_ACTIVE;
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if (z == 0)
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*((uint32_t*) (CRB_OWN+GLCFG0)) = tmp;
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else if (z == 1)
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*((uint32_t*) (CRB_OWN+GLCFG1)) = tmp;
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*/
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/* reload core configuration */
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/* tmp = 0;
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if (z == 0)
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tmp = *((uint32_t*) (CRB_OWN+GLCFG0));
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else if (z == 1)
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tmp = *((uint32_t*) (CRB_OWN+GLCFG1));
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kprintf("Core Configuration %u: 0x%x\n", z, tmp);
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*/
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//RCCE_barrier(&RCCE_COMM_WORLD);
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kputs("Now, the SCC is initialized!\n");
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