Merge branch 'master' into readwrite
Conflicts: arch/x86/include/asm/page.h arch/x86/include/asm/processor.h arch/x86/kernel/idt.c
This commit is contained in:
commit
be0a6fa72f
8 changed files with 37 additions and 14 deletions
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@ -60,6 +60,8 @@
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#define PG_DIRTY (1 << _PAGE_BIT_DIRTY)
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/// Big page: 4MB (or 2MB)
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#define PG_PSE (1 << _PAGE_BIT_PSE)
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#define PG_MPE PG_PSE
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/// Global TLB entry (Pentium Pro and later)
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#define PG_GLOBAL (1 << _PAGE_BIT_GLOBAL)
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/// This virtual address range is reserved as marked
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@ -168,9 +168,20 @@ static inline void write_cr3(uint32_t val) {
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asm volatile("mov %0, %%cr3" : : "r"(val));
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}
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static inline uint32_t read_cr4(void) {
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uint32_t val;
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asm volatile("mov %%cr4, %0" : "=r"(val));
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return val;
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}
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static inline void write_cr4(uint32_t val) {
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asm volatile("mov %0, %%cr4" : : "r"(val));
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}
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/** @brief Flush a specific page entry in TLB
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* @param addr The (virtual) address of the page to flush
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*/
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static inline void tlb_flush_one_page(uint32_t addr)
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{
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asm volatile("invlpg (%0)" : : "r"(addr) : "memory");
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@ -103,14 +103,7 @@ gdt_flush:
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flush2:
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ret
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; Loads the IDT defined in '_idtp' into the processor.
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; This is declared in C as 'extern void idt_load();'
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global idt_load
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extern idtp
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idt_load:
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lidt [idtp]
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ret
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; determines the current instruction pointer (after the jmp)
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global read_eip
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read_eip:
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pop eax ; Get the return address
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@ -72,13 +72,13 @@ typedef struct {
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* "Unhandled Interrupt" exception
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*/
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static idt_entry_t idt[256] = {[0 ... 255] = {0, 0, 0, 0, 0}};
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idt_ptr_t idtp;
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/** @brief Loads the IDT
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*
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* The true definition lives in 'start.asm'
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*/
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extern void idt_load(void);
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//extern void idt_load(void);
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static idt_ptr_t idtp;
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/*
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* Use this function to set an entry in the IDT. Alot simpler
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@ -113,5 +113,5 @@ void idt_install(void)
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IDT_FLAG_PRESENT|IDT_FLAG_RING3|IDT_FLAG_32BIT|IDT_FLAG_TRAPGATE);
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/* Points the processor's internal register to the new IDT */
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idt_load();
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asm volatile("lidt %0" : : "m" (idtp));
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}
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@ -348,6 +348,10 @@ size_t map_region(size_t viraddr, size_t phyaddr, uint32_t npages, uint32_t flag
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if (flags & MAP_NO_CACHE)
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pgt->entries[index] |= PG_PCD;
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#ifdef CONFIG_ROCKCREEK
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if (flags & MAP_MPE)
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pgt->entries[index] |= PG_MPE;
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#endif
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if (flags & MAP_USER_SPACE)
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atomic_int32_inc(&task->user_usage);
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@ -695,8 +699,8 @@ int arch_paging_init(void)
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viraddr = map_region(CRB_X0_Y0, CRB_X0_Y0, (CRB_OWN-CRB_X0_Y0+16*1024*1024)/PAGE_SIZE, MAP_KERNEL_SPACE|MAP_NO_CACHE);
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kprintf("Map configuration registers at 0x%x\n", viraddr);
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// map SCC's configuration registers
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viraddr = map_region(MPB_X0_Y0, MPB_X0_Y0, (MPB_OWN-MPB_X0_Y0+16*1024*1024)/PAGE_SIZE, MAP_KERNEL_SPACE);
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// map SCC's message passing buffers
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viraddr = map_region(MPB_X0_Y0, MPB_X0_Y0, (MPB_OWN-MPB_X0_Y0+16*1024*1024)/PAGE_SIZE, MAP_KERNEL_SPACE|MAP_MPE);
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kprintf("Map message passing buffers at 0x%x\n", viraddr);
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#endif
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@ -27,6 +27,9 @@
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#ifdef CONFIG_ROCKCREEK
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/* PSE bit for Pentium+ equals MPE (message buffer enable) flag in RCK! So, use it to create _PAGE_MPB symbol... */
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#define _CR4_MPE 0x00000800
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/*
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* Workaround to create a suitable argv array
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*/
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@ -83,6 +86,11 @@ int scc_init(void)
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num_ranks = RCCE_num_ues();
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kprintf("Got rank %d of %d ranks\n", my_rank, num_ranks);
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/* Enable Messagepassing in CR4 */
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uint32_t cr4 = read_cr4();
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cr4 = cr4 | _CR4_MPE;
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write_cr4(cr4);
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i = ReadConfigReg(CRB_OWN+GLCFG0);
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kprintf("glcfg0 0x%x\n", i);
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@ -45,7 +45,9 @@ extern "C" {
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#define MAP_HEAP (1 << 5)
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#define MAP_CODE (1 << 6)
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#define MAP_READONLY (1 << 7)
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#ifdef CONFIG_ROCKCREEK
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#define MAP_MPE (1 << 8)
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#endif
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void NORETURN abort(void);
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/** @brief Kernel's memory allocator function.
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@ -89,6 +89,9 @@ int main(void)
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#endif
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multitasking_init();
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mmu_init();
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#ifdef CONFIG_ROCKCREEK
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scc_init();
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#endif
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initrd_init();
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irq_enable();
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