252 lines
8.4 KiB
C
252 lines
8.4 KiB
C
/*
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* Copyright 2013 Steffen Vogel, Chair for Operating Systems,
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* RWTH Aachen University
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* This file is part of MetalSVM.
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*/
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/**
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* @author Steffen Vogel
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* @file arch/x86/include/pmc.h
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* @brief Simple interface to IA32 Performance Monitor Counters
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*
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* This implementation is in parts specific for Intel Core 2 Duo Processors!
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*/
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#ifndef _ARCH_PMC_H_
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#define _ARCH_PMC_H_
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#include <stddef.h>
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// PMC MSR addresses
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#define MSR_PERF_GLOBAL_STATUS 0x38E // global counter control facilities
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#define MSR_PERF_GLOBAL_CTRL 0x38F
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#define MSR_PERF_GLOBAL_OVF_CTRL 0x390
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#define IA32_PERF_CAPABILITIES 0x345
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#define IA32_PERFEVTSEL(i) (0x186 + i) // general purpose PMC configuration register
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#define IA32_PMC(i) (0x0C1 + i) // general purpose PMC counter register
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#define IA32_A_PMC(i) (0x4C1 + i) // general purpose alias PMC counter register for full width writes
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#define MSR_PERF_FIXED_CTR(i) (0x309 + i) // fixed function PMC counter register
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#define MSR_PERF_FIXED_CTR_CTRL 0x38D // fixed functiion PMC configuration register
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#define PMC_FIXED_OS (1 << 0)
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#define PMC_FIXED_USR (1 << 1)
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#define PMV_FIXED_PMI (1 << 3)
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/* For Intel Core 2 Duo the MSR_PERF_FIXED_CTRs are mapped as followed:
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* MSR_PERF_FIXED_CTR(0) => INST_RETIRED.ANY
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* MSR_PERF_FIXED_CTR(1) => CPU_CLK_UNHALTED.CORE
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* MSR_PERF_FIXED_CTR(2) => CPU_CLK_UNHALTED.REF */
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// architectural flags for IA32_PERFEVTSEL
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#define PMC_EVTSEL_CMASK 24 // counter mask [31:24]
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#define PMC_EVTSEL_UMASK 8 // unit mask [15:8]
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#define PMC_EVTSEL_INC (1 << 23) // invert counter mask
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#define PMC_EVTSEL_EN (1 << 22) // enable counters
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#define PMC_EVTSEL_ANY (1 << 21) // any thread (from version 3 on)
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#define PMC_EVTSEL_INT (1 << 20) // APIC interrupt enable
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#define PMC_EVTSEL_PC (1 << 19) // pin control
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#define PMC_EVTSEL_E (1 << 18) // edge detect
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#define PMC_EVTSEL_OS (1 << 17) // operating system mode
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#define PMC_EVTSEL_USR (1 << 16) // user mode
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// Core 2 Duo non-architecural flags for IA32_PERFEVTSEL (bus snooping)
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#define PMC_EVTSEL_HITM (1 << 11) // HITM response
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#define PMC_EVTSEL_HIT (1 << 9) // HIT response
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#define PMV_EVTSEL_CLEAN (1 << 8) // CLEAN response
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// architecutral PMC events CPUID.0AH.EBX[6:0]
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#define PMC_EVT_UNHALTED_CORE_CLKS 0x003C // UnHalted Core Cycles
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#define PMC_EVT_UNHALTED_REF_CLKS 0x013C // UnHalted Reference Cycles
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#define PMC_EVT_INST_RET 0x00C0 // Instruction Retired
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#define PMC_EVT_LLC_REF 0x4F2E // LLC Reference
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#define PMC_EVT_LLC_MISS 0x412E // LLC Misses
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#define PMC_EVT_BRANCH_RET 0x00C4 // Branch Instruction Retired
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#define PMC_EVT_BRANCH_MISS_RET 0x00C5 // Branch Miss Retired
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// Core 2 Duo non-architecural PMC events
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#define PMC_EVT_DTLB_MISS_ANY 0x0108 // Memory accesses that missed the TLB
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#define PMC_EVT_DTLB_MISS_LD 0x0208 // DTLB misses due to load operations
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#define PMC_EVT_DTLB_MISS_L0_LD 0x0408 // Level 0: DTLB misses due to load operations
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#define PMC_EVT_DTLB_MISS_ST 0x0808 // DTLB misses due to store operations
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#define PMC_EVT_ITLB_FLUSH 0x4082 // ITLB flushes
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#define PMC_EVT_ITLB_MISS 0x1282 // ITLB misses (either large or small page)
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#define PMC_EVT_ITLB_MISS_RET 0x00C9 // Retired instructions that missed the ITLB
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#define PMC_EVT_ITLB_MISS_SMALL 0x0282 // ITLB small page misses
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#define PMC_EVT_ITLB_MISS_LARGE 0x1082 // ITLB large page misses
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#define PMC_EVT_PAGE_WALK_COUNT 0x010C // Number of page-walks executed
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#define PMC_EVT_PAGE_WALK_CLKS 0x020C // Duration of page-walks in core cycles
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#define PMC_EVT_MEM_LOAD_RETIRED_L1D_MISS 0x01CB // Retired loads that miss the L1 data cache (precise event)
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#define PMC_EVT_MEM_LOAD_RETIRED_L1D_LINE_MISS 0x02CB // L1 data cache line missed by retired loads (precise event)
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#define PMC_EVT_MEM_LOAD_RETIRED_L2_MISS 0x04CB // Retired loads that miss the L2 cache (precise event)
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#define PMC_EVT_MEM_LOAD_RETIRED_L2_LINE_MISS 0x08CB // L2 cache line missed by retired loads (precise event)
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#define PMC_EVT_MEM_LOAD_RETIRED_DTLB_MISS 0x10CB // Retired loads that miss the DTLB (precise event)
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struct pmc {
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uint8_t id;
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void (*start)();
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void (*stop)();
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void (*reset)();
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void (*write)(uint64_t val);
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uint64_t (*read)();
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};
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struct pmc_caps {
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/// Architecural PM version (CPUID.0AH:EAX[7:0])
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uint8_t version;
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/// Number of available General Purpose PMCs (CPUID.0AH:EAX[15:8])
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uint8_t gp_count;
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/// Number of available Fixed Function PMCs (CPUID.0AH.EDX[4:0])
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uint8_t ff_count;
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/// Counter bit width of General Purpose PMCs (CPUID.0AH:EAX[23:16])
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uint8_t gp_width;
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/// Counter bit width of Fixed Function PMCs (CPUID.0AH.EDX[12:5])
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uint8_t ff_width;
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/// Bit mask of supported architecural PMC events (CPUID.0AH.EBX[6:0])
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uint32_t arch_events;
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/// IA32_PERF_CAPABILITIES MSR
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uint64_t msr;
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};
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/** @brief Queries the CPU about available Performance Monitoring capabilities
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*
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* @return A pointer to the capabilities struct
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**/
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struct pmc_caps* pmc_init();
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/** @brief Setups and stops the general purpose PMCs
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*
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* @param i The counter number to configure (positive for gp PMCs, negative for ff PMCs)
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* @param event A combined event number including the unit mask (PMC_EVT_*)
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* @param flags Flags for the IA32_PERFEVTSEL registers (PMC_EVTSEL_*)
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* @param umask A seperate Unitmask ORed with event
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* @param cmask A optional counter mask value
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* @return
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* - 0 on success
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* - else failure (invalid counter or flags)
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*/
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int pmc_gp_config(uint8_t i, uint16_t event, uint32_t flags, uint8_t umask, uint8_t cmask);
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/** @brief Setups and stops the fixed function PMCs
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*
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* @param i The counter number to configure (positive for gp PMCs, negative for ff PMCs)
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* @param flags Flags for the MSR_PERF_FIXED_CTR_CTRL register
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* @return
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* - 0 on success
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* - else failure (invalid counter or flags)
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*/
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int pmc_ff_config(uint8_t i, uint8_t flags);
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/** @brief Start a single general purpose PMC
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*
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* @param i The counter number
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* @return
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* - 0 on success
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* - -EINVAL on invalid counter number
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*/
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inline int pmc_gp_start(uint8_t i);
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/** @brief Stop a single general purpose PMC
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*
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* @param i The counter number
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* @return
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* - 0 on success
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* - -EINVAL on invalid counter number
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*/
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inline int pmc_gp_stop(uint8_t i);
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/** @brief Start a single fixed function PMC
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*
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* @param i The counter number
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* @return
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* - 0 on success
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* - -EINVAL on invalid counter number
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*/
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inline int pmc_ff_start(uint8_t i);
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/** @brief Stop a single fixed function PMC
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*
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* @param i The counter number
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* @return
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* - 0 on success
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* - -EINVAL on invalid counter number
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*/
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inline int pmc_ff_stop(uint8_t i);
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/** @brief Start all PMCs at the same time
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*
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* @return
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* - 0 on success
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* - -EINVAL on invalid counter number
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*/
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inline int pmc_start_all();
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/** @brief Stop all PMCs at the same time
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*
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* @return
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* - 0 on success
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* - -EINVAL on invalid counter number
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*/
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inline int pmc_stop_all();
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/** @brief Reset all PMCs to zero
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*
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* @return
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* - 0 on success
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* - -EINVAL on invalid counter number
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*/
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inline int pmc_reset_all();
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/** @brief Read a single general purpose PMC
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*
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* @param i The counter number
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* @return The counter value (see struct pmc_caps.gp_width)
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*/
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inline uint64_t pmc_gp_read(uint8_t i);
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/** @brief Read a single fixed function PMC
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*
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* @param i The counter number
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* @return The counter value (see struct pmc_caps.gp_width)
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*/
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inline uint64_t pmc_ff_read(uint8_t i);
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/** @brief Write a single general purpose PMC value
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*
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* Not all architectures support full width writes to the PMCs.
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* If bit 13 (FW_WRITE) in struct pmc_caps.msr is not set the PMC
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* is updated with the 32 bit sign extended version of val!
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*
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* @param i The counter number
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* @param val The counter value (see struct pmc_caps.gp_width)
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*/
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inline int pmc_gp_write(uint8_t i, uint64_t val);
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/** @brief Write a single fixed function PMC value
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*
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* @param i The counter number
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* @param val The counter value (see struct pmc_caps.ff_width)
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*/
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inline int pmc_ff_write(uint8_t i, uint64_t val);
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#endif
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