41 lines
802 B
VHDL
41 lines
802 B
VHDL
-- Short description
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--
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-- Long description
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--
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-- @copyright 2021, Steffen Vogel
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-- @license http://www.gnu.org/licenses/gpl.txt GNU Public License
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-- @author Steffen Vogel <post@steffenvogel.de>
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-- @link https://www.steffenvogel.de
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-- @package
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-- @category
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-- @since
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--
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use ieee.math_real.all;
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library std;
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use std.textio.all;
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entity name is
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generic (
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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input : in std_logic_vector(7 downto 0);
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output : out std_logic_vector(7 downto 0)
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)
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end entity;
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architecture rtl of name is
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begin
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end architecture;
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