143 lines
No EOL
3.2 KiB
VHDL
143 lines
No EOL
3.2 KiB
VHDL
-- Various smaller helpers
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--
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package helpers is
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-- Types
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type axis_data is array (integer range <>) of std_logic_vector(31 downto 0);
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type axis_bus is record
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tdata : std_logic_vector(31 downto 0);
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tvalid : std_logic;
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tlast : std_logic;
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tready : std_logic;
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end record;
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-- Case boolean to std_logic
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function to_std_logic(value : boolean) return std_ulogic;
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-- Wait for c_cycles cylces of i_clk
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procedure wait_clk (
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signal i_clk : in std_logic;
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constant c_cycles : in integer
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);
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-- Toggle pin io_toggle for 1 cycle of i_clk
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procedure toggle (
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signal i_clk : in std_logic;
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signal io_toggle : inout std_logic
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);
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-- Trigger active-low reset for signal reset
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procedure reset (
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signal reset : out std_logic
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);
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-- Pseudo AXI Stream Master BFM
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procedure axis_send (
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signal i_clk : in std_logic;
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constant i_data : in axis_data;
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signal axis_tdata : out std_logic_vector(31 downto 0);
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signal axis_tvalid : out std_logic;
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signal axis_tlast : out std_logic;
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signal axis_tready : in std_logic
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);
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-- Pseudo AXI Steam Slave BFM
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procedure axis_recv (
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signal i_clk : in std_logic;
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signal axis_tdata : in std_logic_vector(31 downto 0);
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signal axis_tvalid : in std_logic;
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signal axis_tlast : in std_logic;
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signal axis_tready : out std_logic
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);
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end package;
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package body helpers is
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procedure wait_clk (
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signal i_clk : in std_logic;
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constant c_cycles : in integer
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) is
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begin
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for I in 1 to c_cycles loop
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wait until rising_edge(i_clk);
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end loop;
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end procedure;
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procedure toggle (
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signal i_clk : in std_logic;
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signal io_toggle : inout std_logic
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) is
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begin
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io_toggle <= io_toggle xor '1';
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wait_clk(i_clk, 1);
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io_toggle <= io_toggle xor '1';
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end procedure;
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procedure reset (
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signal reset : out std_logic
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) is
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begin
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reset <= '0';
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wait for 5 ns;
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reset <= '1';
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end procedure;
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procedure axis_send (
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signal i_clk : in std_logic;
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constant i_data : in axis_data;
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signal axis_tdata : out std_logic_vector(31 downto 0);
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signal axis_tvalid : out std_logic;
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signal axis_tlast : out std_logic;
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signal axis_tready : in std_logic
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) is
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begin
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for i in i_data'range loop
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wait until rising_edge(i_clk) and axis_tready = '1';
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axis_tvalid <= '1';
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axis_tdata <= i_data(i);
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if i = i_data'high then
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axis_tlast <= '1';
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else
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axis_tlast <= '0';
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end if;
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end loop;
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wait until rising_edge(i_clk);
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axis_tvalid <= '0';
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axis_tlast <= '0';
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end procedure;
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procedure axis_recv (
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signal i_clk : in std_logic;
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signal axis_tdata : in std_logic_vector(31 downto 0);
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signal axis_tvalid : in std_logic;
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signal axis_tlast : in std_logic;
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signal axis_tready : out std_logic
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) is
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begin
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axis_tready <= '1';
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loop
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wait until rising_edge(i_clk) and axis_tvalid = '1';
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if axis_tlast = '1' then
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exit;
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end if;
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end loop;
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end procedure;
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function to_std_logic(value : boolean) return std_ulogic is
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begin
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if value then
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return('1');
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else
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return('0');
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end if;
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end function;
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end package body; |