62 lines
No EOL
1.7 KiB
VHDL
62 lines
No EOL
1.7 KiB
VHDL
-- CDC Synchronizer for single pulse signals
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--
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity two_flop_toggle_synchronizer is
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generic (
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-- 4 ns for backward compatibility with spartan3
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META_FFS_MAXDELAY : string := "4.8 ns"
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);
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port (
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i_src_clk : in std_logic;
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i_dst_clk : in std_logic;
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i_rst : in std_logic;
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i_signal : in std_logic;
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o_signal : out std_logic
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);
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end entity;
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architecture rtl of two_flop_toggle_synchronizer is
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signal s_tff : std_logic;
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signal s_resynch : std_logic := '0';
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signal s_resynch_1d : std_logic := '0';
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signal s_resynch_2d : std_logic := '0';
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attribute MAXDELAY : string;
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attribute ASYNC_REG : string;
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attribute MAXDELAY of s_tff : signal is META_FFS_MAXDELAY;
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attribute MAXDELAY of s_resynch : signal is META_FFS_MAXDELAY;
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attribute MAXDELAY of s_resynch_1d : signal is META_FFS_MAXDELAY;
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attribute MAXDELAY of s_resynch_2d : signal is META_FFS_MAXDELAY;
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attribute ASYNC_REG of s_resynch : signal is "TRUE";
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attribute ASYNC_REG of s_resynch_1d : signal is "TRUE";
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attribute ASYNC_REG of s_resynch_2d : signal is "TRUE";
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begin
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TFF: process (i_src_clk, i_rst)
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begin
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if i_rst = '0' then
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s_tff <= '0';
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elsif rising_edge(i_src_clk) then
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s_tff <= s_tff XOR i_signal;
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end if;
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end process;
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EDGE_SYNC: process (i_dst_clk, i_rst)
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begin
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if i_rst = '0' then
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s_resynch <= '0';
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s_resynch_1d <= '0';
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s_resynch_2d <= '0';
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o_signal <= '0';
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elsif rising_edge(i_dst_clk) then
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s_resynch <= s_tff;
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s_resynch_1d <= s_resynch;
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s_resynch_2d <= s_resynch_1d;
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o_signal <= s_resynch_2d xor s_resynch_1d;
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end if;
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end process;
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end architecture; |