yosys/passes/sat/example.ys

read_verilog example.v
proc; opt_clean
sat_solve -set y 1'b1 example001
sat_solve -set y 1'b1 example002
sat_solve -set y 1'b1 example003
Added SAT generator and simple sat_solve command 2013-06-07 13:59:13 +02:00			`read_verilog example.v`
Various improvements in sat_solve pass and SAT generator 2013-06-08 14:11:50 +02:00			`proc; opt_clean`
			`sat_solve -set y 1'b1 example001`
			`sat_solve -set y 1'b1 example002`
			`sat_solve -set y 1'b1 example003`