Added examples/ top-level directory

This commit is contained in:
Clifford Wolf 2015-10-13 15:40:21 +02:00
parent f13e387321
commit f42218682d
17 changed files with 7 additions and 4 deletions

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@ -342,10 +342,10 @@ Then with default config setting:
./yosys -p 'synth; show' tests/simple/fiedler-cooley.v
./yosys -p 'synth_xilinx -top up3down5; show' tests/simple/fiedler-cooley.v
cd ~yosys/techlibs/cmos
cd ~yosys/examples/cmos
cd ~yosys/techlibs/xilinx/example_basys3
cd ~yosys/examples/basys3

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@ -190,7 +190,7 @@ for the given cell library:
If you do not have a liberty file but want to test this synthesis script,
you can use the file techlibs/cmos/cmos_cells.lib from the yosys sources.
you can use the file examples/cmos/cmos_cells.lib from the yosys sources.
Various more complex liberty files (for testing) can be found here:

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@ -2,6 +2,9 @@
A simple example design, based on the Digilent BASYS3 board
This example uses Yosys for synthesis and Xilinx Vivado
for place&route and bit-stream creation.
Running Yosys:
yosys run_yosys.ys

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@ -1,5 +1,5 @@
// Note: Set ENABLE_LIBYOSYS=1 in Makefile or Makefile.conf to build
// yosys-config --exec --cxx -o example --cxxflags --ldflags -lyosys -lstdc++
// yosys-config --exec --cxx -o demomain --cxxflags --ldflags -lyosys -lstdc++
#include <kernel/yosys.h>