Clifford Wolf
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6c84341f22
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Fixed trailing whitespaces
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2015-07-02 11:14:30 +02:00 |
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Clifford Wolf
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caa274ada6
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Added design->rename(module, new_name)
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2015-06-30 01:37:59 +02:00 |
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Clifford Wolf
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99100f367d
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Added "rename -top new_name"
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2015-06-17 09:38:56 +02:00 |
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Clifford Wolf
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f889e3d385
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Fixed iterator invalidation bug in "rename" command
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2015-02-09 00:18:36 +01:00 |
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Clifford Wolf
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a6c96b986b
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Added Yosys::{dict,nodict,vector} container types
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2014-12-26 10:53:21 +01:00 |
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Clifford Wolf
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d92fb5b35e
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Added missing fixup_ports() calls to "rename" command
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2014-11-08 12:38:48 +01:00 |
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Clifford Wolf
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f9a307a50b
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namespace Yosys
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2014-09-27 16:17:53 +02:00 |
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Clifford Wolf
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084685f480
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Implemented "rename -enumerate -pattern"
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2014-08-26 12:51:08 +02:00 |
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Clifford Wolf
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10e5791c5e
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Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
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Clifford Wolf
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4c4b602156
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Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-27 01:51:45 +02:00 |
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Clifford Wolf
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f9946232ad
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Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-27 01:49:51 +02:00 |
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Clifford Wolf
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d68c993ed2
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Changed more code to the new RTLIL::Wire constructors
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2014-07-26 21:30:38 +02:00 |
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Clifford Wolf
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456ae31a8a
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Added "rename -hide" command
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2014-01-02 20:23:34 +01:00 |
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Clifford Wolf
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e729857647
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Improved handling of private names in opt_clean and rename commands
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2013-08-07 18:39:49 +02:00 |
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Clifford Wolf
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a6aeb3dbf0
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Added renaming of wires and cells to "rename" command
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2013-06-19 16:55:43 +02:00 |
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Clifford Wolf
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95e937438f
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Added "rename" command
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2013-06-10 12:37:22 +02:00 |
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