36 commits

Author	SHA1	Message	Date
Clifford Wolf	0bc95f1e04	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
Clifford Wolf	6041f780c3	Prefer noninverting FFs in dfflibmap	2016-04-05 12:51:04 +02:00
Clifford Wolf	9251553592	Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)	2016-02-01 11:49:11 +01:00
Clifford Wolf	452d4bf741	Added support for "dfflibmap -liberty +/..."	2015-09-18 11:55:57 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	522705cc28	Added liberty dont_use support to dfflibmap	2015-05-31 07:51:12 +02:00
Clifford Wolf	2a9ad48eb6	Added ENABLE_NDEBUG makefile options	2015-01-24 12:16:46 +01:00
Clifford Wolf	aad195b88c	Added "dfflibmap -prepare" help	2014-12-24 12:56:05 +01:00
Clifford Wolf	35f5aa300f	Added "dfflibmap -prepare"	2014-12-24 12:19:20 +01:00
Clifford Wolf	84ffe04075	Fixed various VS warnings	2014-10-18 15:20:38 +02:00
Clifford Wolf	4569a747f8	Renamed SIZE() to GetSize() because of name collision on Win32	2014-10-10 17:07:24 +02:00
Clifford Wolf	f9a307a50b	namespace Yosys	2014-09-27 16:17:53 +02:00
Clifford Wolf	d148b0af0d	Fixed inserting of Q-inverters in dfflibmap	2014-08-27 19:44:12 +02:00
Clifford Wolf	19cff41eb4	Changed frontend-api from FILE to std::istream	2014-08-23 15:03:55 +02:00
Clifford Wolf	f092b50148	Renamed $_INV_ cell type to $_NOT_	2014-08-15 14:11:40 +02:00
Clifford Wolf	b9bd22b8c8	More cleanups related to RTLIL::IdString usage	2014-08-02 13:19:57 +02:00
Clifford Wolf	cdae8abe16	Renamed port access function on RTLIL::Cell, added param access functions	2014-07-31 16:38:54 +02:00
Clifford Wolf	10e5791c5e	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00
Clifford Wolf	4c4b602156	Refactoring: Renamed RTLIL::Module::cells to cells_	2014-07-27 01:51:45 +02:00
Clifford Wolf	f8fdc47d33	Manual fixes for new cell connections API	2014-07-26 15:58:23 +02:00
Clifford Wolf	b7dda72302	Changed users of cell->connections_ to the new API (sed command) ... git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'	2014-07-26 15:58:23 +02:00
Clifford Wolf	cc4f10883b	Renamed RTLIL::{Module,Cell}::connections to connections_	2014-07-26 11:58:03 +02:00
Clifford Wolf	2bec47a404	Use only module->addCell() and module->remove() to create and delete cells	2014-07-25 17:56:19 +02:00
Clifford Wolf	91704a7853	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys ... (see https://github.com/cliffordwolf/yosys/pull/28)	2014-03-11 14:24:24 +01:00
Clifford Wolf	cdf0f10760	Fixed dfflibmap for cell libraries with no set-reset-ff	2014-02-15 16:34:12 +01:00
Clifford Wolf	9a00980129	renamed LibertyParer to LibertyParser	2014-01-14 18:57:47 +01:00
Clifford Wolf	334b0cc803	Fixed dfflibmap for unused output ports	2013-12-21 20:47:22 +01:00
Clifford Wolf	8856cec308	Now prefer smallest cells in dfflibmap	2013-12-21 08:42:37 +01:00
Clifford Wolf	1fb29050e5	Cleanup of dfflibmap cellmap exploration code	2013-12-20 14:21:18 +01:00
Clifford Wolf	eaf7d9675d	Further improved dfflibmap cellmap exploration	2013-12-20 12:34:34 +01:00
Clifford Wolf	404bcc2d1e	Fixed dfflibmap endless-loop bug	2013-12-20 12:13:51 +01:00
Clifford Wolf	c904f5e197	Prefer non-inverted clocks in dfflibmap	2013-12-19 13:21:57 +01:00
Clifford Wolf	295e352ba6	Renamed "placeholder" to "blackbox"	2013-11-22 15:01:12 +01:00
Clifford Wolf	0efe16f118	Added placeholder check to dfflibmap and cleaned up some other placeholder checks	2013-10-31 12:27:07 +01:00
Clifford Wolf	dd56004fc0	Added support for sr flip-flops to dfflibmap	2013-10-24 18:20:06 +02:00
Clifford Wolf	b6db2d9b33	Moved dfflibmap from passes/dfflibmap to passes/techmap	2013-10-16 15:32:26 +02:00

Renamed from passes/dfflibmap/dfflibmap.cc (Browse further)