4 commits

Author	SHA1	Message	Date
Clifford Wolf	924d9d6e86	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
Clifford Wolf	8520b7fbe0	Added support for initialized xilinx brams	2015-04-06 17:07:10 +02:00
Clifford Wolf	1b159bc955	Added missing ports and parameters to xilinx brams	2015-02-01 15:42:59 +01:00
Clifford Wolf	d29d26f882	Various cleanups in xilinx techlib	2015-01-18 19:43:54 +01:00

Renamed from techlibs/xilinx/brams.v (Browse further)