Clifford Wolf
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9c7f47bbd5
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Towards Xilinx bram support
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2015-01-06 13:33:51 +01:00 |
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Clifford Wolf
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9ea2511fe8
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Towards Xilinx bram support
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2015-01-05 13:59:04 +01:00 |
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Clifford Wolf
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8898897f7b
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Towards Xilinx bram support
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2015-01-04 14:23:30 +01:00 |
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Clifford Wolf
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327a5d42b6
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Progress in memory_bram
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2014-12-31 22:50:08 +01:00 |
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Clifford Wolf
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94e6b70736
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Added memory_bram (not functional yet)
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2014-12-31 16:53:53 +01:00 |
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Clifford Wolf
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f9a307a50b
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namespace Yosys
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2014-09-27 16:17:53 +02:00 |
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Clifford Wolf
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b64b38eea2
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Renamed $lut ports to follow A-Y naming scheme
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2014-08-15 14:18:40 +02:00 |
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Clifford Wolf
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b17d6531c8
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Added "make PRETTY=1"
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2014-07-24 17:15:01 +02:00 |
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Clifford Wolf
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20175afd29
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Added "techmap -share_map" option
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2013-11-24 19:50:25 +01:00 |
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Clifford Wolf
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ae798d3fd5
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Fixed xilinx/example_sim_counter test bench
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2013-11-24 17:55:46 +01:00 |
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Clifford Wolf
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532091afcb
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Added more generic _TECHMAP_ wire mechanism to techmap pass
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2013-11-23 15:58:06 +01:00 |
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James Walmsley
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40b3551b45
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[EXAMPLES] Ported the mojo counter example to Zynq ZED board.
Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days.
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2013-10-27 21:48:39 +01:00 |
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Clifford Wolf
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88cd2eadf5
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Cleanups in xilinx examples
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2013-10-27 09:58:53 +01:00 |
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Clifford Wolf
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4a3669d871
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Added synth_xilinx command
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2013-10-27 09:51:06 +01:00 |
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Clifford Wolf
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90b016716b
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Moved simple xilinx counter sim example to subdir
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2013-10-27 09:30:17 +01:00 |
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Clifford Wolf
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02f321b6fc
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Xilinx mojo_counter example is now working
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2013-10-27 08:21:56 +01:00 |
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Clifford Wolf
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d635f8adaa
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Renamed techlibs/xilinx7 to techlibs/xilinx
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2013-10-26 22:29:40 +02:00 |
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