Clifford Wolf
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0bc95f1e04
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Added "yosys -D" feature
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2016-04-21 23:28:37 +02:00 |
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Andrew Zonenberg
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d0aaf8d262
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Added GP_SHREG cell
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2016-04-13 23:13:51 -07:00 |
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Andrew Zonenberg
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cdefa60367
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Refactoring: alphabetized cells_sim
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2016-04-13 23:13:39 -07:00 |
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Andrew Zonenberg
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f1679936fe
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Fixed missing semicolon
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2016-04-09 01:18:02 -07:00 |
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Andrew Zonenberg
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58d8715681
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Added GP_RCOSC cell
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2016-04-09 01:17:13 -07:00 |
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Andrew Zonenberg
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01a5f71187
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Fixed assertion failure for non-inferrable counters in some cases
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2016-04-06 23:42:22 -07:00 |
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Andrew Zonenberg
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48c10d90f4
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Added second divider to GP_RINGOSC
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2016-04-06 23:10:34 -07:00 |
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Andrew Zonenberg
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1df559c706
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Added GP_RINGOSC primitive
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2016-04-06 22:40:25 -07:00 |
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Andrew Zonenberg
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c2b909c051
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Added GP_POR
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2016-04-04 21:46:07 -07:00 |
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Andrew Zonenberg
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c01ff05fab
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Added GP_BANDGAP cell
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2016-04-04 16:56:43 -07:00 |
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Andrew Zonenberg
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34667ded53
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Removed more debug prints
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2016-04-01 23:41:03 -07:00 |
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Andrew Zonenberg
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87e7cd9fbd
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Removed forgotten debug code
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2016-04-01 23:39:32 -07:00 |
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Andrew Zonenberg
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2386885f22
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Added GreenPak inverter support
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2016-04-01 21:18:29 -07:00 |
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Andrew Zonenberg
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6dbcf50fa1
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Added support for inferring counters with asynchronous resets. Fixed use-after-free in inference pass.
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2016-04-01 18:07:59 -07:00 |
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Andrew Zonenberg
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f277267916
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Merge https://github.com/cliffordwolf/yosys
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2016-04-01 00:03:00 -07:00 |
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Andrew Zonenberg
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736a998a75
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DFFINIT is now correctly called for all kinds of flipflop, not just DFF
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2016-03-31 23:16:45 -07:00 |
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Andrew Zonenberg
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7498ff8041
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Fixed incorrect port name in cells_map.v
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2016-03-31 22:51:22 -07:00 |
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Clifford Wolf
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2553319081
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Added ScriptPass helper class for script-like passes
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2016-03-31 11:16:34 +02:00 |
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Andrew Zonenberg
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c04a3d2763
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Fixed typo (wasn't written in 2012)
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2016-03-30 23:58:45 -07:00 |
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Clifford Wolf
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ec93680bd5
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Renamed opt_share to opt_merge
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2016-03-31 08:52:49 +02:00 |
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Clifford Wolf
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1d0f0d668a
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Renamed opt_const to opt_expr
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2016-03-31 08:46:56 +02:00 |
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Clifford Wolf
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d31c968d76
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Fixed typo in greenpak4_counters.cc
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2016-03-31 08:00:59 +02:00 |
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Andrew Zonenberg
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984561c034
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Renamed counters pass to greenpak4_counters
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2016-03-30 22:52:01 -07:00 |
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Andrew Zonenberg
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1ae33344f4
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Added initial implementation of "counters" pass to synth_greenpak4. Can only infer non-resettable down counters for now.
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2016-03-30 22:40:14 -07:00 |
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Andrew Zonenberg
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94a6923e7d
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Updated tech lib for greenpak4 counter with some clarifications
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2016-03-30 20:30:25 -07:00 |
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Andrew Zonenberg
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489caf32c5
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Initial work on greenpak4 counter extraction. Doesn't work but a decent start
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2016-03-30 01:07:20 -07:00 |
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Andrew Zonenberg
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3ea6026648
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Added splitnets to synth_greenpak4
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2016-03-29 20:02:59 -07:00 |
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Clifford Wolf
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19c20235b5
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Added more cell help messages
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2016-03-29 15:14:43 +02:00 |
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Clifford Wolf
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8c8b2e72b1
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Fixed indenting in techlibs/greenpak4/gp_dff.lib
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2016-03-29 13:44:14 +02:00 |
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Andrew Zonenberg
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75f0030458
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Added keep constraint to GP_SYSRESET cell
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2016-03-28 23:16:43 -07:00 |
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Andrew Zonenberg
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ea9cc03092
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Added GP_SYSRESET block
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2016-03-28 22:49:46 -07:00 |
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Andrew Zonenberg
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3197b6c372
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Added GP_COUNT8/GP_COUNT14 cells
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2016-03-26 23:29:02 -07:00 |
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Andrew Zonenberg
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31a7567aff
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Changed GP_LFOSC parameter configuration
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2016-03-26 14:13:52 -07:00 |
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Andrew Zonenberg
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44fd3cd149
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Added GP_LFOSC cell
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2016-03-26 13:42:53 -07:00 |
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Andrew Zonenberg
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af15b92c86
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Renamed GP4_V* cells to GP_V* for consistency
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2016-03-26 13:42:41 -07:00 |
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Clifford Wolf
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b4bf787f10
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Added GP_DFFS, GP_DFFR, and GP_DFFSR
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2016-03-23 08:46:10 +01:00 |
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Clifford Wolf
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456c10f16e
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Added GP_DFF INIT parameter
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2016-03-23 08:12:54 +01:00 |
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Clifford Wolf
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ca8f8e30f2
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Improvements in synth_greenpak4, added -part option
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2016-03-21 09:44:52 +01:00 |
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Clifford Wolf
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ff5c61b120
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Added black box modules for all the 7-series design elements (as listed in ug953)
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2016-03-19 11:09:10 +01:00 |
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Clifford Wolf
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a75f94ec4a
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Run dffsr2dff in synth_xilinx
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2016-02-13 08:20:19 +01:00 |
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Clifford Wolf
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0ccfb88728
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Work around DDR dout sim glitches in ice40 SB_IO sim model
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2016-02-07 11:19:48 +01:00 |
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Clifford Wolf
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d69395ca08
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Added dffsr2dff
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2016-02-02 17:19:01 +01:00 |
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Clifford Wolf
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bd10927f45
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Progress in cell library documentation
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2016-02-01 13:58:10 +01:00 |
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Clifford Wolf
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17372d8abd
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Added "abc -luts" option, Improved Xilinx logic mapping
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2016-02-01 12:40:32 +01:00 |
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Clifford Wolf
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2ee608246f
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Re-run ice40_opt in "synth_ice40 -abc2"
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2015-12-22 12:19:11 +01:00 |
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Clifford Wolf
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3102ffbb83
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Improvements in ice40_opt
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2015-12-22 12:18:38 +01:00 |
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Clifford Wolf
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8bf452c364
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Bugfix in ice40_ffinit
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2015-12-22 12:18:06 +01:00 |
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Clifford Wolf
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ec93d258a4
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Improved ice40_ffinit
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2015-12-22 11:15:25 +01:00 |
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Clifford Wolf
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f1b959dc69
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Run opt_const before check in default scripts
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2015-12-22 11:15:05 +01:00 |
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Clifford Wolf
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494e5f24f9
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Added "synth_ice40 -abc2"
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2015-12-08 11:16:26 +01:00 |
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