Clifford Wolf
|
b4f10e342c
|
Various improvements in memory_dff pass
|
2014-08-06 14:31:38 +02:00 |
|
Clifford Wolf
|
2501abe1ee
|
Various fixes and improvements in wreduce pass
|
2014-08-05 19:01:41 +02:00 |
|
Clifford Wolf
|
5b3dc07b9a
|
Removed old "constmap" from wreduce code
|
2014-08-05 16:53:53 +02:00 |
|
Clifford Wolf
|
523df73145
|
Added support for truncating of wires to wreduce pass
|
2014-08-05 14:47:03 +02:00 |
|
Clifford Wolf
|
d3b1a29708
|
Cleanups and improvements in wreduce pass
|
2014-08-05 13:11:04 +02:00 |
|
Clifford Wolf
|
1c182cedb7
|
Added mux support to wreduce command
|
2014-08-05 12:49:53 +02:00 |
|
Clifford Wolf
|
0bb6942218
|
Added "show -signed"
|
2014-08-04 15:40:08 +02:00 |
|
Clifford Wolf
|
ebbbe7fc83
|
Added RTLIL::IdString::in(...)
|
2014-08-04 15:40:07 +02:00 |
|
Clifford Wolf
|
c7f99be3be
|
Fixed "share" for memory read ports
|
2014-08-03 20:22:33 +02:00 |
|
Clifford Wolf
|
027376515a
|
Progress in "wreduce" pass
|
2014-08-03 20:02:42 +02:00 |
|
Clifford Wolf
|
0b02f6ca30
|
Added "wreduce" command (work in progress)
|
2014-08-03 15:02:05 +02:00 |
|
Clifford Wolf
|
014a41fcf3
|
Implemented recursive techmap
|
2014-08-03 12:40:43 +02:00 |
|
Clifford Wolf
|
9bb5298c10
|
Fixes in show command (related to new IdString)
|
2014-08-03 12:40:23 +02:00 |
|
Clifford Wolf
|
08ec33a5e5
|
Implemented simplemap support for "techmap -extern"
|
2014-08-02 21:55:13 +02:00 |
|
Clifford Wolf
|
b6acbc82e6
|
Bugfix in "techmap -extern"
|
2014-08-02 20:54:30 +02:00 |
|
Clifford Wolf
|
8e7361f128
|
Removed at() method from RTLIL::IdString
|
2014-08-02 19:08:02 +02:00 |
|
Clifford Wolf
|
04727c7e0f
|
No implicit conversion from IdString to anything else
|
2014-08-02 18:58:40 +02:00 |
|
Clifford Wolf
|
768eb846c4
|
More bugfixes related to new RTLIL::IdString
|
2014-08-02 18:14:21 +02:00 |
|
Clifford Wolf
|
8fd1c269ac
|
Fixed a performance bug in opt_reduce
|
2014-08-02 15:12:16 +02:00 |
|
Clifford Wolf
|
b9bd22b8c8
|
More cleanups related to RTLIL::IdString usage
|
2014-08-02 13:19:57 +02:00 |
|
Clifford Wolf
|
14412e6c95
|
Preparations for RTLIL::IdString redesign: cleanup of existing code
|
2014-08-02 00:45:25 +02:00 |
|
Clifford Wolf
|
bd74ed7da4
|
Replaced sha1 implementation
|
2014-08-01 19:01:10 +02:00 |
|
Clifford Wolf
|
d13eb7e099
|
Added ModIndex helper class, some changes to RTLIL::Monitor
|
2014-08-01 17:14:32 +02:00 |
|
Clifford Wolf
|
03ef9a75c6
|
Added "test_autotb -n <num_iter>" option
|
2014-08-01 03:55:51 +02:00 |
|
Clifford Wolf
|
32a1cc3efd
|
Renamed modwalker.h to modtools.h
|
2014-07-31 23:30:18 +02:00 |
|
Clifford Wolf
|
cdae8abe16
|
Renamed port access function on RTLIL::Cell, added param access functions
|
2014-07-31 16:38:54 +02:00 |
|
Clifford Wolf
|
b5a9e51b96
|
Added "trace" command
|
2014-07-31 15:02:16 +02:00 |
|
Clifford Wolf
|
e6d33513a5
|
Added module->design and cell->module, wire->module pointers
|
2014-07-31 14:11:39 +02:00 |
|
Clifford Wolf
|
1cb25c05b3
|
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
|
2014-07-31 13:19:47 +02:00 |
|
Clifford Wolf
|
1202f7aa4b
|
Renamed "stdcells.v" to "techmap.v"
|
2014-07-31 02:32:00 +02:00 |
|
Clifford Wolf
|
6ca0c569d9
|
Added "techmap -assert"
|
2014-07-31 02:21:41 +02:00 |
|
Clifford Wolf
|
2541489105
|
Added techmap CONSTMAP feature
|
2014-07-30 22:04:30 +02:00 |
|
Clifford Wolf
|
6400ae3648
|
Added write_file command
|
2014-07-30 19:59:29 +02:00 |
|
Clifford Wolf
|
ceecf5b153
|
Improvements in test_cell
|
2014-07-30 18:49:12 +02:00 |
|
Clifford Wolf
|
273383692a
|
Added "test_cell" command
|
2014-07-29 22:07:41 +02:00 |
|
Clifford Wolf
|
e6df25bf74
|
Renamed "write_autotest" to "test_autotb" and moved to passes/tests/
|
2014-07-29 21:12:50 +02:00 |
|
Clifford Wolf
|
77e2d39cd0
|
Allow "hierarchy -generate" for $__ cells
|
2014-07-29 16:35:13 +02:00 |
|
Clifford Wolf
|
03c96f9ce7
|
Added "techmap -map %{design-name}"
|
2014-07-29 16:35:13 +02:00 |
|
Clifford Wolf
|
397b00252d
|
Added $shift and $shiftx cell types (needed for correct part select behavior)
|
2014-07-29 16:35:13 +02:00 |
|
Clifford Wolf
|
7bd2d1064f
|
Using log_assert() instead of assert()
|
2014-07-28 11:27:48 +02:00 |
|
Clifford Wolf
|
8b0f50792c
|
Added techmap -extern
|
2014-07-27 21:31:18 +02:00 |
|
Clifford Wolf
|
5da343b7de
|
Added topological sorting to techmap
|
2014-07-27 16:43:39 +02:00 |
|
Clifford Wolf
|
0c86d6106c
|
Added SigPool::check(bit)
|
2014-07-27 15:38:02 +02:00 |
|
Clifford Wolf
|
77a1462f2d
|
Fixed bug in opt_clean
|
2014-07-27 15:13:29 +02:00 |
|
Clifford Wolf
|
d07a871d35
|
Improved performance of opt_const on large modules
|
2014-07-27 14:50:25 +02:00 |
|
Clifford Wolf
|
dbb3556e3f
|
Fixed a bug in opt_clean and some RTLIL API usage cleanups
|
2014-07-27 13:19:05 +02:00 |
|
Clifford Wolf
|
d878fcbdc7
|
Added log_cmd_error_expection
|
2014-07-27 12:05:50 +02:00 |
|
Clifford Wolf
|
49f72421d5
|
Using new obj iterator API in a few places
|
2014-07-27 11:32:42 +02:00 |
|
Clifford Wolf
|
10e5791c5e
|
Refactoring: Renamed RTLIL::Design::modules to modules_
|
2014-07-27 11:18:30 +02:00 |
|
Clifford Wolf
|
4c4b602156
|
Refactoring: Renamed RTLIL::Module::cells to cells_
|
2014-07-27 01:51:45 +02:00 |
|