Clifford Wolf
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7f3dc86ecd
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Added RTLIL::SigSpec move constructor and move assignment operator
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2014-07-27 02:11:57 +02:00 |
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Clifford Wolf
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c91570bde3
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Mostly cosmetic changes to rtlil.h
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2014-07-27 02:00:04 +02:00 |
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Clifford Wolf
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4c4b602156
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Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-27 01:51:45 +02:00 |
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Clifford Wolf
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f9946232ad
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Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-27 01:49:51 +02:00 |
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Clifford Wolf
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d68c993ed2
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Changed more code to the new RTLIL::Wire constructors
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2014-07-26 21:30:38 +02:00 |
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Clifford Wolf
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946ddff9ce
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Changed a lot of code to the new RTLIL::Wire constructors
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2014-07-26 20:12:50 +02:00 |
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Clifford Wolf
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267c615640
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Added support for here documents
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2014-07-26 17:21:40 +02:00 |
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Clifford Wolf
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97a59851a6
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Added RTLIL::Cell::has(portname)
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2014-07-26 16:11:28 +02:00 |
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Clifford Wolf
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f8fdc47d33
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Manual fixes for new cell connections API
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2014-07-26 15:58:23 +02:00 |
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Clifford Wolf
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b7dda72302
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Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
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2014-07-26 15:58:23 +02:00 |
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Clifford Wolf
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cd6574ecf6
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Added some missing "const" in rtlil.h
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2014-07-26 15:58:22 +02:00 |
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Clifford Wolf
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7ac9dc7f6e
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Added RTLIL::Module::connections()
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2014-07-26 15:58:21 +02:00 |
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Clifford Wolf
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b03aec6e32
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Added RTLIL::Module::connect(const RTLIL::SigSig&)
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2014-07-26 14:31:47 +02:00 |
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Clifford Wolf
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3719281ed4
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Automatically pack SigSpec on copy/assign
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2014-07-26 13:59:30 +02:00 |
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Clifford Wolf
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e75e495c2b
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Added new RTLIL::Cell port access methods
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2014-07-26 12:22:58 +02:00 |
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Clifford Wolf
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cc4f10883b
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Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-26 11:58:03 +02:00 |
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Clifford Wolf
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4755e14e7b
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Added copy-constructor-like module->addCell(name, other) method
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2014-07-26 00:38:44 +02:00 |
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Clifford Wolf
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2bec47a404
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Use only module->addCell() and module->remove() to create and delete cells
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2014-07-25 17:56:19 +02:00 |
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Clifford Wolf
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c762050e7f
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Added RTLIL::SigSpec is_chunk()/as_chunk() API
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2014-07-25 14:23:10 +02:00 |
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Clifford Wolf
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c4e4f79a2a
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Disabled cover() for non-linux builds
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2014-07-25 12:27:36 +02:00 |
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Clifford Wolf
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7f1789ad1b
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Fixed typo in cover id
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2014-07-25 03:41:53 +02:00 |
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Clifford Wolf
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6aa792c864
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Replaced more old SigChunk programming patterns
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2014-07-24 23:10:58 +02:00 |
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Clifford Wolf
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10d2402e2f
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Added cover_list() API
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2014-07-24 20:47:18 +02:00 |
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Clifford Wolf
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2f54345cff
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Added "cover" command
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2014-07-24 16:14:19 +02:00 |
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Clifford Wolf
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e589289df7
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Some improvements in SigSpec packing/unpacking and checking
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2014-07-24 15:05:41 +02:00 |
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Clifford Wolf
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7679000673
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Now using a dedicated ELF section for all coverage counters
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2014-07-24 15:05:05 +02:00 |
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Clifford Wolf
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22ede43b3f
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Small changes regarding cover() and check() in SigSpec
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2014-07-24 04:46:36 +02:00 |
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Clifford Wolf
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798f713629
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Added support for YOSYS_COVER_FILE env variable
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2014-07-24 04:16:32 +02:00 |
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Clifford Wolf
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1b0d5fc22d
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Added cover() calls to RTLIL::SigSpec methods
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2014-07-24 03:50:28 +02:00 |
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Clifford Wolf
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9cf12570ba
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Added support for YOSYS_COVER_DIR env variable
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2014-07-24 03:49:32 +02:00 |
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Clifford Wolf
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6b1018314c
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Added cover() API
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2014-07-24 03:48:38 +02:00 |
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Clifford Wolf
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82fa356037
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Added hashing to RTLIL::SigSpec relational and equal operators
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2014-07-23 23:58:03 +02:00 |
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Clifford Wolf
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f368d792fb
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Disabled RTLIL::SigSpec::check() in release builds
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2014-07-23 21:42:44 +02:00 |
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Clifford Wolf
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95ac484548
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Fixed release build
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2014-07-23 21:38:18 +02:00 |
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Clifford Wolf
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2a41afb7b2
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Added RTLIL::SigSpec::repeat()
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2014-07-23 21:34:14 +02:00 |
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Clifford Wolf
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c094c53de8
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Removed RTLIL::SigSpec::optimize()
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2014-07-23 20:32:28 +02:00 |
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Clifford Wolf
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8fd8e4a468
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Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always optimized
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2014-07-23 20:11:55 +02:00 |
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Clifford Wolf
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a62c21c9c6
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Removed RTLIL::SigSpec::expand() method
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2014-07-23 19:34:51 +02:00 |
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Clifford Wolf
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4e802eb7f6
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Fixed all users of SigSpec::chunks_rw() and removed it
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2014-07-23 15:36:09 +02:00 |
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Clifford Wolf
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85db102e13
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Replaced RTLIL::SigSpec::operator!=() with inline version
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2014-07-23 15:35:09 +02:00 |
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Clifford Wolf
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ec923652e2
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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
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2014-07-23 09:52:55 +02:00 |
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Clifford Wolf
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a8d3a68971
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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
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2014-07-23 09:49:43 +02:00 |
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Clifford Wolf
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260c19ec5a
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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3
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2014-07-23 09:34:47 +02:00 |
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Clifford Wolf
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c61467a32c
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Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)
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2014-07-23 08:59:54 +02:00 |
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Clifford Wolf
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115dd959d9
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SigSpec refactoring: More cleanups of old SigSpec use pattern
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2014-07-22 23:50:21 +02:00 |
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Clifford Wolf
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9e94f41b89
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SigSpec refactoring: Added RTLIL::SigSpecIterator
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2014-07-22 23:49:26 +02:00 |
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Clifford Wolf
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f80da7b41d
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SigSpec refactoring: added RTLIL::SigSpec::operator[]
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2014-07-22 22:54:03 +02:00 |
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Clifford Wolf
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fd4cbe6275
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SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form
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2014-07-22 22:26:30 +02:00 |
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Clifford Wolf
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a97be0828a
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Removed RTLIL::SigChunk::compare()
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2014-07-22 21:40:52 +02:00 |
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Clifford Wolf
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08e1e25169
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SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api
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2014-07-22 21:33:52 +02:00 |
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