Clifford Wolf
28b3fd05fa
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
2014-07-22 20:58:44 +02:00
Clifford Wolf
7bffde6abd
SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only
2014-07-22 20:39:38 +02:00
Clifford Wolf
4b4048bc5f
SigSpec refactoring: using the accessor functions everywhere
2014-07-22 20:39:37 +02:00
Clifford Wolf
16e5ae0b92
SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and added accessor functions
2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
Clifford Wolf
550ac35873
Added support for scripts with labels
2014-07-21 13:28:18 +02:00
Clifford Wolf
361e0d62ff
Replaced depricated NEW_WIRE macro with module->addWire() calls
2014-07-21 12:42:02 +02:00
Clifford Wolf
1d88f1cf9f
Removed deprecated module->new_wire()
2014-07-21 12:35:06 +02:00
Clifford Wolf
c54d1f2ad1
Bugfix in satgen for cells with wider in- than outputs.
2014-07-21 12:03:41 +02:00
Clifford Wolf
54b0f2e659
Added module->remove(), module->addWire(), module->addCell(), cell->check()
2014-07-21 12:02:55 +02:00
Clifford Wolf
caae6e19df
Added log_ping()
2014-07-21 12:01:45 +02:00
Clifford Wolf
8d04ca7d22
Added call_on_selection() and call_on_module() API
2014-07-20 15:33:06 +02:00
Clifford Wolf
e57db5e9b2
Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion
2014-07-20 11:01:04 +02:00
Clifford Wolf
efa7884026
Added SIZE() macro
2014-07-20 10:36:14 +02:00
Clifford Wolf
a6174aaf5e
Added log_cell()
2014-07-20 10:35:47 +02:00
Clifford Wolf
02f0acb3bc
Fixed log_id() memory corruption
2014-07-19 20:53:29 +02:00
Clifford Wolf
35edac0b31
Added ModWalker helper class
2014-07-19 15:33:00 +02:00
Clifford Wolf
1c288adcc0
Some "const" cleanups in SigMap
2014-07-19 15:32:39 +02:00
Clifford Wolf
a721f7d768
Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>
2014-07-18 11:36:34 +02:00
Clifford Wolf
2d69c309f9
Added function-like cell creation helpers
2014-07-18 10:27:06 +02:00
Clifford Wolf
a8cedb2257
Added log_id() helper function
2014-07-18 10:26:01 +02:00
Clifford Wolf
274c514879
Fixed RTLIL::SigSpec::append_bit() for appending constants
2014-07-17 12:10:57 +02:00
Clifford Wolf
73e0e13d2f
Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal
2014-07-16 11:38:02 +02:00
Clifford Wolf
847e2ee4a1
Use "verilog -sv" to parse .sv files
2014-07-11 13:10:51 +02:00
Clifford Wolf
e275e8eef9
Add support for cell arrays
2014-06-07 11:48:50 +02:00
Clifford Wolf
f9c1cd5edb
Improved error message for options after front-end filename arguments
2014-06-04 09:10:50 +02:00
Clifford Wolf
a5a519a9d1
workaround for OpenBSD 'stdout' implementation
2014-05-03 12:55:56 +02:00
Clifford Wolf
75a5d6bd1e
workaround for OpenBSD 'stdin' implementation
2014-05-02 13:22:26 +02:00
Clifford Wolf
d4a1b0af5b
Added support for dlatchsr cells
2014-03-31 14:14:40 +02:00
Clifford Wolf
e164edc8d1
Fixed typo in RTLIL::Module::addAdff()
2014-03-17 14:41:41 +01:00
Clifford Wolf
ef1795a1e8
Fixed typo in RTLIL::Module::{addSshl,addSshr}
2014-03-15 22:52:10 +01:00
Clifford Wolf
b7c71d92f6
Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API
2014-03-15 14:35:29 +01:00
Clifford Wolf
5da9558fa8
Added log_dump() support for generic pointers
2014-03-14 16:39:50 +01:00
Clifford Wolf
0ac915a757
Progress in Verific bindings
2014-03-14 11:46:13 +01:00
Clifford Wolf
77e5968323
Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API
2014-03-14 11:45:44 +01:00
Clifford Wolf
542afc562f
Hotfix for kernel/compatibility.h
2014-03-13 12:55:15 +01:00
Clifford Wolf
fad8558eb5
Merged OSX fixes from Siesh1oo with some modifications
2014-03-13 12:48:10 +01:00
Siesh1oo
8127d5e8c3
- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname().
...
This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems.
- passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
2014-03-12 23:17:14 +01:00
Clifford Wolf
94c1307c26
Added libs/minisat (copy of minisat git master)
2014-03-12 10:17:51 +01:00
Clifford Wolf
91704a7853
Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
...
(see https://github.com/cliffordwolf/yosys/pull/28 )
2014-03-11 14:24:24 +01:00
Clifford Wolf
78c64a6401
Fixed a typo in RTLIL::Module::addReduce...
2014-03-10 12:07:26 +01:00
Clifford Wolf
fdef064b1d
Added RTLIL::Module::add... helper methods
2014-03-10 03:02:27 +01:00
Clifford Wolf
97710ffad5
Fixed use of frozen literals in SatGen
2014-03-06 13:08:44 +01:00
Clifford Wolf
a1bfde8c5e
Strictly zero-extend unsigned A-inputs of shift operations
2014-03-06 11:53:37 +01:00
Clifford Wolf
9e99984336
Fixed const folding of $bu0 cells
2014-02-27 04:09:32 +01:00
Clifford Wolf
aaaa604853
Added support for $bu0 to SatGen
2014-02-26 21:31:34 +01:00
Clifford Wolf
dab1612f81
Added support for Minisat::SimpSolver + ezSAT frezze() API
2014-02-23 01:35:59 +01:00
Clifford Wolf
b76528d8a5
Fixed small memory leak in Pass::call()
2014-02-23 01:28:29 +01:00
Clifford Wolf
483c99fe46
Added "design -push" and "design -pop"
2014-02-20 23:28:59 +01:00
Clifford Wolf
8f9c707a4c
Improved checking of internal cell conventions
2014-02-08 19:13:49 +01:00
