William Speirs
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fda52f05f2
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Wrapped math in int constructor
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2014-10-17 11:28:14 +02:00 |
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Clifford Wolf
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3838856a9e
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Print "SystemVerilog" in "read_verilog -sv" log messages
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2014-10-16 10:31:54 +02:00 |
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Clifford Wolf
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6b05a9e807
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Fixed handling of invalid array access in mem2reg code
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2014-10-16 00:44:23 +02:00 |
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Clifford Wolf
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f65e1c309f
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Updated .gitignore file for ilang and verilog frontends
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2014-10-15 01:14:38 +02:00 |
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Clifford Wolf
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c3e9922b5d
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Replaced readsome() with read() and gcount()
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2014-10-15 01:12:53 +02:00 |
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William Speirs
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fad0b0c506
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Updated lexers & parsers to include prefixes
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2014-10-15 00:48:19 +02:00 |
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Clifford Wolf
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0b9282a779
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Added make_temp_{file,dir}() and remove_directory() APIs
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2014-10-12 12:11:57 +02:00 |
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Clifford Wolf
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b1596bc0e7
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Added run_command() api to replace system() and popen()
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2014-10-12 10:57:15 +02:00 |
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Clifford Wolf
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35fbc0b35f
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Do not the 'z' modifier in format string (another win32 fix)
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2014-10-11 11:42:08 +02:00 |
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Clifford Wolf
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8263f6a74a
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Fixed win32 troubles with f.readsome()
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2014-10-11 11:36:22 +02:00 |
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Clifford Wolf
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0a651f112f
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Disabled vhdl2verilog command for win32 builds
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2014-10-11 10:46:19 +02:00 |
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Clifford Wolf
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bbd808072b
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Added format __attribute__ to stringf()
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2014-10-10 17:22:08 +02:00 |
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Clifford Wolf
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4569a747f8
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Renamed SIZE() to GetSize() because of name collision on Win32
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2014-10-10 17:07:24 +02:00 |
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Clifford Wolf
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f9a307a50b
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namespace Yosys
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2014-09-27 16:17:53 +02:00 |
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Clifford Wolf
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48b00dccea
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Another $clog2 bugfix
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2014-09-08 12:25:23 +02:00 |
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Clifford Wolf
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680eaaac41
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Fixed $clog2 (off by one error)
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2014-09-06 19:31:04 +02:00 |
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Clifford Wolf
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deff416ea7
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Fixed assignment of out-of bounds array element
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2014-09-06 17:58:27 +02:00 |
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Ruben Undheim
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79cbf9067c
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Corrected spelling mistakes found by lintian
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2014-09-06 08:47:06 +02:00 |
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Clifford Wolf
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8927aa6148
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Removed $bu0 cell type
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2014-09-04 02:07:52 +02:00 |
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Clifford Wolf
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58367cd87a
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Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore
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2014-08-23 15:14:58 +02:00 |
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Clifford Wolf
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19cff41eb4
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Changed frontend-api from FILE to std::istream
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2014-08-23 15:03:55 +02:00 |
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Clifford Wolf
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98442e019d
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Added emscripten (emcc) support to build system and some build fixes
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2014-08-22 16:20:22 +02:00 |
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Clifford Wolf
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e218f0eacf
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Added support for non-standard <plugin>:<c_name> DPI syntax
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2014-08-22 14:30:29 +02:00 |
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Clifford Wolf
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74af3a2b70
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Archibald Rust and Clifford Wolf: ffi-based dpi_call()
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2014-08-22 14:22:09 +02:00 |
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Clifford Wolf
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ad146c2582
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Fixed small memory leak in ast simplify
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2014-08-21 17:33:40 +02:00 |
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Clifford Wolf
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6c5cafcd8b
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Added support for DPI function with different names in C and Verilog
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2014-08-21 17:22:04 +02:00 |
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Clifford Wolf
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085c8e873d
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Added AstNode::asInt()
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2014-08-21 17:11:51 +02:00 |
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Clifford Wolf
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490d7a5bf2
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Fixed memory leak in DPI function calls
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2014-08-21 13:09:47 +02:00 |
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Clifford Wolf
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7bfc4ae120
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Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
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2014-08-21 12:43:51 +02:00 |
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Clifford Wolf
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38addd4c67
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Added support for global tasks and functions
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2014-08-21 12:42:28 +02:00 |
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Clifford Wolf
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640d9fc551
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Added "via_celltype" attribute on task/func
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2014-08-18 14:29:30 +02:00 |
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Clifford Wolf
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acb435b6cf
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Added const folding of AST_CASE to AST simplifier
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2014-08-18 00:02:30 +02:00 |
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Clifford Wolf
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64713647a9
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Improved AST ProcessGenerator performance
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2014-08-17 02:17:49 +02:00 |
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Clifford Wolf
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d491fd8c19
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Use stackmap<> in AST ProcessGenerator
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2014-08-17 00:57:24 +02:00 |
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Clifford Wolf
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7f734ecc09
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Added module->uniquify()
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2014-08-16 23:50:36 +02:00 |
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Clifford Wolf
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83e2698e10
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AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map
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2014-08-16 19:31:59 +02:00 |
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Clifford Wolf
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f092b50148
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Renamed $_INV_ cell type to $_NOT_
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2014-08-15 14:11:40 +02:00 |
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Clifford Wolf
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c7afbd9d8e
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Fixed bug in "read_verilog -ignore_redef"
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2014-08-15 01:53:22 +02:00 |
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Clifford Wolf
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978a933b6a
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Added RTLIL::SigSpec::to_sigbit_map()
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2014-08-14 23:14:47 +02:00 |
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Clifford Wolf
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c83b990458
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Changed the AST genWidthRTLIL subst interface to use a std::map
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2014-08-14 23:02:07 +02:00 |
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Clifford Wolf
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6d56172c0d
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Fixed line numbers when using here-doc macros
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2014-08-14 22:26:30 +02:00 |
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Clifford Wolf
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85e3cc12ac
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Fixed handling of task outputs
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2014-08-14 22:26:10 +02:00 |
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Clifford Wolf
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1bf7a18fec
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Added module->ports
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2014-08-14 16:22:52 +02:00 |
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Clifford Wolf
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f53984795d
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Added support for non-standard """ macro bodies
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2014-08-13 13:03:38 +02:00 |
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Clifford Wolf
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593264e9ed
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Fixed building verific bindings
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2014-08-12 15:21:06 +02:00 |
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Clifford Wolf
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2dc3333734
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Also allow "module foobar(input foo, output bar, ...);" syntax
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2014-08-07 16:41:27 +02:00 |
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Clifford Wolf
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d259abbda2
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Added AST_MULTIRANGE (arrays with more than 1 dimension)
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2014-08-06 15:52:54 +02:00 |
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Clifford Wolf
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91dd87e60b
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Improved scope resolution of local regs in Verilog+AST frontend
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2014-08-05 12:15:53 +02:00 |
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Clifford Wolf
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0129d41efa
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Fixed AST handling of variables declared inside a functions main block
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2014-08-05 08:35:51 +02:00 |
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Clifford Wolf
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b5a3419ac2
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Added support for non-standard "module mod_name(...);" syntax
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2014-08-04 15:40:07 +02:00 |
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