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  • 4b6221478e Added simple $dlatch support to opt_rmdff Clifford Wolf 2015-05-23 09:45:48 +02:00
  • 264eb8eb6e Added ice40 SB_IO sim model Clifford Wolf 2015-05-23 09:30:24 +02:00
  • 98bceed0da Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2015-05-22 08:23:03 +02:00
  • e122c2644e preserve used $-wires with init attribute in opt_clean Clifford Wolf 2015-05-22 08:20:29 +02:00
  • 4744bb95fb Some fixes for $mem in verilog back-end Clifford Wolf 2015-05-20 13:55:50 +02:00
  • 6061b7bd58 bugfix in blif front-end Clifford Wolf 2015-05-18 11:15:49 +02:00
  • 83499dc1ba added vloghtb test_febe.sh Clifford Wolf 2015-05-17 19:54:00 +02:00
  • 3ecb2bf067 Improved .latch support in BLIF front-end Clifford Wolf 2015-05-17 18:58:24 +02:00
  • 2cc4e75914 Added read_blif command Clifford Wolf 2015-05-17 15:25:03 +02:00
  • e5116eeb77 Generalized blifparse API Clifford Wolf 2015-05-17 15:10:37 +02:00
  • 7dad017c9c abc/blifparse files reorganization Clifford Wolf 2015-05-17 14:44:28 +02:00
  • 61512b6f41 Verific build fixes Clifford Wolf 2015-05-17 08:19:52 +02:00
  • c2f30e0de4 Added .barbuf support to abc BLIF parser Clifford Wolf 2015-05-13 06:45:12 +02:00
  • dae00e1d83 changed file() to open() in python scripts Clifford Wolf 2015-05-11 21:46:35 +02:00
  • 42348cddd9 Merge pull request #63 from wluker/verilog-backend-mem Clifford Wolf 2015-05-11 21:38:06 +02:00
  • 3bb5f064b8 Fixed bug in $mem cell verilog code generation. luke whittlesey 2015-05-11 14:05:18 -04:00
  • 9e56739634 Disabled broken $mem support in verilog backend Clifford Wolf 2015-05-10 21:38:41 +02:00
  • e47218e9ea Merge pull request #62 from wluker/verilog-backend-mem Clifford Wolf 2015-05-10 21:23:59 +02:00
  • 6de8fea2c7 Made changes recommended by Clifford Wolf ... luke whittlesey 2015-05-10 11:33:24 -04:00
  • 2c1e150297 Verilog backend for $mem cells should now be able to handle different write-enable bits and RD_TRANSPARENT parameter settings. luke whittlesey 2015-05-08 15:29:51 -04:00
  • c0b68f4848 Added support for $mem cells in the verilog backend. luke whittlesey 2015-05-07 13:03:09 -04:00
  • 7c62318239 Fix for all zero mask eddiehung 2015-05-03 12:53:09 +01:00
  • 079c1205fe Escape '<' and '>' some more eddiehung 2015-05-03 10:37:20 +01:00
  • 7462618591 Fixed memory_unpack for initialized memories Clifford Wolf 2015-04-29 19:55:32 +02:00
  • 96be31de89 Preserve important attributes in splitnets Clifford Wolf 2015-04-29 07:44:57 +02:00
  • f483dce7c2 Added $eq/$neq -> $logic_not/$reduce_bool optimization Clifford Wolf 2015-04-29 07:28:15 +02:00
  • 872e13321c For vtr, escape angle brackets as well eddiehung 2015-04-28 08:56:00 +01:00
  • 058deb777e blifwriter: write out .names for true/false/undef type == '-' eddiehung 2015-04-28 08:55:26 +01:00
  • 9d067fecea ice40_opt bugfix Clifford Wolf 2015-04-27 11:36:13 +02:00
  • 310fde197e iCE40: SB_CARRY const fold -> unmap SB_LUT Clifford Wolf 2015-04-27 10:27:50 +02:00
  • 794d22969d Added simplemap $lut support Clifford Wolf 2015-04-27 10:16:07 +02:00
  • 8d4a675f91 Added iCE40 const folding support for SB_CARRY Clifford Wolf 2015-04-27 08:38:14 +02:00
  • 752851954b Initialization support for all iCE40 bram modes Clifford Wolf 2015-04-26 08:39:31 +02:00
  • b4d7a590e8 initialized iCE40 brams (mode 0) Clifford Wolf 2015-04-25 20:44:51 +02:00
  • 4cc4400514 improved iCE40 SB_RAM40_4K simulation model Clifford Wolf 2015-04-25 20:01:37 +02:00
  • bd0597137d Updated ABC to hg rev 779de2de1481 Clifford Wolf 2015-04-25 18:07:13 +02:00
  • 82a4722f46 More iCE40 bram improvements Clifford Wolf 2015-04-25 18:04:57 +02:00
  • 49859393bb Improved attributes API and handling of "src" attributes Clifford Wolf 2015-04-24 22:04:05 +02:00
  • 687f5a5b12 iCE40 bram progress Clifford Wolf 2015-04-24 15:38:11 +02:00
  • 308a59aa18 iCE40 bram tests and fixes Clifford Wolf 2015-04-24 08:32:07 +02:00
  • d6f7698f59 Added ice40 bram support Clifford Wolf 2015-04-24 00:06:50 +02:00
  • 11f77205f5 Fixed memory_share for unconditional write with part select to memory Clifford Wolf 2015-04-22 06:40:23 +02:00
  • 1277d1bcb8 iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models Clifford Wolf 2015-04-19 21:37:40 +02:00
  • 7ff802e199 Verilog front-end: define `BLACKBOX in -lib mode Clifford Wolf 2015-04-19 21:30:46 +02:00
  • 49ef830464 added sync reset to ice40 test_ffs.sh Clifford Wolf 2015-04-18 09:41:31 +02:00
  • f564a65851 Added ice40 test_arith Clifford Wolf 2015-04-18 09:33:34 +02:00
  • f78fa718be Added ice40 SB_CARRY support Clifford Wolf 2015-04-18 09:33:08 +02:00
  • faa95dd845 don't consider blackbox modules in "sat" command Clifford Wolf 2015-04-18 09:29:03 +02:00
  • 9041f34233 Improved handling of init values in opt_rmdff Clifford Wolf 2015-04-18 08:04:31 +02:00
  • 8cdbcf6859 Bugfix for $_DFF_?_ in "dff2dffe -direct-match" Clifford Wolf 2015-04-17 21:35:59 +02:00
  • 661b647559 Added mapping of synchronous set/reset to iCE40 flow Clifford Wolf 2015-04-17 11:54:25 +02:00
  • e050467b89 Improved "maccmap" help message Clifford Wolf 2015-04-16 18:23:43 +02:00
  • cfdc9fc50e A "#" does start a comment, not a label. Clifford Wolf 2015-04-16 18:13:41 +02:00
  • 31755ed1cf Changed ice40 ICESTORM_CARRYCONST port name Clifford Wolf 2015-04-16 12:09:14 +02:00
  • dc30b034f7 Fixed "dff2dffe -direct-match" Clifford Wolf 2015-04-16 11:47:59 +02:00
  • 3e9e6e1c22 Added simple ice40 dff tests Clifford Wolf 2015-04-16 11:31:15 +02:00
  • 0d344a23d3 improved ice40 dff cell mapping Clifford Wolf 2015-04-16 11:30:56 +02:00
  • f80d020f17 Added "dff2dffe -direct-match" Clifford Wolf 2015-04-16 11:30:17 +02:00
  • 4529c56cc6 use "hierarchy -auto-top" in synth_ice40 Clifford Wolf 2015-04-14 13:45:15 +02:00
  • 06ce496f8d more cells in ice40 cell library Clifford Wolf 2015-04-14 13:44:43 +02:00
  • 2fc2f8f5b3 Added "splice -wires" Clifford Wolf 2015-04-13 19:28:12 +02:00
  • e305d85807 Added handling of bool-output cells to "wreduce" Clifford Wolf 2015-04-13 19:27:49 +02:00
  • 3481f46d1e Improved xilinx "bram1" test Clifford Wolf 2015-04-09 17:12:12 +02:00
  • 7319951145 Added memory_bram "make_outreg" feature Clifford Wolf 2015-04-09 16:08:54 +02:00
  • 44519d4399 Added back-end auto-detect for .edif and .json Clifford Wolf 2015-04-09 15:37:54 +02:00
  • d176e613c2 Minor fixes in handling of "init" attribute Clifford Wolf 2015-04-09 15:12:26 +02:00
  • 229825e1b8 Xilinx DRAMS: RAM64X1D, RAM128X1D Clifford Wolf 2015-04-09 13:37:07 +02:00
  • 25781e329b Fixed const2big performance bug Clifford Wolf 2015-04-09 13:20:19 +02:00
  • be7b9b34ca techmap code cleanup Clifford Wolf 2015-04-09 12:02:26 +02:00
  • b00cad81d7 Towards DRAM support in Xilinx flow Clifford Wolf 2015-04-09 08:17:14 +02:00
  • 21a1cc1b60 Added support for "file names with blanks" Clifford Wolf 2015-04-08 12:14:34 +02:00
  • aa0ab975b9 Removed "techmap -share_map" (use "-map +/filename" instead) Clifford Wolf 2015-04-08 12:13:53 +02:00
  • 8eadd8fb18 Added %M and %C select operators Clifford Wolf 2015-04-07 22:22:09 +02:00
  • 724cead61d Added "pmuxtree" command Clifford Wolf 2015-04-07 20:27:10 +02:00
  • 1f33b2a490 Added "chparam -list" Clifford Wolf 2015-04-07 19:21:30 +02:00
  • 590f74d8f0 Added decoder generation to "muxcover" Clifford Wolf 2015-04-07 18:03:27 +02:00
  • aae5f2ca08 Added hashlib support for std::tuple<> Clifford Wolf 2015-04-07 17:23:30 +02:00
  • f7fb21f185 Added "muxcover" command Clifford Wolf 2015-04-07 15:42:25 +02:00
  • b31e77fd06 Added pool<K>::pop() Clifford Wolf 2015-04-07 15:07:01 +02:00
  • c1af590f4e typo fix Clifford Wolf 2015-04-07 07:43:01 +02:00
  • 329b841aac Added "chparam" command Clifford Wolf 2015-04-07 07:30:14 +02:00
  • 8520b7fbe0 Added support for initialized xilinx brams Clifford Wolf 2015-04-06 17:07:10 +02:00
  • 169d1c4711 Added support for initialized brams Clifford Wolf 2015-04-06 17:06:15 +02:00
  • d19866615b Added Xilinx test case for initialized brams Clifford Wolf 2015-04-06 13:03:37 +02:00
  • 4389d9306e Added Xilinx bram black-box modules Clifford Wolf 2015-04-06 08:44:30 +02:00
  • c0e2b3eb11 Added "port_directions" to write_json output Clifford Wolf 2015-04-06 01:49:58 +02:00
  • a1c62b79d5 Avoid parameter values with size 0 ($mem cells) Clifford Wolf 2015-04-05 18:04:19 +02:00
  • 95944eb69e make all vector-size related integer params in $mem sim model signed Clifford Wolf 2015-04-05 17:26:53 +02:00
  • 706631225e Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types Clifford Wolf 2015-04-05 09:45:14 +02:00
  • c52a4cdeed Added "dffinit", Support for initialized Xilinx DFF Clifford Wolf 2015-04-04 19:00:15 +02:00
  • b0c0ede879 Added "init" attribute support to verilog backend Clifford Wolf 2015-04-04 18:06:52 +02:00
  • 0737bf5fb8 appnote 012 fix Clifford Wolf 2015-04-04 15:13:35 +02:00
  • 1d5d1f79f9 Appnote 012 Clifford Wolf 2015-04-04 13:48:13 +02:00
  • 082550f1f3 Updated ABC to 51705b168d7a Clifford Wolf 2015-04-04 11:47:59 +02:00
  • 3b6ebb62fc Merge pull request #55 from ahmedirfan1983/master Clifford Wolf 2015-04-04 09:35:21 +02:00
  • 13e2e71ebe Update README Ahmed Irfan 2015-04-03 17:11:45 +02:00
  • ed750f0a55 Delete btor.ys Ahmed Irfan 2015-04-03 16:45:54 +02:00
  • e82e4f7df4 Update README Ahmed Irfan 2015-04-03 16:45:14 +02:00
  • ea2e0297d5 separated memory next from write cell Ahmed Irfan 2015-04-03 16:41:50 +02:00
  • bdf6b2b19a Merge branch 'master' of https://github.com/cliffordwolf/yosys Ahmed Irfan 2015-04-03 16:38:07 +02:00