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  • 788bd02f97 Fixed FSM mapping for multiple reset-like signals Clifford Wolf 2014-08-10 12:04:02 +02:00
  • 9d4362990f Fixed "share" for complex scenarios with never-active cells Clifford Wolf 2014-08-09 17:07:20 +02:00
  • b9811d5aff Do not share any $reduce_* cells (its complicated and not worth it anyways) Clifford Wolf 2014-08-09 15:17:54 +02:00
  • 2faef89738 Some improvements in fsm_opt and fsm_map for FSM with unreachable states Clifford Wolf 2014-08-09 14:49:51 +02:00
  • 51aa5544fb Improved FSM tests Clifford Wolf 2014-08-08 14:30:45 +02:00
  • 58ac605470 Another fsm_extract bugfix Clifford Wolf 2014-08-08 14:55:11 +02:00
  • 7067c43ec0 Fixed "fsm -export" Clifford Wolf 2014-08-08 14:49:06 +02:00
  • cb6ca08a53 Fixed sharing of reduce operator Clifford Wolf 2014-08-08 14:24:09 +02:00
  • 7c94024fc3 Fixed fsm_extract for wreduced muxes Clifford Wolf 2014-08-08 13:47:20 +02:00
  • c07774b0b6 Added FSM test bench Clifford Wolf 2014-08-08 13:12:18 +02:00
  • 622ebab671 Added "sat -prove-skip" Clifford Wolf 2014-08-08 13:11:54 +02:00
  • 0b8b8d41eb Fixed build with gcc-4.6 Clifford Wolf 2014-08-07 22:37:01 +02:00
  • c55eb8f8a6 Use "-keepdc" in "miter -equiv -flatten" Clifford Wolf 2014-08-07 16:42:35 +02:00
  • 2dc3333734 Also allow "module foobar(input foo, output bar, ...);" syntax Clifford Wolf 2014-08-07 16:41:27 +02:00
  • 312ee00c9e Added adff2dff.v (for techmap -share_map) Clifford Wolf 2014-08-07 16:14:38 +02:00
  • d259abbda2 Added AST_MULTIRANGE (arrays with more than 1 dimension) Clifford Wolf 2014-08-06 15:43:46 +02:00
  • b4f10e342c Various improvements in memory_dff pass Clifford Wolf 2014-08-06 14:31:38 +02:00
  • 2501abe1ee Various fixes and improvements in wreduce pass Clifford Wolf 2014-08-05 19:01:41 +02:00
  • 5b3dc07b9a Removed old "constmap" from wreduce code Clifford Wolf 2014-08-05 16:53:53 +02:00
  • 523df73145 Added support for truncating of wires to wreduce pass Clifford Wolf 2014-08-05 14:47:03 +02:00
  • d3b1a29708 Cleanups and improvements in wreduce pass Clifford Wolf 2014-08-05 13:11:04 +02:00
  • 1c182cedb7 Added mux support to wreduce command Clifford Wolf 2014-08-05 12:49:53 +02:00
  • 91dd87e60b Improved scope resolution of local regs in Verilog+AST frontend Clifford Wolf 2014-08-05 12:15:53 +02:00
  • 0129d41efa Fixed AST handling of variables declared inside a functions main block Clifford Wolf 2014-08-05 08:35:51 +02:00
  • 0bb6942218 Added "show -signed" Clifford Wolf 2014-08-04 15:33:51 +02:00
  • b5a3419ac2 Added support for non-standard "module mod_name(...);" syntax Clifford Wolf 2014-08-04 15:19:24 +02:00
  • ebbbe7fc83 Added RTLIL::IdString::in(...) Clifford Wolf 2014-08-04 15:08:35 +02:00
  • c7f99be3be Fixed "share" for memory read ports Clifford Wolf 2014-08-03 20:19:50 +02:00
  • 358bf70a21 Added "wreduce" to some of the standard test benches Clifford Wolf 2014-08-03 20:03:16 +02:00
  • 027376515a Progress in "wreduce" pass Clifford Wolf 2014-08-03 20:02:42 +02:00
  • 0b02f6ca30 Added "wreduce" command (work in progress) Clifford Wolf 2014-08-03 15:02:05 +02:00
  • 653edd7a2f Added query() API to ModIndex Clifford Wolf 2014-08-03 15:00:38 +02:00
  • 75423169c5 Added ID() macro for static IdStrings Clifford Wolf 2014-08-03 14:59:13 +02:00
  • 014a41fcf3 Implemented recursive techmap Clifford Wolf 2014-08-03 12:40:43 +02:00
  • 9bb5298c10 Fixes in show command (related to new IdString) Clifford Wolf 2014-08-03 12:40:23 +02:00
  • 08ec33a5e5 Implemented simplemap support for "techmap -extern" Clifford Wolf 2014-08-02 21:55:13 +02:00
  • bc947d4c7b Fixed a va_list corruption in logv_error() Clifford Wolf 2014-08-02 21:54:30 +02:00
  • 88cf00ce78 Be more conservative with printing decimal numbers in verilog backend Clifford Wolf 2014-08-02 21:54:02 +02:00
  • ca1b5d50e0 Improved verilog output for ordinary $mux cells Clifford Wolf 2014-08-02 21:10:08 +02:00
  • b6acbc82e6 Bugfix in "techmap -extern" Clifford Wolf 2014-08-02 20:54:30 +02:00
  • 8e7361f128 Removed at() method from RTLIL::IdString Clifford Wolf 2014-08-02 19:08:02 +02:00
  • 04727c7e0f No implicit conversion from IdString to anything else Clifford Wolf 2014-08-02 18:58:40 +02:00
  • 768eb846c4 More bugfixes related to new RTLIL::IdString Clifford Wolf 2014-08-02 16:03:18 +02:00
  • 08392aad8f Limit size of log_signal buffer to 100 elements Clifford Wolf 2014-08-02 15:52:21 +02:00
  • e590ffc84d Improvements in new RTLIL::IdString implementation Clifford Wolf 2014-08-02 15:44:10 +02:00
  • 8fd1c269ac Fixed a performance bug in opt_reduce Clifford Wolf 2014-08-02 15:12:16 +02:00
  • 60f3dc9923 Implemented new reference counting RTLIL::IdString Clifford Wolf 2014-08-02 15:11:35 +02:00
  • 97ad0623df Fixed memory corruption related to id2cstr() Clifford Wolf 2014-08-02 13:34:07 +02:00
  • b9bd22b8c8 More cleanups related to RTLIL::IdString usage Clifford Wolf 2014-08-02 13:11:01 +02:00
  • 14412e6c95 Preparations for RTLIL::IdString redesign: cleanup of existing code Clifford Wolf 2014-08-02 00:45:25 +02:00
  • 75ffd1643c Added logfile hash to statistics footer Clifford Wolf 2014-08-01 19:43:28 +02:00
  • bd74ed7da4 Replaced sha1 implementation Clifford Wolf 2014-08-01 19:01:10 +02:00
  • 1e224506be Added per-pass cpu usage statistics Clifford Wolf 2014-08-01 18:42:10 +02:00
  • d13eb7e099 Added ModIndex helper class, some changes to RTLIL::Monitor Clifford Wolf 2014-08-01 16:53:15 +02:00
  • 97a17d39e2 Packed SigBit::data and SigBit::offset in a union Clifford Wolf 2014-08-01 15:25:42 +02:00
  • 5e641acc90 Consolidated hana test benches into fewer files Clifford Wolf 2014-08-01 03:57:37 +02:00
  • 03ef9a75c6 Added "test_autotb -n <num_iter>" option Clifford Wolf 2014-08-01 03:55:51 +02:00
  • 32a1cc3efd Renamed modwalker.h to modtools.h Clifford Wolf 2014-07-31 23:30:18 +02:00
  • 62c8a71525 Various cleanups in Makefile, Renamed default configurations Clifford Wolf 2014-07-31 23:14:17 +02:00
  • 069fe0db42 Added compiler + compiler version + compiler flags to version string Clifford Wolf 2014-07-31 23:07:00 +02:00
  • c6fd82c70b Fixed build of verific bindings Clifford Wolf 2014-07-31 16:45:23 +02:00
  • cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions Clifford Wolf 2014-07-31 16:38:54 +02:00
  • b5a9e51b96 Added "trace" command Clifford Wolf 2014-07-31 15:02:16 +02:00
  • cd9407404a Added RTLIL::Monitor Clifford Wolf 2014-07-31 14:34:12 +02:00
  • e6d33513a5 Added module->design and cell->module, wire->module pointers Clifford Wolf 2014-07-31 14:11:39 +02:00
  • 1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace Clifford Wolf 2014-07-31 13:19:47 +02:00
  • 1202f7aa4b Renamed "stdcells.v" to "techmap.v" Clifford Wolf 2014-07-31 02:32:00 +02:00
  • 6ca0c569d9 Added "techmap -assert" Clifford Wolf 2014-07-31 02:21:41 +02:00
  • 41555cde10 Reorganized stdcells.v (no actual code change, just moved and indented stuff) Clifford Wolf 2014-07-31 02:21:06 +02:00
  • 6166c76831 Added "yosys -A" Clifford Wolf 2014-07-31 01:05:27 +02:00
  • e5c245df9d Added "yosys -Q" Clifford Wolf 2014-07-31 00:53:21 +02:00
  • 2541489105 Added techmap CONSTMAP feature Clifford Wolf 2014-07-30 22:04:30 +02:00
  • 7daad40ca4 Fixed counting verilog line numbers for "// synopsys translate_off" sections Clifford Wolf 2014-07-30 20:18:48 +02:00
  • 6400ae3648 Added write_file command Clifford Wolf 2014-07-30 19:59:29 +02:00
  • 7d98645fe8 Added "make -j{N}" support to "make test" Clifford Wolf 2014-07-30 19:21:52 +02:00
  • ceecf5b153 Improvements in test_cell Clifford Wolf 2014-07-30 15:59:38 +02:00
  • 6c05badc43 New techmap default rules for $shr $sshr $shl $sshl Clifford Wolf 2014-07-30 15:59:05 +02:00
  • 3f0a5746ef Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models Clifford Wolf 2014-07-30 17:18:31 +02:00
  • 9b566a7efa Added native support for shift operations to ezSAT Clifford Wolf 2014-07-30 17:17:31 +02:00
  • 45fd26b76e Added "log_dump_val_worker(char *v)" Clifford Wolf 2014-07-30 15:58:21 +02:00
  • e2a029b5d5 Added CodingStyle document Clifford Wolf 2014-07-30 14:10:49 +02:00
  • a7c6b37abf Added "kernel/yosys.h" and "kernel/yosys.cc" Clifford Wolf 2014-07-30 14:10:15 +02:00
  • 273383692a Added "test_cell" command Clifford Wolf 2014-07-29 22:05:00 +02:00
  • e6df25bf74 Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ Clifford Wolf 2014-07-29 21:12:50 +02:00
  • e605af8a49 Fixed Verilog pre-processor for files with no trailing newline Clifford Wolf 2014-07-29 20:14:25 +02:00
  • 2145e57ef0 Bugfix in simlib.v for iverilog Clifford Wolf 2014-07-29 19:23:31 +02:00
  • 77e2d39cd0 Allow "hierarchy -generate" for $__ cells Clifford Wolf 2014-07-29 16:33:56 +02:00
  • 03c96f9ce7 Added "techmap -map %{design-name}" Clifford Wolf 2014-07-29 16:06:27 +02:00
  • 397b00252d Added $shift and $shiftx cell types (needed for correct part select behavior) Clifford Wolf 2014-07-29 14:42:33 +02:00
  • 48822e79a3 Removed left over debug code Clifford Wolf 2014-07-28 19:38:30 +02:00
  • ec58965967 Fixed part selects of parameters Clifford Wolf 2014-07-28 16:45:26 +02:00
  • a03297a7df Set results of out-of-bounds static bit/part select to undef Clifford Wolf 2014-07-28 16:09:50 +02:00
  • 55521c085a Fixed RTLIL code generator for part select of parameter Clifford Wolf 2014-07-28 15:31:19 +02:00
  • 0598bc8708 Fixed width detection for part selects Clifford Wolf 2014-07-28 15:19:34 +02:00
  • 27a872d1e7 Added support for "upto" wires to Verilog front- and back-end Clifford Wolf 2014-07-28 14:25:03 +02:00
  • 3c45277ee0 Added wire->upto flag for signals such as "wire [0:7] x;" Clifford Wolf 2014-07-28 12:12:13 +02:00
  • 7bd2d1064f Using log_assert() instead of assert() Clifford Wolf 2014-07-28 11:08:55 +02:00
  • d86a25f145 Added std::initializer_list<> constructor to SigSpec Clifford Wolf 2014-07-28 10:52:58 +02:00
  • f99495a895 Added cover() to all SigSpec constructors Clifford Wolf 2014-07-28 10:52:30 +02:00
  • ee65dea738 Fixed signdness detection of expressions with bit- and part-selects Clifford Wolf 2014-07-28 10:10:08 +02:00