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  • 5af7f4db72 Added support for "show -pause" and "show -format dot" Clifford Wolf 2013-11-28 13:35:28 +01:00
  • 143a58bccc Added QGraphicsWebView to yosys-svgviewer Clifford Wolf 2013-11-28 11:57:25 +01:00
  • 1268182f0b Updated ABC to 9241719523f6 Clifford Wolf 2013-11-28 00:43:17 +01:00
  • 9826f6ae02 Added some svgviewer code for possible future switch to QGraphicsWebView Clifford Wolf 2013-11-27 20:43:42 +01:00
  • 18e52d81bf Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2013-11-27 09:08:42 +01:00
  • 38e7fa6530 Tighter integration of ABC build Clifford Wolf 2013-11-27 09:08:35 +01:00
  • 0256105ac2 Set version number to 0.1.0+ Clifford Wolf 2013-11-27 06:29:13 +01:00
  • bc3cc88719 Started implementing undef support in "sat" command Clifford Wolf 2013-11-25 21:40:00 +01:00
  • 3d95047ce2 Bugfixes in new "stat" command Clifford Wolf 2013-11-25 21:08:34 +01:00
  • 4c7d6e63ec Added "stat" command Clifford Wolf 2013-11-25 20:43:57 +01:00
  • 61412d167f Improvements in satgen undef handling Clifford Wolf 2013-11-25 16:50:45 +01:00
  • bd65e67d8a Improvements in satgen undef handling Clifford Wolf 2013-11-25 15:12:01 +01:00
  • 11e8118589 Added ezsat vec_const() api Clifford Wolf 2013-11-25 15:10:32 +01:00
  • 8c3f4b3957 Started implementing undef handling in satgen Clifford Wolf 2013-11-25 04:51:33 +01:00
  • 4d43331748 Removed undef feature from ezsat api Clifford Wolf 2013-11-25 02:50:34 +01:00
  • 76f7c10cfc Using simplemap mappers from techmap Clifford Wolf 2013-11-24 23:31:14 +01:00
  • 3ee33cbdaf Added simplemap pass Clifford Wolf 2013-11-24 22:52:30 +01:00
  • 1afe6589df Renamed stdcells_sim.v to simcells.v and fixed blackbox.v Clifford Wolf 2013-11-24 20:44:00 +01:00
  • 8dafecd34d Added module->avail_parameters (for advanced techmap features) Clifford Wolf 2013-11-24 20:29:07 +01:00
  • 4011d47646 Added techmap -D and -I options Clifford Wolf 2013-11-24 20:04:48 +01:00
  • 7d9a90396d Added verilog frontend -ignore_redef option Clifford Wolf 2013-11-24 19:57:42 +01:00
  • 20175afd29 Added "techmap -share_map" option Clifford Wolf 2013-11-24 19:50:25 +01:00
  • 019b301541 Early wire/reg/parameter width calculation in ast/simplify Clifford Wolf 2013-11-24 19:40:23 +01:00
  • 620b7c900a Updated TODOs Clifford Wolf 2013-11-24 17:58:05 +01:00
  • ae798d3fd5 Fixed xilinx/example_sim_counter test bench Clifford Wolf 2013-11-24 17:55:46 +01:00
  • 41205afc39 Added proper dumping of signed/unsigned parameters to verilog backend Clifford Wolf 2013-11-24 17:47:22 +01:00
  • 0ef22c7609 Added support for signed parameters in ilang Clifford Wolf 2013-11-24 17:37:27 +01:00
  • 7eaad2218d Removed now obsolete test cases Clifford Wolf 2013-11-24 17:30:04 +01:00
  • f71e27dbf1 Remove auto_wire framework (smarter than the verilog standard) Clifford Wolf 2013-11-24 17:29:11 +01:00
  • 609caa23b5 Implemented correct handling of signed module parameters Clifford Wolf 2013-11-24 17:17:21 +01:00
  • 1e6836933d Added modelsim support to autotest Clifford Wolf 2013-11-24 15:10:43 +01:00
  • 72b35e0b99 Fixed "flatten" top-module detection: Only use on fully selected designs Clifford Wolf 2013-11-24 14:10:46 +01:00
  • 981677cf09 Fixed "make install" dependencies Clifford Wolf 2013-11-24 05:05:50 +01:00
  • 28093d9dd2 Added "top" attribute to mark top module in hierarchy Clifford Wolf 2013-11-24 05:03:43 +01:00
  • a4edecb0ca Updated command-reference-manual.tex Clifford Wolf 2013-11-23 20:09:47 +01:00
  • db8ce0fe95 AppNote 010 typo fixes and corrections Clifford Wolf 2013-11-23 20:04:51 +01:00
  • e216e0e291 AppNote 010 progress Clifford Wolf 2013-11-23 17:33:26 +01:00
  • 5f9c7fc6ea Improved handling of techmap special wires Clifford Wolf 2013-11-23 16:49:58 +01:00
  • 1de12e1efc Improved handling of initialized registers Clifford Wolf 2013-11-23 16:26:59 +01:00
  • 532091afcb Added more generic _TECHMAP_ wire mechanism to techmap pass Clifford Wolf 2013-11-23 15:58:06 +01:00
  • 9ab850e45e Making prograss on Appnote 010 Clifford Wolf 2013-11-23 05:46:51 +01:00
  • 3c023054bc Progress on AppNote 010 Clifford Wolf 2013-11-22 19:08:29 +01:00
  • bf501b9ba3 Started to write on AppNote 010: Verilog to BLIF Clifford Wolf 2013-11-22 17:33:59 +01:00
  • 7b9ca46f8d Updated command-reference-manual.tex Clifford Wolf 2013-11-22 15:02:40 +01:00
  • 295e352ba6 Renamed "placeholder" to "blackbox" Clifford Wolf 2013-11-22 15:01:12 +01:00
  • c854ad2e7e Some driver changes/fixes Clifford Wolf 2013-11-22 14:53:57 +01:00
  • a362fd81ae Fixed O(n^2) performance bug in verilog preprocessor Clifford Wolf 2013-11-22 14:08:43 +01:00
  • 058ceda6a0 Added more performance measurement infrastructure Clifford Wolf 2013-11-22 14:08:10 +01:00
  • e4429c480e Enable {* .. *} feature per default (removes dependency to REJECT feature in flex) Clifford Wolf 2013-11-22 12:46:02 +01:00
  • 18d003254c Massive performance improvement from refactoring RTLIL::SigSpec::optimize() Clifford Wolf 2013-11-22 04:41:20 +01:00
  • 8e58bb330d Added SigBit struct and refactored RTLIL::SigSpec::extract Clifford Wolf 2013-11-22 04:07:13 +01:00
  • 7b01ba384f Improved make rules for profiling and debugging Clifford Wolf 2013-11-22 04:05:30 +01:00
  • 1c4a6411af Updated abc Clifford Wolf 2013-11-21 22:39:10 +01:00
  • 40d9542647 Implemented $_DFFSR_ expression generator in verilog backend Clifford Wolf 2013-11-21 21:52:30 +01:00
  • 95c94a02fc Fixed async proc detection in mem2reg Clifford Wolf 2013-11-21 21:26:56 +01:00
  • 09471846c5 Major improvements in mem2reg and added "init" sync rules Clifford Wolf 2013-11-21 13:49:00 +01:00
  • 84ced2bb8e Fixed a bug in "add -global_input" Clifford Wolf 2013-11-21 03:01:20 +01:00
  • 64a5f8f75e Added "proc_arst -global_arst" feature Clifford Wolf 2013-11-20 21:00:43 +01:00
  • 08ceb3729e Fixed ilang parser: memory width Clifford Wolf 2013-11-20 19:55:52 +01:00
  • 2279b2a196 Added "add" command (only wires for now) Clifford Wolf 2013-11-20 19:37:40 +01:00
  • 65ad556f3d Another name resolution bugfix for generate blocks Clifford Wolf 2013-11-20 13:57:40 +01:00
  • 92035fb38e Implemented indexed part selects Clifford Wolf 2013-11-20 13:05:27 +01:00
  • c4c299eb5a Do not allow memory bit select on the left side of an assignment Clifford Wolf 2013-11-20 12:18:46 +01:00
  • 0f04738f40 Added "synthesis" in (synopsys|synthesis) comment support Clifford Wolf 2013-11-20 11:44:09 +01:00
  • ac2be2d892 Fixed name resolution of local tasks and functions in generate block Clifford Wolf 2013-11-20 11:05:58 +01:00
  • 19dba2561e Implemented part/bit select on memory read Clifford Wolf 2013-11-20 10:51:32 +01:00
  • d248419fe0 Updated TODOs in README file Clifford Wolf 2013-11-20 02:10:48 +01:00
  • e340532ce5 Added init= attribute for fpga-style reset values Clifford Wolf 2013-11-20 01:49:37 +01:00
  • a1353ec61b Added "make config-sudo" Clifford Wolf 2013-11-19 23:13:41 +01:00
  • 0c91f890c9 Install simlib in datdir Clifford Wolf 2013-11-19 23:05:46 +01:00
  • 7ea7342c18 Large improvements in yosys-config Clifford Wolf 2013-11-19 22:48:48 +01:00
  • 0dfdbd991a Fixed parsing of module arguments when one type is used for many args Clifford Wolf 2013-11-19 20:35:31 +01:00
  • 63285b300c Renamed temp module generated by "abc" pass from "logic" to "netlist" Clifford Wolf 2013-11-19 01:03:57 +01:00
  • c5e26f839c Added additional mem2reg testcase Clifford Wolf 2013-11-18 19:55:39 +01:00
  • 4f2edcf2f9 Fixed two bugs in mem2reg functionality in AST frontend Clifford Wolf 2013-11-18 19:55:12 +01:00
  • 79910a5547 Added dumping of attributes in AST frontend Clifford Wolf 2013-11-18 19:54:36 +01:00
  • 2a25e3bca3 Fixed parsing of default cases when not last case Clifford Wolf 2013-11-18 16:10:50 +01:00
  • de03184150 Fixed mem2reg for reg usage outside always block Clifford Wolf 2013-11-18 12:35:41 +01:00
  • 97f2979bba Added commented-out osu025 maping commands to cmos techmap example Clifford Wolf 2013-11-18 12:01:00 +01:00
  • 7d52eb0ddb Added -v<level> option and some minor driver cleanups Clifford Wolf 2013-11-17 13:26:31 +01:00
  • 2df5cd87b2 Renamed ABCHGPULL to ABCPULL in Makefile Clifford Wolf 2013-11-16 15:17:32 +01:00
  • f3345bd3b4 Improved building of yosys-abc Clifford Wolf 2013-11-13 15:49:42 +01:00
  • a694324a75 Fixed abc pass blif parser for constant bits Clifford Wolf 2013-11-13 15:46:28 +01:00
  • 63060dcd2e Fixed parsing of "parameter integer" Clifford Wolf 2013-11-13 15:30:23 +01:00
  • e5b974fa2a Cleanups and bugfixes in response to new internal cell checker Clifford Wolf 2013-11-11 00:02:28 +01:00
  • 0fd3ebdb23 Added information on all internal cell types to internal checker Clifford Wolf 2013-11-10 23:25:04 +01:00
  • 378cc509cd Call internal checker more often Clifford Wolf 2013-11-10 23:24:21 +01:00
  • 223892ac28 Improved user-friendliness of "sat" and "eval" expression parsing Clifford Wolf 2013-11-09 12:02:27 +01:00
  • 2864cb3b59 Silenced a gcc warning in spice backend Clifford Wolf 2013-11-09 12:01:50 +01:00
  • 18f9477e95 Added verification of SAT model to "eval -vloghammer_report" command Clifford Wolf 2013-11-09 11:38:17 +01:00
  • 259cc1391e More undef-propagation related fixes Clifford Wolf 2013-11-08 11:40:36 +01:00
  • 9f49d538e1 Fixed handling of different signedness in power operands Clifford Wolf 2013-11-08 11:06:11 +01:00
  • b04051a0e2 Fixed keep attribute on wires in opt_clean Clifford Wolf 2013-11-08 05:20:15 +01:00
  • 4abc8e695a Implemented const folding of ternary op with undef select Clifford Wolf 2013-11-08 04:44:09 +01:00
  • 81b8f3292e Removed debug log from const_pow() Clifford Wolf 2013-11-08 04:43:38 +01:00
  • fc6dc0d7b8 Fixed handling of power operator Clifford Wolf 2013-11-07 22:20:00 +01:00
  • d7cb62ac96 Fixed more extend vs. extend_u0 issues Clifford Wolf 2013-11-07 19:19:53 +01:00
  • 02f4f89fdb Disabled const folding of ternary op when select is undef Clifford Wolf 2013-11-07 18:18:16 +01:00
  • 947bd9b96b Renamed extend_un0() to extend_u0() and use it in genrtlil Clifford Wolf 2013-11-07 18:17:10 +01:00
  • 0e1661f84e Fixed type of sign extension in opt_const $eq/$ne handling Clifford Wolf 2013-11-07 16:53:28 +01:00