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  • ffcdc53a18 Don't sign-extend memory bram initialization data Clifford Wolf 2016-05-15 00:05:30 +02:00
  • 864eeadcd9 Added missing "#define HASHLIB_H" Clifford Wolf 2016-05-14 11:43:20 +02:00
  • d05115ceda Minor presentation fixes Clifford Wolf 2016-05-14 11:35:39 +02:00
  • 407cdea0bc Updated min GCC requirement to GCC 4.8 Clifford Wolf 2016-05-11 09:31:53 +02:00
  • b8b39472bb Added manual download link to README Clifford Wolf 2016-05-09 12:43:49 +02:00
  • 570014800a Include <cmath> in yosys.h Clifford Wolf 2016-05-08 10:50:39 +02:00
  • fa76d51941 Merge pull request #162 from azonenberg/master Clifford Wolf 2016-05-08 10:22:01 +02:00
  • 47eace0b9f Added GP_DELAY cell Andrew Zonenberg 2016-05-07 21:29:26 -07:00
  • 41bbad4e4c Fixed typo in port name Andrew Zonenberg 2016-05-07 21:14:42 -07:00
  • b5171541cd Fixed extra semicolon Andrew Zonenberg 2016-05-07 21:14:18 -07:00
  • 85ee88b0ee Fixed typo in parameter name Andrew Zonenberg 2016-05-07 21:14:00 -07:00
  • a0c19aae55 Added simulation timescale declaration Andrew Zonenberg 2016-05-07 21:13:47 -07:00
  • f103bfb9ba Fixes for MXE build Clifford Wolf 2016-05-07 10:53:18 +02:00
  • c3f6e0ea85 Added support for "keep" attribute to shregmap Clifford Wolf 2016-05-07 09:33:16 +02:00
  • 6fe3d5a1cf Added synth_ice40 support for latches via logic loops Clifford Wolf 2016-05-06 23:02:37 +02:00
  • d10dfccabb Added "write_blif -noalias" Clifford Wolf 2016-05-06 15:05:53 +02:00
  • 126da0ad3d Fixed ice40_opt lut unmapping, added "ice40_opt -unlut" Clifford Wolf 2016-05-06 14:32:32 +02:00
  • aadca148da Fixed preservation of important attributes in techmap Clifford Wolf 2016-05-06 13:59:30 +02:00
  • ec1938737b Merge pull request #159 from azonenberg/master Clifford Wolf 2016-05-05 18:18:48 +02:00
  • 2096a05ec2 Changed order of passes for better handling of INIT attributes on "output reg" FFs Andrew Zonenberg 2016-05-04 17:13:54 -07:00
  • 3486637b19 Changed port names in greenpak shregmap Andrew Zonenberg 2016-05-04 17:04:50 -07:00
  • dee1c27a19 Renamed module parameter Andrew Zonenberg 2016-05-04 17:03:45 -07:00
  • a613f171ae Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT cells instead of extract Andrew Zonenberg 2016-05-04 15:55:16 -07:00
  • 9647dc3c07 Added tristate buffer support to iopadmap Clifford Wolf 2016-05-04 22:48:02 +02:00
  • 86add29072 Merge pull request #157 from azonenberg/master Clifford Wolf 2016-05-04 19:12:59 +02:00
  • deb1eccab5 Fixed incorrect signal naming in GP_IOBUF Andrew Zonenberg 2016-05-04 08:06:18 -07:00
  • 2db8dd6d35 Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-05-04 07:23:27 -07:00
  • 7a74ae4c54 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2016-05-04 10:48:42 +02:00
  • 658f93663b Fixed iopadmap attribute handling Clifford Wolf 2016-05-04 10:48:23 +02:00
  • dcee3256d5 Added tri-state I/O extraction for GreenPak Andrew Zonenberg 2016-05-03 22:53:29 -07:00
  • 66095153fd Added GreenPak I/O buffer cells Andrew Zonenberg 2016-05-03 22:03:04 -07:00
  • 9fc9d5f1fb Added comment to clarify GP_ABUF cell Andrew Zonenberg 2016-05-02 20:29:39 -07:00
  • 79460208c9 Added GP_ABUF cell Andrew Zonenberg 2016-05-02 20:27:41 -07:00
  • 12000b90de Merge pull request #154 from azonenberg/master Clifford Wolf 2016-05-02 09:49:07 +02:00
  • 3a85e40f42 Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-05-01 10:07:21 -07:00
  • 06d35ea942 Improved TCL_VERSION detection so it does not read .tclshrc Clifford Wolf 2016-04-29 10:26:22 +02:00
  • fb87022dca Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-04-29 00:57:37 -07:00
  • e01464e2ac Added "qwp -v" Clifford Wolf 2016-04-28 23:17:30 +02:00
  • 134e093e4e Added GP_PGA cell Andrew Zonenberg 2016-04-27 23:07:21 -07:00
  • 0d2923cccd Connections between inputs and inouts are driven by the input Clifford Wolf 2016-04-26 19:49:05 +02:00
  • 958fb29c76 Fixed test_autotb for modules with many cell ports Clifford Wolf 2016-04-25 16:37:11 +02:00
  • 93e107e455 Fixed proc_mux performance bug Clifford Wolf 2016-04-25 10:43:04 +02:00
  • d086224a39 Merge pull request #150 from azonenberg/master Clifford Wolf 2016-04-25 10:33:18 +02:00
  • d57c85111f Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-04-24 22:11:56 -07:00
  • 349d717202 Removed VIN_BUF_EN Andrew Zonenberg 2016-04-24 17:01:21 -07:00
  • b1d6f05fa2 Fixed performance bug in proc_dlatch Clifford Wolf 2016-04-24 19:29:56 +02:00
  • 9aa4b3309c Added "yosys -D ALL" Clifford Wolf 2016-04-24 17:12:34 +02:00
  • 6e215f374d Renamed VOUT to OUT on GP_ACMP cell Andrew Zonenberg 2016-04-23 22:53:49 -07:00
  • 512486dcf3 Added GP_ACMP cell Andrew Zonenberg 2016-04-23 22:33:36 -07:00
  • 09ffebb995 Added "prep -flatten" and "synth -flatten" Clifford Wolf 2016-04-24 00:48:33 +02:00
  • 77aa2031e7 Converted "prep" to ScriptPass Clifford Wolf 2016-04-24 00:48:06 +02:00
  • 096c25d29d Improvements in greenpak4 shreg mapping Clifford Wolf 2016-04-23 23:10:13 +02:00
  • c9c5192cd6 Run clean after splitnets in synth_greenpak4 Clifford Wolf 2016-04-23 23:09:45 +02:00
  • 7f16784f3c Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-04-23 12:22:08 -07:00
  • e13c66122e Added "shregmap -zinit" for greenpak4 tech Clifford Wolf 2016-04-23 20:20:21 +02:00
  • 421b0d715c Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-04-23 10:18:15 -07:00
  • 34195f281f Merge https://github.com/azonenberg/yosys Clifford Wolf 2016-04-23 10:33:32 +02:00
  • f85cfa5666 Added "shregmap" to synth_greenpak4 Clifford Wolf 2016-04-23 10:31:19 +02:00
  • a24021ea20 Converted synth_greenpak4 to ScriptPass Clifford Wolf 2016-04-23 10:27:33 +02:00
  • 2849fd486e Fixed typo in help text Andrew Zonenberg 2016-04-22 23:01:39 -07:00
  • 0cbe70eaa4 Fixed typo Andrew Zonenberg 2016-04-22 19:08:19 -07:00
  • ab11f2aa70 Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-04-22 19:07:55 -07:00
  • 7311be4028 Added "shregmap -tech greenpak4" Clifford Wolf 2016-04-22 19:42:08 +02:00
  • 779e2cc819 Added support for "active high" and "active low" latches in BLIF front-end Clifford Wolf 2016-04-22 18:02:55 +02:00
  • 60ac1bd178 Added support for "active high" and "active low" latches in BLIF back-end Clifford Wolf 2016-04-22 18:00:46 +02:00
  • 965b0d59b5 More flexible handling of initialization values Clifford Wolf 2016-04-22 12:13:06 +02:00
  • 0bc95f1e04 Added "yosys -D" feature Clifford Wolf 2016-04-21 23:28:37 +02:00
  • 1565d1af69 Fixed performance bug in "share" pass Clifford Wolf 2016-04-21 19:47:25 +02:00
  • 5a09fa4553 Fixed handling of parameters and const functions in casex/casez pattern Clifford Wolf 2016-04-21 15:31:54 +02:00
  • f38ca3e18f Improvements in opt_expr Clifford Wolf 2016-04-21 13:02:56 +02:00
  • 1761d08dd2 Bugfix and improvements in memory_share Clifford Wolf 2016-04-21 12:06:07 +02:00
  • d90c1e9522 Added GP_VREF cell Andrew Zonenberg 2016-04-20 20:48:19 -07:00
  • bf64974d43 Merge pull request #149 from azonenberg/master Clifford Wolf 2016-04-19 10:37:04 +02:00
  • 8c9ac5db7b Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-04-18 19:22:52 -07:00
  • f1fa757d0e Added "shregmap -params" Clifford Wolf 2016-04-18 11:58:21 +02:00
  • 525651c8f6 Added "shregmap -zinit" and "shregmap -init" Clifford Wolf 2016-04-18 11:44:10 +02:00
  • b2c36f6136 Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-04-17 08:15:34 -07:00
  • ce7c980ec7 Improvements in "shregmap" Clifford Wolf 2016-04-17 15:37:22 +02:00
  • be570712d8 Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-04-16 15:14:32 -07:00
  • de647a390c Added "shregmap" pass Clifford Wolf 2016-04-16 23:20:49 +02:00
  • fbdb8e7b3e Fixed copy&paste error in log message in lut2mux Clifford Wolf 2016-04-16 23:20:34 +02:00
  • a07f893a5f Minor hashlib bugfix Clifford Wolf 2016-04-16 23:20:11 +02:00
  • d0aaf8d262 Added GP_SHREG cell Andrew Zonenberg 2016-04-13 23:13:51 -07:00
  • cdefa60367 Refactoring: alphabetized cells_sim Andrew Zonenberg 2016-04-13 23:13:39 -07:00
  • f1679936fe Fixed missing semicolon Andrew Zonenberg 2016-04-09 01:18:02 -07:00
  • c1b8d3b580 Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-04-09 01:17:24 -07:00
  • 58d8715681 Added GP_RCOSC cell Andrew Zonenberg 2016-04-09 01:17:13 -07:00
  • 3d9ff912c2 Merge pull request #147 from azonenberg/master Clifford Wolf 2016-04-08 11:58:40 +02:00
  • 01a5f71187 Fixed assertion failure for non-inferrable counters in some cases Andrew Zonenberg 2016-04-06 23:42:22 -07:00
  • 48c10d90f4 Added second divider to GP_RINGOSC Andrew Zonenberg 2016-04-06 23:10:34 -07:00
  • 1df559c706 Added GP_RINGOSC primitive Andrew Zonenberg 2016-04-06 22:40:25 -07:00
  • f6a0f2cf73 Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-04-06 22:31:22 -07:00
  • ace462237f Hashlib indenting fix Clifford Wolf 2016-04-05 13:25:23 +02:00
  • 38245b6733 Added msan origins tracking Clifford Wolf 2016-04-05 13:25:05 +02:00
  • 6041f780c3 Prefer noninverting FFs in dfflibmap Clifford Wolf 2016-04-05 12:51:04 +02:00
  • eaac5bfbc7 Improved formatting of "sat" output tables Clifford Wolf 2016-04-05 08:26:10 +02:00
  • 3920bf58d0 Fixed some typos Clifford Wolf 2016-04-05 08:18:21 +02:00
  • c2b909c051 Added GP_POR Andrew Zonenberg 2016-04-04 21:46:07 -07:00
  • c01ff05fab Added GP_BANDGAP cell Andrew Zonenberg 2016-04-04 16:56:43 -07:00
  • e4e6becba9 Merge pull request #145 from laanwj/master Clifford Wolf 2016-04-03 17:16:26 +02:00