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  • 71f9f40fa9 Fix a few typos in the manual Wladimir J. van der Laan 2016-04-03 14:26:56 +02:00
  • f9d7091c3b Add instructions for building manual on Ubuntu Wladimir J. van der Laan 2016-04-03 14:26:46 +02:00
  • 27e0d29863 Merge pull request #144 from azonenberg/master Clifford Wolf 2016-04-02 10:19:36 +02:00
  • 34667ded53 Removed more debug prints Andrew Zonenberg 2016-04-01 23:41:03 -07:00
  • 87e7cd9fbd Removed forgotten debug code Andrew Zonenberg 2016-04-01 23:39:32 -07:00
  • 2386885f22 Added GreenPak inverter support Andrew Zonenberg 2016-04-01 21:18:29 -07:00
  • b0a28c793c Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-04-01 18:09:08 -07:00
  • 6dbcf50fa1 Added support for inferring counters with asynchronous resets. Fixed use-after-free in inference pass. Andrew Zonenberg 2016-04-01 18:07:59 -07:00
  • 7a4dd27b1b Merge pull request #143 from azonenberg/master Clifford Wolf 2016-04-01 09:13:52 +02:00
  • f277267916 Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-04-01 00:03:00 -07:00
  • 736a998a75 DFFINIT is now correctly called for all kinds of flipflop, not just DFF Andrew Zonenberg 2016-03-31 23:16:45 -07:00
  • 7498ff8041 Fixed incorrect port name in cells_map.v Andrew Zonenberg 2016-03-31 22:51:22 -07:00
  • 2553319081 Added ScriptPass helper class for script-like passes Clifford Wolf 2016-03-31 11:16:34 +02:00
  • 6cafd08ac1 Improved opt_merge support for $pmux cells Clifford Wolf 2016-03-31 09:58:55 +02:00
  • 6f1b6dc322 Added log_dump() support for dict<> and pool<> containers Clifford Wolf 2016-03-31 09:57:44 +02:00
  • e5dd5c0bcc Preserve empty $pmux default cases Clifford Wolf 2016-03-31 09:57:23 +02:00
  • e2f6d61c00 Typo fixes in opt_expr and opt_merge Clifford Wolf 2016-03-31 09:56:56 +02:00
  • c04a3d2763 Fixed typo (wasn't written in 2012) Andrew Zonenberg 2016-03-30 23:58:45 -07:00
  • ec93680bd5 Renamed opt_share to opt_merge Clifford Wolf 2016-03-31 08:52:49 +02:00
  • 1d0f0d668a Renamed opt_const to opt_expr Clifford Wolf 2016-03-31 08:43:28 +02:00
  • d31c968d76 Fixed typo in greenpak4_counters.cc Clifford Wolf 2016-03-31 08:00:59 +02:00
  • cecd0cf788 Merge pull request #142 from azonenberg/master Clifford Wolf 2016-03-31 07:59:55 +02:00
  • 984561c034 Renamed counters pass to greenpak4_counters Andrew Zonenberg 2016-03-30 22:52:01 -07:00
  • 1ae33344f4 Added initial implementation of "counters" pass to synth_greenpak4. Can only infer non-resettable down counters for now. Andrew Zonenberg 2016-03-30 22:40:14 -07:00
  • 1b42e0c471 Reduced log verbosity Andrew Zonenberg 2016-03-30 22:03:50 -07:00
  • ad19e0c64a Continued work on counter extraction. Can recognize compatible RTL counters but not replace with hard macros. Andrew Zonenberg 2016-03-30 21:54:23 -07:00
  • d16d05e415 Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-03-30 20:38:18 -07:00
  • 94a6923e7d Updated tech lib for greenpak4 counter with some clarifications Andrew Zonenberg 2016-03-30 20:30:25 -07:00
  • dd7204c0bd Fixed typo in log message Andrew Zonenberg 2016-03-30 20:30:03 -07:00
  • 0db53284fd We have 2016 for a while now Clifford Wolf 2016-03-30 13:52:26 +02:00
  • 48dbc75bed Added .vhd file extension support Clifford Wolf 2016-03-30 13:24:49 +02:00
  • 489caf32c5 Initial work on greenpak4 counter extraction. Doesn't work but a decent start Andrew Zonenberg 2016-03-30 01:07:20 -07:00
  • 2c15a3a9d0 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2016-03-30 10:02:18 +02:00
  • a47f69536a Added support for installed plugins Clifford Wolf 2016-03-30 10:02:03 +02:00
  • 3ea6026648 Added splitnets to synth_greenpak4 Andrew Zonenberg 2016-03-29 20:02:59 -07:00
  • 19c20235b5 Added more cell help messages Clifford Wolf 2016-03-29 15:12:14 +02:00
  • 8c8b2e72b1 Fixed indenting in techlibs/greenpak4/gp_dff.lib Clifford Wolf 2016-03-29 13:44:14 +02:00
  • d4472ae945 Merge pull request #141 from azonenberg/master Clifford Wolf 2016-03-29 09:53:35 +02:00
  • 75f0030458 Added keep constraint to GP_SYSRESET cell Andrew Zonenberg 2016-03-28 23:16:43 -07:00
  • ea9cc03092 Added GP_SYSRESET block Andrew Zonenberg 2016-03-28 22:49:46 -07:00
  • 95784437ac Merge pull request #137 from ravenexp/master Clifford Wolf 2016-03-28 16:54:23 +02:00
  • 2ec832ddce Merge pull request #138 from SebKuzminsky/help-typo Clifford Wolf 2016-03-28 16:53:47 +02:00
  • aade2c21fa Merge pull request #139 from azonenberg/master Clifford Wolf 2016-03-28 16:53:24 +02:00
  • 3197b6c372 Added GP_COUNT8/GP_COUNT14 cells Andrew Zonenberg 2016-03-26 23:29:02 -07:00
  • 31a7567aff Changed GP_LFOSC parameter configuration Andrew Zonenberg 2016-03-26 14:13:52 -07:00
  • 44fd3cd149 Added GP_LFOSC cell Andrew Zonenberg 2016-03-26 13:42:53 -07:00
  • af15b92c86 Renamed GP4_V* cells to GP_V* for consistency Andrew Zonenberg 2016-03-26 13:42:41 -07:00
  • 73870c1edf fix a cut-n-paste error in the -h help Sebastian Kuzminsky 2016-03-26 11:15:35 -06:00
  • 963c0d2525 Embed DATDIR make variable value into yosys binary. Sergey Kvachonok 2016-03-26 11:01:53 +03:00
  • a922d705d4 Merge pull request #136 from ravenexp/master Clifford Wolf 2016-03-25 09:16:45 +01:00
  • e14055edf0 Optionally use ${CC} when compiling test utils. Sergey Kvachonok 2016-03-25 08:47:45 +03:00
  • d53a16e43a Allow redefining pkg-config Makefile command. Sergey Kvachonok 2016-03-24 16:07:05 +03:00
  • 972f4a9616 Allow redefining binary and data install locations. Sergey Kvachonok 2016-03-24 12:18:21 +03:00
  • 5328a85149 Do not set "nosync" on task outputs, fixes #134 Clifford Wolf 2016-03-24 12:16:32 +01:00
  • 9717495401 Fixed handling of inverters (aka 1-input luts) in nlutmap Clifford Wolf 2016-03-23 08:56:08 +01:00
  • b4bf787f10 Added GP_DFFS, GP_DFFR, and GP_DFFSR Clifford Wolf 2016-03-23 08:46:10 +01:00
  • 456c10f16e Added GP_DFF INIT parameter Clifford Wolf 2016-03-23 08:12:54 +01:00
  • 4f2ea221dc Added ast.h to exported headers Clifford Wolf 2016-03-22 14:46:10 +01:00
  • 043fa0fad0 Cleanup abstract modules at end of "hierarchy -top" Clifford Wolf 2016-03-21 16:33:34 +01:00
  • 2c7e107d7a Support for abstract modules in chparam Clifford Wolf 2016-03-21 16:30:55 +01:00
  • 4f0d4899ce Added support for $stop system task Clifford Wolf 2016-03-21 16:19:51 +01:00
  • ca8f8e30f2 Improvements in synth_greenpak4, added -part option Clifford Wolf 2016-03-21 09:44:52 +01:00
  • bb9374b67c Improvements in ABCEXTERNAL handling Clifford Wolf 2016-03-19 20:02:40 +01:00
  • b471a32ec3 Merge pull request #130 from ravenexp/master Clifford Wolf 2016-03-19 19:46:27 +01:00
  • 2656b2c55a Support calling out to an external ABC. Sergey Kvachonok 2016-03-19 18:36:18 +03:00
  • e5d42ebb4d Added $display %m support, fixed mem leak in $display, fixes #128 Clifford Wolf 2016-03-19 11:51:13 +01:00
  • ff5c61b120 Added black box modules for all the 7-series design elements (as listed in ug953) Clifford Wolf 2016-03-19 11:09:10 +01:00
  • ef4207d5ad Fixed localparam signdness, fixes #127 Clifford Wolf 2016-03-18 12:15:00 +01:00
  • b6d08f39ba Set "nosync" attribute on internal task/function wires Clifford Wolf 2016-03-18 10:53:29 +01:00
  • 33c10350b2 Fixed Verilog parser fix and more similar improvements Clifford Wolf 2016-03-15 12:22:31 +01:00
  • 81d4e9e7c1 Use left-recursive rule for cell_port_list in Verilog parser. Andrew Becker 2016-03-14 19:28:34 +01:00
  • 2a8d5e64f5 Bugfix in write_verilog for RTLIL processes Clifford Wolf 2016-03-14 13:03:28 +01:00
  • dac807fb33 Cleanups and improvements in examples/cmos/ Clifford Wolf 2016-03-11 11:30:01 +01:00
  • 3265795154 Merge commit 'b34385ec924b6067c1f82bdbae923f8062518956' Clifford Wolf 2016-03-11 11:10:44 +01:00
  • 35a6ad4cc1 Fixed typos in verilog_defaults help message Clifford Wolf 2016-03-10 11:14:51 +01:00
  • d117893007 Added "write_edif -nogndvcc" Clifford Wolf 2016-03-08 21:30:45 +01:00
  • dcd4fb9984 Added examples/cxx-api/evaldemo.cc Clifford Wolf 2016-03-08 16:54:15 +01:00
  • e7ed653771 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2016-03-07 11:17:44 +01:00
  • c4aaed099f Using "mfs" and "lutpack" in ABC lut mapping Clifford Wolf 2016-03-07 11:14:11 +01:00
  • b34385ec92 Completed ngspice digital example with verilog tb Uros Platise 2016-03-05 08:34:05 +01:00
  • b0ac32bc03 Added digital (xspice) example code to examples/cmos/ Clifford Wolf 2016-03-02 12:07:57 +01:00
  • 5547fae4cf Be more conservative with net names in spice output Clifford Wolf 2016-03-02 12:02:59 +01:00
  • b36cad75f6 Merge pull request #119 from SebKuzminsky/spelling-fixes Clifford Wolf 2016-02-29 10:18:50 +01:00
  • 7e6426a67d user-facing spelling fixes Sebastian Kuzminsky 2016-02-28 15:14:01 -07:00
  • c89f61c730 We are now in 0.6+ development Clifford Wolf 2016-02-26 17:24:31 +01:00
  • 5869d26da0 Yosys 0.6 yosys-0.6 Clifford Wolf 2016-02-26 16:55:21 +01:00
  • 22c549ab37 Fixed BLIF parser for empty port assignments Clifford Wolf 2016-02-24 09:16:43 +01:00
  • 45af4a4acf Use easyer-to-read unoptimized ceil_log2() Clifford Wolf 2016-02-15 23:06:18 +01:00
  • 7a9257e7b5 Updated ABC to ae7d65e71adc Clifford Wolf 2016-02-15 15:30:46 +01:00
  • 85fe6d176f Updated command reference in manual Clifford Wolf 2016-02-14 11:02:11 +01:00
  • 0761ad6e18 Changelog for upcoming 0.6 release Clifford Wolf 2016-02-14 10:50:19 +01:00
  • 0c4b311242 Fixed more visual studio warnings Clifford Wolf 2016-02-14 09:35:25 +01:00
  • bcc873b805 Fixed some visual studio warnings Clifford Wolf 2016-02-13 17:31:24 +01:00
  • 6f1d694171 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2016-02-13 17:01:29 +01:00
  • 0d7fd2585e Added "int ceil_log2(int)" function Clifford Wolf 2016-02-13 16:52:16 +01:00
  • 0373bd98bb Fixed MXE ABC build Clifford Wolf 2016-02-13 15:43:23 +01:00
  • a75f94ec4a Run dffsr2dff in synth_xilinx Clifford Wolf 2016-02-13 08:20:19 +01:00
  • 7bd329afa0 Support for more Verific primitives (patch I got per email) Clifford Wolf 2016-02-13 08:19:30 +01:00
  • 840a6dc893 Updated ABC Clifford Wolf 2016-02-08 01:13:53 +01:00
  • 0ccfb88728 Work around DDR dout sim glitches in ice40 SB_IO sim model Clifford Wolf 2016-02-07 11:19:48 +01:00