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  • 022f570563 Keep gcc from complaining about uninitialized variables Larry Doolittle 2015-08-14 13:22:17 -07:00
  • 0350074819 Re-created command-reference-manual.tex, copied some doc fixes to online help Clifford Wolf 2015-08-14 11:27:19 +02:00
  • 84bf862f7c Spell check (by Larry Doolittle) Clifford Wolf 2015-08-14 10:56:05 +02:00
  • 80910d13a6 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2015-08-13 09:52:06 +02:00
  • c699d7c614 More ASCII encoding fixes Clifford Wolf 2015-08-13 09:42:24 +02:00
  • ad8efeb13f Fixed CRLF line endings Clifford Wolf 2015-08-13 09:35:00 +02:00
  • 08ad5409a2 Some ASCII encoding fixes (comments and docs) by Larry Doolittle Clifford Wolf 2015-08-13 09:30:20 +02:00
  • 698357dd9a Added "write_smt2 -regs" Clifford Wolf 2015-08-12 17:13:54 +02:00
  • fc20b1c3d2 Fixed "make clean" for out-of-tree builds Clifford Wolf 2015-08-12 16:54:30 +02:00
  • e4ef000b70 Adjust makefiles to work with out-of-tree builds Clifford Wolf 2015-08-12 15:04:44 +02:00
  • c43f38c81b Improved handling of "keep" attributes in hierarchical designs in opt_clean Clifford Wolf 2015-08-12 14:10:14 +02:00
  • bc468cb6f2 Fixed hashlib for 64 bit int keys Clifford Wolf 2015-08-12 13:37:09 +02:00
  • f81bf9bdea Added SMV back-end 'test_cells.sh' script Clifford Wolf 2015-08-12 12:56:20 +02:00
  • 667b015018 Merge pull request #70 from gaomy3832/bugfix Clifford Wolf 2015-08-12 08:45:04 +02:00
  • cbda56d178 Remove unused blackbox modules in opt_clean. Mingyu Gao 2015-08-10 13:14:21 -07:00
  • 8c4c62f3e1 Bugfix for cell hash cache option in opt_share. Mingyu Gao 2015-08-10 13:01:44 -07:00
  • 45ee2ba3b8 Fixed handling of [a-fxz?] in decimal constants Clifford Wolf 2015-08-11 11:32:37 +02:00
  • 2185125760 Added missing ct_all setup to opt_clean Clifford Wolf 2015-08-11 07:54:32 +02:00
  • 021b4a2436 Bugfix for cell hash cache option in opt_share. Mingyu Gao 2015-08-10 13:01:44 -07:00
  • 883e09d8ed Use MEMID as name for $mem cell Clifford Wolf 2015-08-09 13:35:44 +02:00
  • 3565e89a8b Merge pull request #69 from zeldin/master Clifford Wolf 2015-08-07 00:03:39 +02:00
  • c9e56bc428 Added iCE40 WARMBOOT cell Marcus Comstedt 2015-08-06 22:58:17 +02:00
  • 6834461f65 Remove some very strange whitespace in btor.cc (by Larry Doolittle) Clifford Wolf 2015-08-05 22:11:10 +02:00
  • 5dc23975eb Bugfix in SMV back-end for partially unassigned wires Clifford Wolf 2015-08-05 11:36:26 +02:00
  • 4e4b156e13 Added ENABLE_LIBYOSYS Makefile option Clifford Wolf 2015-08-04 20:25:26 +02:00
  • c7fd3fbb68 Added $assert support to SMV back-end Clifford Wolf 2015-08-04 20:05:37 +02:00
  • 31b555ae72 Added libyosys.so build Clifford Wolf 2015-08-04 13:22:49 +02:00
  • c63e5ed7ec Merge pull request #68 from zeldin/master Clifford Wolf 2015-08-01 12:52:10 +02:00
  • c836faae3e Add -noautowire option to verilog frontend Marcus Comstedt 2015-08-01 12:16:54 +02:00
  • 8d6d5c30d9 Added WORDS parameter to $meminit Clifford Wolf 2015-07-31 10:40:09 +02:00
  • 3860c9a9f2 Fixed flatten $meminit handling Clifford Wolf 2015-07-30 21:43:41 +02:00
  • eac0bcd7d3 Improvements in BLIF back-end Clifford Wolf 2015-07-29 17:06:19 +02:00
  • 4513ff1b85 Fixed nested mem2reg Clifford Wolf 2015-07-29 16:37:08 +02:00
  • 516e8828f2 Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle) Clifford Wolf 2015-07-27 22:44:01 +02:00
  • 4d0ba9b3b2 Fixed "check" command for inout ports Clifford Wolf 2015-07-27 09:54:58 +02:00
  • 2a613b1b66 Some cleanups in opt_rmdff Clifford Wolf 2015-07-25 12:01:25 +02:00
  • badc5f7eb9 Added "miter -assert" Clifford Wolf 2015-07-25 11:23:45 +02:00
  • 2397078485 Keep modules with $assume (like $assert) Clifford Wolf 2015-07-25 10:31:52 +02:00
  • 914ae3401e Improved $adff simplification Clifford Wolf 2015-07-24 14:12:50 +02:00
  • c6ca4780e2 iCE40 DFF sim models: init Q regs to 0 Clifford Wolf 2015-07-20 13:05:18 +02:00
  • ad919ae4e3 Fixed techmap processes error msg Clifford Wolf 2015-07-18 12:16:27 +02:00
  • 54588a276a Avoid tristate warning for blackbox ice40/cells_sim.v Clifford Wolf 2015-07-18 11:59:04 +02:00
  • 8393f70538 Some fixes in "select" command Clifford Wolf 2015-07-16 22:10:26 +02:00
  • 55acc51ad4 Fixed YosysJS.create_worker() usage of this.url_prefix Clifford Wolf 2015-07-10 13:20:57 +02:00
  • 85aaf08e53 Improved liberty file test case Clifford Wolf 2015-07-06 17:45:56 +02:00
  • 3049a08912 Updated ABC Clifford Wolf 2015-07-06 17:45:40 +02:00
  • d2ff5d9994 Do not collect disabled $memwr cells Clifford Wolf 2015-07-06 13:28:00 +02:00
  • c4dde71dca Improved YosysJS WebWorker API Clifford Wolf 2015-07-04 17:08:44 +02:00
  • 766dd51447 Bugfix in fsm_extract Clifford Wolf 2015-07-03 18:42:36 +02:00
  • f0c9a099d2 Added "synth -nofsm" Clifford Wolf 2015-07-02 15:25:38 +02:00
  • 6c84341f22 Fixed trailing whitespaces Clifford Wolf 2015-07-02 11:14:30 +02:00
  • 053058d781 Added opt_const -clkinv Clifford Wolf 2015-07-01 10:49:21 +02:00
  • ee9188a5b4 Added logic-loop error handling to freduce Clifford Wolf 2015-06-30 17:11:46 +02:00
  • 7987f23200 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2015-06-30 01:49:55 +02:00
  • 77e89399a6 Bugfix in chparam Clifford Wolf 2015-06-30 01:38:34 +02:00
  • caa274ada6 Added design->rename(module, new_name) Clifford Wolf 2015-06-30 01:37:59 +02:00
  • 358e415918 Added YosysJS.create_worker() Clifford Wolf 2015-06-28 17:47:58 +02:00
  • df0163cd2b iCE40: set min bram efficiency to 2% Clifford Wolf 2015-06-20 09:31:19 +02:00
  • 94fbaff58f Using static mem size of 128 MB in emcc build Clifford Wolf 2015-06-20 08:58:02 +02:00
  • 3123c45415 Added init support to SMV back-end Clifford Wolf 2015-06-19 16:43:02 +02:00
  • 6c6bf4999e Progress in SMV back-end Clifford Wolf 2015-06-19 16:26:53 +02:00
  • 8c79765de5 Progress in SMV back-end Clifford Wolf 2015-06-19 14:08:46 +02:00
  • 8a86162ae9 Progress in SMV back-end Clifford Wolf 2015-06-18 16:29:11 +02:00
  • 8e84418225 Progress in SMV back-end Clifford Wolf 2015-06-17 09:56:42 +02:00
  • 99100f367d Added "rename -top new_name" Clifford Wolf 2015-06-17 09:38:56 +02:00
  • 9f7a5b4ef9 Progress in SMV back-end Clifford Wolf 2015-06-17 07:24:27 +02:00
  • b8c5e27006 Progress in SMV back-end Clifford Wolf 2015-06-16 19:05:26 +02:00
  • ed128b82d7 Added "synth -nordff -noalumacc" Clifford Wolf 2015-06-15 17:07:40 +02:00
  • 52315039c5 Progress in SMV back-end Clifford Wolf 2015-06-15 17:01:01 +02:00
  • 0f01ef61ef Progress in SMV back-end Clifford Wolf 2015-06-15 13:24:17 +02:00
  • ea23bb8aa4 Added "write_smv" skeleton Clifford Wolf 2015-06-15 00:46:27 +02:00
  • 93685a77c6 Removed debug code from write_smt2 Clifford Wolf 2015-06-14 16:22:06 +02:00
  • 66910e15b2 Modernized memory_dff (and fixed a bug) Clifford Wolf 2015-06-14 16:15:51 +02:00
  • f6eca509bb Added "memory -nordff" Clifford Wolf 2015-06-14 15:47:11 +02:00
  • 255dcb27a0 Added write_smt2 -mem Clifford Wolf 2015-06-14 15:46:47 +02:00
  • 285f140f60 Makefile fix for YosysJS build Clifford Wolf 2015-06-11 15:48:40 +02:00
  • 4c733301e6 Fixed cstr_buf for std::string with small string optimization Clifford Wolf 2015-06-11 13:39:49 +02:00
  • 3a6abc9bf6 Improvements in cellaigs.cc and "json -aig" Clifford Wolf 2015-06-11 10:48:16 +02:00
  • 1ae360cf72 AigMaker refactoring Clifford Wolf 2015-06-10 23:00:12 +02:00
  • e534881794 Added "json -aig" Clifford Wolf 2015-06-10 08:13:56 +02:00
  • 56d4822719 Renamed "aig" to "aigmap" Clifford Wolf 2015-06-10 07:24:26 +02:00
  • 85287295b2 Fixed cellaigs port extending Clifford Wolf 2015-06-10 07:16:30 +02:00
  • 66f9ee412a Added "aig" pass Clifford Wolf 2015-06-09 22:33:26 +02:00
  • 9500b564ac synth_ice40 now flattens by default Clifford Wolf 2015-06-09 20:28:17 +02:00
  • e49e2662aa Added cellaigs API Clifford Wolf 2015-06-09 09:54:22 +02:00
  • b57cb4a7fe Merge clock inverters in memory_dff Clifford Wolf 2015-06-09 07:19:04 +02:00
  • c88be7bae5 Merge branch 'verilog-backend-memV2' of github.com:wluker/yosys Clifford Wolf 2015-06-09 06:42:07 +02:00
  • 2f90499e3d $mem cell in verilog backend : grouped writes by clock luke whittlesey 2015-06-08 17:35:40 -04:00
  • de4f4dad3c Fixed "avail_parameters" handling in module clone/copy Clifford Wolf 2015-06-08 14:49:34 +02:00
  • 98650a0609 Added log_dump() support for IdStrings Clifford Wolf 2015-06-08 14:49:02 +02:00
  • 13983e8318 Fixed handling of parameters with reversed range Clifford Wolf 2015-06-08 14:03:06 +02:00
  • a8fe040906 Bug fix in $mem verilog backend + changed tests/bram flow of make test. luke whittlesey 2015-06-04 14:56:13 -04:00
  • 08f9b38a9c Added opt_share -share_all Clifford Wolf 2015-05-31 14:24:34 +02:00
  • 09ef279b60 Added iCE40 PLL cells Clifford Wolf 2015-05-31 13:10:43 +02:00
  • 522705cc28 Added liberty dont_use support to dfflibmap Clifford Wolf 2015-05-31 07:51:12 +02:00
  • 99b8746d27 Fixed signedness of genvar expressions Clifford Wolf 2015-05-29 20:08:00 +02:00
  • c329233f0d Added output args to synth_ice40 Clifford Wolf 2015-05-26 17:04:37 +02:00
  • 08a4af3cde Improvements in BLIF front-end Clifford Wolf 2015-05-24 08:03:21 +02:00
  • 313f570fcc improved ice40 SB_IO sim model Clifford Wolf 2015-05-23 10:17:03 +02:00
  • 9f772eb970 Improved "flatten" handlings of inout ports Clifford Wolf 2015-05-23 10:14:53 +02:00