7 lines
126 B
Verilog
7 lines
126 B
Verilog
module test(out, vout, in, vin);
|
|
output out, vout;
|
|
input in;
|
|
input [3:0] vin;
|
|
assign out = !in;
|
|
assign vout = !vin;
|
|
endmodule
|