yosys/passes
Martin Schmölzer 4f6cda502d Add support for "fsm_export" synthesis attributes to fsm_export pass.
This allows to specify the file name for exported files directly in the HDL
source via the fsm_export=... attribute on the FSM state register.

Verilog example:
    (* fsm_export="my_fsm.kiss2" *)
    reg [3:0] state;

The fsm_export pass now also accepts the option "-noauto". This causes only
FSMs with the fsm_export attribute to be exported, any other FSMs are ignored.

Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
2013-01-08 09:43:35 +01:00
..
abc initial import 2013-01-05 11:13:26 +01:00
dfflibmap initial import 2013-01-05 11:13:26 +01:00
fsm Add support for "fsm_export" synthesis attributes to fsm_export pass. 2013-01-08 09:43:35 +01:00
hierarchy initial import 2013-01-05 11:13:26 +01:00
memory initial import 2013-01-05 11:13:26 +01:00
opt initial import 2013-01-05 11:13:26 +01:00
proc initial import 2013-01-05 11:13:26 +01:00
submod initial import 2013-01-05 11:13:26 +01:00
techmap added .gitignore files 2013-01-05 11:19:11 +01:00