2023-09-08 11:35:18 +02:00
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/* GPU2RTDS IP core
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2023-01-07 17:20:15 +01:00
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*
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* Author: Daniel Krebs <github@daniel-krebs.net>
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2023-01-07 17:32:48 +01:00
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* SPDX-FileCopyrightText: 2017 Daniel Krebs <github@daniel-krebs.net>
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2023-01-07 17:20:15 +01:00
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* SPDX-License-Identifier: Apache-2.0
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2023-09-08 11:35:18 +02:00
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*/
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2023-01-07 17:20:15 +01:00
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2018-05-30 17:24:51 +02:00
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#include <cstring>
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2024-02-29 19:34:27 +01:00
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#include <unistd.h>
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2018-05-30 17:24:51 +02:00
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2024-02-29 19:34:27 +01:00
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#include <villas/fpga/ips/gpu2rtds.hpp>
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2018-08-21 14:25:20 +02:00
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#include <villas/log.hpp>
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2018-05-30 17:24:51 +02:00
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#include <villas/memory_manager.hpp>
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2020-06-14 22:11:15 +02:00
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using namespace villas::fpga::ip;
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bool Gpu2Rtds::init() {
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Hls::init();
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2018-05-30 17:24:51 +02:00
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2024-02-29 19:34:27 +01:00
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auto ®isters = addressTranslations.at(registerMemory);
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2018-05-30 17:24:51 +02:00
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2024-02-29 19:34:27 +01:00
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registerStatus = reinterpret_cast<StatusRegister *>(
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registers.getLocalAddr(registerStatusOffset));
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registerStatusCtrl = reinterpret_cast<StatusControlRegister *>(
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registers.getLocalAddr(registerStatusCtrlOffset));
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registerFrameSize = reinterpret_cast<uint32_t *>(
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registers.getLocalAddr(registerFrameSizeOffset));
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registerFrames =
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reinterpret_cast<uint32_t *>(registers.getLocalAddr(registerFrameOffset));
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2018-05-30 17:24:51 +02:00
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maxFrameSize = getMaxFrameSize();
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logger->info("Max. frame size supported: {}", maxFrameSize);
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return true;
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}
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bool Gpu2Rtds::startOnce(size_t frameSize) {
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*registerFrameSize = frameSize;
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start();
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return true;
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}
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void Gpu2Rtds::dump(spdlog::level::level_enum logLevel) {
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const auto frame_size = *registerFrameSize;
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auto status = *registerStatus;
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logger->log(logLevel, "Gpu2Rtds registers:");
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logger->log(logLevel, " Frame size (words): {:#x}", frame_size);
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logger->log(logLevel, " Status: {:#x}", status.value);
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logger->log(logLevel, " Running: {}",
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(status.is_running ? "yes" : "no"));
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logger->log(logLevel, " Frame too short: {}",
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(status.frame_too_short ? "yes" : "no"));
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logger->log(logLevel, " Frame too long: {}",
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(status.frame_too_long ? "yes" : "no"));
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logger->log(logLevel, " Frame size invalid: {}",
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(status.invalid_frame_size ? "yes" : "no"));
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logger->log(logLevel, " Last count: {}", (int)status.last_count);
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logger->log(logLevel, " Last seq. number: {}", (int)status.last_seq_nr);
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logger->log(logLevel, " Max. frame size: {}",
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(int)status.max_frame_size);
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}
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2020-06-14 22:03:50 +02:00
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//bool Gpu2Rtds::startOnce(const MemoryBlock &mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset)
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//{
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// auto &mm = MemoryManager::get();
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2020-06-11 18:38:46 +02:00
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// if (frameSize > maxFrameSize) {
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// logger->error("Requested frame size of {} exceeds max. frame size of {}",
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// frameSize, maxFrameSize);
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// return false;
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// }
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// auto translationFromIp = mm.getTranslation(
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// getMasterAddrSpaceByInterface(axiInterface),
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// mem.getAddrSpaceId());
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2022-08-30 12:01:47 -04:00
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// // Set address of memory block in HLS IP
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// XGpu2Rtds_Set_baseaddr(&xInstance, translationFromIp.getLocalAddr(0));
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// XGpu2Rtds_Set_doorbell_offset(&xInstance, doorbellOffset);
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// XGpu2Rtds_Set_data_offset(&xInstance, dataOffset);
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// XGpu2Rtds_Set_frame_size(&xInstance, frameSize);
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// // Prepare memory with all zeroes
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// auto translationFromProcess = mm.getTranslationFromProcess(mem.getAddrSpaceId());
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// auto memory = reinterpret_cast<void*>(translationFromProcess.getLocalAddr(0));
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// memset(memory, 0, mem.getSize());
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// // Start IP
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// return start();
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//}
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//bool
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//Gpu2Rtds::updateStatus()
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//{
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2020-06-11 18:38:46 +02:00
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// if (not XGpu2Rtds_Get_status_vld(&xInstance))
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// return false;
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// status.value = XGpu2Rtds_Get_status(&xInstance);
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// return true;
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//}
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2024-02-29 19:34:27 +01:00
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size_t Gpu2Rtds::getMaxFrameSize() {
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*registerFrameSize = 0;
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2018-05-30 17:24:51 +02:00
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start();
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while (not isFinished())
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;
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2018-05-30 17:24:51 +02:00
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2024-02-29 19:34:27 +01:00
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while (not registerStatusCtrl->status_ap_vld)
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;
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2018-05-30 17:24:51 +02:00
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axilite_reg_status_t status = *registerStatus;
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// logger->debug("(*registerStatus).max_frame_size: {}", (*registerStatus).max_frame_size);
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// logger->debug("status.max_frame_size: {}", status.max_frame_size);
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// assert(status.max_frame_size == (*registerStatus).max_frame_size);
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return status.max_frame_size;
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}
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//void
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//Gpu2Rtds::dumpDoorbell(uint32_t doorbellRegister) const
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//{
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// auto &doorbell = reinterpret_cast<reg_doorbell_t&>(doorbellRegister);
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// logger->info("Doorbell register: {:#08x}", doorbell.value);
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// logger->info(" Valid: {}", (doorbell.is_valid ? "yes" : "no"));
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// logger->info(" Count: {}", doorbell.count);
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2022-03-04 03:33:47 -05:00
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// logger->info(" Seq. number: {}", (int) doorbell.seq_nr);
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2018-05-30 17:24:51 +02:00
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//}
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2022-12-02 18:46:00 +01:00
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static char n[] = "gpu2rtds";
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static char d[] = "HLS Gpu2Rtds IP";
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static char v[] = "acs.eonerc.rwth-aachen.de:hls:gpu2rtds:";
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static NodePlugin<Gpu2Rtds, n, d, v> p;
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