VILLASnode/etc/fpga.conf

/** Example configuration file for VILLASfpga / VILLASnode.
 *
 * The syntax of this file is similar to JSON.
 * A detailed description of the format can be found here:
 *   http://www.hyperrealm.com/libconfig/libconfig_manual.html#Configuration-Files
 *
 * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
 * @copyright 2017, Institute for Automation of Complex Power Systems, EONERC
 * @license GNU General Public License (version 3)
 *
 * VILLASnode
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *********************************************************************************/

# Some global settings are used by multiple configuration files
# and therefore defined in separate files
@include "global.conf"
@include "plugins.conf"

############    Dictionary of FPGAs    ############

fpgas = {
	vc707 = {
		id = "10ee:7022";		# Card identification
		slot = "01:00.0";		# Usually only id or slot is required

		do_reset = true;		# Perform a full reset of the FPGA board
						# Requires a IP core named 'axi_reset_0'

		############   List of IP cores on FPGA   ############
		#
		# Every IP core can have the following settings:
		#  baseaddr	Baseaddress as accessible from BAR0 memory region
		#  irq		Interrupt index of MSI interrupt controller
		#  port		Port index of AXI4-Stream interconnect

		ips = {
			### Utility IPs
			axi_pcie_intc_0 = {
				vlnv = "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:1.0";
				baseaddr = 0xb000;
			},
			switch_0 = {
				vlnv = "xilinx.com:ip:axis_interconnect:2.1"
				baseaddr = 0x5000;
				num_ports = 10;
			},
			axi_reset_0 = {
				vlnv = "xilinx.com:ip:axi_gpio:2.0";
				baseaddr = 0x7000;
			},
			timer_0 = {
				vlnv = "xilinx.com:ip:axi_timer:2.0";
				baseaddr = 0x4000;
				irq = 0;
			},

			### Data mover IPs
			dma_0 = {
				vlnv = "xilinx.com:ip:axi_dma:7.1";
				baseaddr = 0x3000;
				port = 1;
				irq = 3; /* 3 - 4 */
			},
			dma_1 = {
				vlnv = "xilinx.com:ip:axi_dma:7.1";
				baseaddr = 0x2000;
				port = 6;
				irq = 3; /* 3 - 4 */
			},
			fifo_mm_s_0 = {
				vlnv = "xilinx.com:ip:axi_fifo_mm_s:4.1";
				baseaddr = 0x6000;
				baseaddr_axi4 = 0xC000;
				port = 2;
				irq = 2;
			},

			### Interface IPs
			rtds_axis_0 = {
				vlnv = "acs.eonerc.rwth-aachen.de:user:rtds_axis:1.0";
				baseaddr = 0x8000;
				port = 0;
				irq = 5; /* 5 -7 */
			},

			### Model IPs
			hls_dft_0 = {
				vlnv = "acs.eonerc.rwth-aachen.de:hls:hls_dft:1.0";
				baseaddr = 0x9000;
				port = 5;
				irq = 1;

				period = 400; /* in samples: 20ms / 50uS = 400*/
				harmonics = [ 0, 1, 3, 5, 7 ]
				decimation = 0; /* 0 = disabled */
				//harmonics = [ 0, 1, 2, 5, 22 ]
			},
			axis_data_fifo_0 = {
				vlnv = "xilinx.com:ip:axis_data_fifo:1.1";
				port = 3;
			},
			axis_data_fifo_1 = {
				vlnv = "xilinx.com:ip:axis_data_fifo:1.1";
				port = 6;
			},
		}

		############   Switch config   ############
		# Requires a single IP core with VLNV:
		#  xilinx.com:ip:axis_interconnect
		paths = (
	//		{ in = "fifo_mm_s_0",	out = "fifo_mm_s_0" },			# Loopback fifo_mm_s_0
	//		{ in = "dma_0",		out = "dma_0" },			# Loopback dma_0
	//		{ in = "dma_1",		out = "dma_1" }				# Loopback dma_1
	//		{ in = "rtds_axis_0",	out = "fifo_mm_s_0", reverse = true }	# Linux <-> RTDS
	//		{ in = "rtds_axis_0",	out = "dma_0", reverse = true }		# Linux (dma_0) <-> RTDS
			{ in = "rtds_axis_0",	out = "dma_1", reverse = true }		# Linux (dma_1) <-> RTDS
	//		{ in = "rtds_axis_0",	out = "fifo_mm_s_0", reverse = true }	# Linux (fifo_mm_s_0) <-> RTDS
	//		{ in = "dma_0",		out = "hls_dft_0", reverse = true }	# DFT <-> Linux
	//		{ in = "rtds_axis_0",	out = "hls_dft_0", reverse = true },	# DFT <-> RTDS
		)
	}
}

############    Dictionary of nodes    ############

nodes = {
	dma_0 = {
		type = "fpga";				# Datamovers to VILLASfpga
		datamover = "dma_0";			# Name of IP core in fpga.ips
		use_irqs = false;			# Use polling or MSI interrupts?
	},
	dma_1 = {
		type = "fpga";
		datamover = "dma_1";
		use_irqs = false;
	},
	fifo_0 = {
		type = "fpga";
		datamover = "fifo_mm_s_0";
		use_irqs = false;
	},
	simple_circuit = {
		type = "cbuilder";
		model = "simple_circuit",
		timestep = 25e-6;			# in seconds
		parameters = [
			1.0,				# R2 = 1 Ohm
			0.001				# C2 = 1000 uF
		];
	}
}

############       List of paths       ############

paths = (
	{ in = "dma_1", out = "simple_circuit", reverse = true }
)