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https://git.rwth-aachen.de/acs/public/villas/node/
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50 lines
1.2 KiB
C
50 lines
1.2 KiB
C
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/** AXI Stream interconnect related helper functions
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*
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* These functions present a simpler interface to Xilinx' AXI Stream switch driver (XAxis_Switch_*)
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*
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2015-2016, Steffen Vogel
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* This file is part of S2SS. All Rights Reserved. Proprietary and confidential.
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* Unauthorized copying of this file, via any medium is strictly prohibited.
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**********************************************************************************/
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#include "fpga/switch.h"
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int switch_init(XAxis_Switch *sw, char *baseaddr, int micnt, int sicnt)
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{
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int ret;
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/* Setup AXI-stream switch */
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XAxis_Switch_Config sw_cfg = {
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.BaseAddress = (uintptr_t) baseaddr,
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.MaxNumMI = micnt,
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.MaxNumSI = sicnt
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};
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ret = XAxisScr_CfgInitialize(sw, &sw_cfg, (uintptr_t) baseaddr);
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if (ret != XST_SUCCESS)
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return -1;
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#if 0
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ret = XAxisScr_SelfTest(sw);
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if (ret != TRUE)
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return -1;
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#endif
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/* Disable all masters */
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XAxisScr_RegUpdateDisable(sw);
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XAxisScr_MiPortDisableAll(sw);
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XAxisScr_RegUpdateEnable(sw);
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return 0;
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}
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int switch_connect(XAxis_Switch *sw, int mi, int si)
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{
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XAxisScr_RegUpdateDisable(sw);
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XAxisScr_MiPortEnable(sw, mi, si);
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XAxisScr_RegUpdateEnable(sw);
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return 0;
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}
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