added VILLASfpga code

.gitignore

@@ -7,5 +7,6 @@ node
 pipe
 test
 signal
+fpga
 
 thirdparty/

config-fpga.h

@@ -0,0 +1,111 @@
+/** Hardcoded configuration for VILLASfpga
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#ifndef _CONFIG_FPGA_H_
+#define _CONFIG_FPGA_H_
+
+#define AFFINITY		(1 << 3)
+#define PRIORITY		90
+
+#define RTDS_DM_FIFO		1
+#define RTDS_DM_DMA_SIMPLE	2
+#define RTDS_DM_DMA_SG		3
+#define DATAMOVER		RTDS_DM_DMA_SIMPLE
+
+/** PCIe BAR number of VILLASfpga registers */
+#define PCI_BAR			0
+
+/** AXI Bus frequency for all components
+ * except RTDS AXI Stream bridge which runs at RTDS_HZ (100 Mhz) */
+#define AXI_HZ			125000000 // 125 MHz
+
+#define virt_to_axi(virt, map) ((char *) ((char *) virt - map))
+#define virt_to_dma(virt, dma) ((char *) ((char *) virt - dma) + BASEADDR_HOST)
+#define dma_to_virt(addr, dma) ((char *) ((char *) addr - BASEADDR_HOST) + dma)
+
+#if 0
+/** Base addresses in AXI bus of FPGA */
+enum {
+	BASEADDR_BRAM		= 0x0000, /* 8 KB Block RAM for DMA SG descriptors */
+	BASEADDR_XSG		= 0x2000, /* Xilinx System Generator Model */
+	BASEADDR_DMA_SG		= 0x3000, /* Scatter Gather DMA controller registers */
+	BASEADDR_TIMER		= 0x4000, /* Timer Counter registers */
+	BASEADDR_SWITCH		= 0x5000, /* AXI Stream switch registers */
+	BASEADDR_FIFO_MM	= 0x6000, /* Memory-mapped to AXI Stream FIFO */
+	BASEADDR_RESET		= 0x7000, /* Internal Reset register */
+	BASEADDR_RTDS		= 0x8000, /* RTDS to AXI Stream bridge */
+	BASEADDR_HLS		= 0x9000, /* High-level Synthesis model registers */
+	BASEADDR_DMA_SIMPLE	= 0xA000, /* Simple DMA controller registers */
+	BASEADDR_INTC		= 0xB000, /* PCIe MSI Interrupt controller registers */
+	BASEADDR_FIFO_MM_AXI4	= 0xC000, /* AXI4 (full) interface of AXI Stream FIFO */
+	BASEADDR_HOST		= 0x80000000 /* Start of host memory (0x0 of IOMMU) */
+};
+
+/** MSI vector table for VILLASfpga components */
+enum {
+	MSI_TMRCTR0		= 0, /* Sensivity: rising edge, synchronous: axi_clk */
+	MSI_TMRCTR1		= 1, /* Sensivity: rising edge, synchronous: axi_clk */
+	MSI_FIFO_MM		= 2, /* Sensivity: level high,  synchronous: axi_clk */
+	MSI_DMA_MM2S		= 3, /* Sensivity: level high,  synchronous: axi_clk */
+	MSI_DMA_S2MM		= 4, /* Sensivity: level high,  synchronous: axi_clk */
+	MSI_RTDS_TS		= 5, /* Sensivity: rising edge, synchronous: rtds_clk100m (New timestep started) */
+	MSI_RTDS_OVF		= 6, /* Sensivity: rising edge, synchronous: rtds_clk100m (UserTxInProgress overlapped with UserTStepPulse)*/
+	MSI_RTDS_CASE		= 7  /* Sensivity: rising edge, synchronous: rtds_clk100m (New RSCAD case started) */
+};
+
+/** Mapping of VILLASfpga components to AXI Stream interconnect ports */
+enum {
+	AXIS_SWITCH_RTDS	= 0,
+	AXIS_SWITCH_DMA_SG	= 1,
+	AXIS_SWITCH_FIFO_MM	= 2,
+	AXIS_SWITCH_FIFO0	= 3,
+	AXIS_SWITCH_XSG		= 4,
+	AXIS_SWITCH_HLS		= 5,
+	AXIS_SWITCH_FIFO1	= 6,
+	AXIS_SWITCH_DMA_SIMPLE	= 7,
+	AXI_SWITCH_NUM		= 8 /* Number of master and slave interfaces */
+};
+#else
+  #define HAS_DMA_SIMPLE	1
+  #define HAS_SWITCH		1
+  #define HAS_XSG		1
+
+/** Base addresses in AXI bus of FPGA */
+enum {
+	BASEADDR_SWITCH		= 0x0000, /* AXI Stream switch registers */
+	BASEADDR_DMA_SIMPLE	= 0x1000, /* Simple DMA controller registers */
+	BASEADDR_RESET		= 0x2000, /* Internal Reset register */
+	BASEADDR_RTDS		= 0x3000, /* RTDS to AXI Stream bridge */
+	BASEADDR_XSG		= 0x4000, /* Xilinx System Generator Model */
+	BASEADDR_INTC		= 0x5000, /* PCIe MSI Interrupt controller registers */
+	BASEADDR_PCIE		= 0x10000000, /* PCIe config space */
+	BASEADDR_HOST		= 0x80000000 /* Start of host memory (0x0 of IOMMU) */
+};
+
+/** MSI vector table for VILLASfpga components */
+enum {
+	MSI_DMA_MM2S		= 0, /* Sensivity: level high,  synchronous: axi_clk */
+	MSI_DMA_S2MM		= 1, /* Sensivity: level high,  synchronous: axi_clk */
+	MSI_RTDS_TS		= 2, /* Sensivity: rising edge, synchronous: rtds_clk100m (New timestep started) */
+	MSI_RTDS_OVF		= 3, /* Sensivity: rising edge, synchronous: rtds_clk100m (UserTxInProgress overlapped with UserTStepPulse)*/
+	MSI_RTDS_CASE		= 4  /* Sensivity: rising edge, synchronous: rtds_clk100m (New RSCAD case started) */
+};
+
+/** Mapping of VILLASfpga components to AXI Stream interconnect ports */
+enum {
+	AXIS_SWITCH_RTDS	= 0,
+	AXIS_SWITCH_XSG		= 1,
+	AXIS_SWITCH_DMA_SIMPLE	= 2,
+	AXI_SWITCH_NUM		= 3 /* Number of master and slave interfaces */
+};
+#endif
+
+#define PCI_VID_XILINX		0x10ee
+#define PCI_PID_VFPGA		0x7022
+
+#endif /* _CONFIG_FPGA_H_ */

config.h

@@ -39,7 +39,7 @@
 
 /* Required kernel version */
 #define KERNEL_VERSION_MAJ	3
-#define KERNEL_VERSION_MIN	4
+#define KERNEL_VERSION_MIN	6
 	
 /** Coefficients for simple FIR-LowPass:
  *   F_s = 1kHz, F_pass = 100 Hz, F_block = 300

include/fpga-bench.h

@@ -0,0 +1,21 @@
+/** Benchmarks for VILLASfpga
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#ifndef _BENCH_H_
+#define _BENCH_H_
+
+#include "nodes/vfpga.h"
+
+int bench_memcpy(struct vfpga *f);
+
+int bench_memcpy(struct vfpga *f);
+
+int bench_dm(struct vfpga *f);
+
+#endif /* _BENCH_H_ */

include/fpga-tests.h

@@ -0,0 +1,29 @@
+/** Test procedures for VILLASfpga
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ *********************************************************************************/
+
+#ifndef _TESTS_H_
+#define _TESTS_H_
+
+#include "nodes/vfpga.h"
+
+int test_intc(struct vfpga *f);
+
+int test_xsg(struct vfpga *f, const char *name);
+
+int test_fifo(struct vfpga *f);
+
+int test_dma(struct vfpga *f);
+
+int test_timer(struct vfpga *f);
+
+int test_rtds_rtt(struct vfpga *f);
+
+int test_rtds_cbuilder(struct vfpga *f);
+
+#endif /* _TESTS_H_ */

include/gtfpga.h

@@ -1,79 +0,0 @@
-/** Node type: GTFPGA (Xilinx ML507)
- *
- * This file implements the gtfpga subtype for nodes.
- * It's based on the uio_pci_generic kernel module.
- * A detailed description of that module is available here:
- * http://www.hep.by/gnu/kernel/uio-howto/uio_pci_generic.html
- *
- * @file
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
- * @copyright 2015-2016, Steffen Vogel
- *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
- *   Unauthorized copying of this file, via any medium is strictly prohibited. 
- */
-/**
- * @addtogroup gtfpga RTDS - PCIexpress Fiber interface node type
- * @ingroup node
- * @{
- *********************************************************************************/
-
-#ifndef _GTFPGA_H_
-#define _GTFPGA_H_
-
-#include <pci/pci.h>
-
-#include "node.h"
-
-#define GTFPGA_BAR	0	/**< The Base Address Register which is mmap()ed to the User Space */
-
-#define GTFPGA_MAX_TX	64	/**< The amount of values which is supported by the GTFPGA card */
-#define GTFPGA_MAX_RX	64	/**< The amount of values which is supported by the GTFPGA card */
-
-#define GTFPGA_VID	0x10ee	/**< The default vendor ID of the GTFPGA card */
-#define GTFPGA_DID	0x0007	/**< The default device ID of the GTFPGA card */
-
-struct gtfpga {
-	struct pci_filter filter;
-
-	int fd_irq;		/**< File descriptor for the timer. This is blocking when read(2) until a new IRQ / timer expiration. */
-
-	char *map_bar0;		/**< Memory-mapped address of BAR0 */
-	
-	enum {
-		GTFPGA_MODE_FIFO,
-		GTFPGA_MODE_DMA
-	} mode;
-
-	char *name;
-	double rate;
-
-	struct pci_dev *dev;
-};
-
-typedef void(*log_cb_t)(char *, ...);
-
-/** @see node_vtable::init */
-int gtfpga_init(int argc, char * argv[], config_setting_t *cfg);
-
-/** @see node_vtable::deinit */
-int gtfpga_deinit();
-
-/** @see node_vtable::parse */
-int gtfpga_parse(struct node *n, config_setting_t *cfg);
-
-/** @see node_vtable::print */
-char * gtfpga_print(struct node *n);
-
-/** @see node_vtable::open */
-int gtfpga_open(struct node *n);
-
-/** @see node_vtable::close */
-int gtfpga_close(struct node *n);
-
-/** @see node_vtable::read */
-int gtfpga_read(struct node *n, struct pool *pool, int cnt);
-
-/** @see node_vtable::write */
-int gtfpga_write(struct node *n, struct pool *pool, int cnt);
-
-#endif /** _GTFPGA_H_ @} */

include/villas/fpga/dma.h

@@ -0,0 +1,42 @@
+/** DMA related helper functions
+ *
+ * These functions present a simpler interface to Xilinx' DMA driver (XAxiDma_*)
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of S2SS. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#ifndef _DMA_H_
+#define _DMA_H_
+ 
+#include <stdlib.h>
+#include <stdint.h>
+#include <sys/types.h>
+
+#include <xilinx/xaxidma.h>
+
+#define XAXIDMA_SR_SGINCL_MASK	0x00000008
+
+enum dma_mode {
+	DMA_MODE_SIMPLE,
+	DMA_MODE_SG
+};
+
+struct dma_mem {
+	uint32_t base_virt;
+	uint32_t base_phys;
+	size_t len;
+};
+
+int dma_init(XAxiDma *xdma, char *baseaddr, enum dma_mode mode, struct dma_mem *bd, struct dma_mem *rx, size_t maxlen);
+
+ssize_t dma_write(XAxiDma *xdma, char *buf, size_t len, int irq);
+
+ssize_t dma_read(XAxiDma *xdma, char *buf, size_t len, int irq);
+
+ssize_t dma_ping_pong(XAxiDma *xdma, char *src, char *dst, size_t len, int s2mm_irq);
+
+#endif /* _DMA_H_ */

include/villas/fpga/fifo.h

@@ -0,0 +1,26 @@
+/** FIFO related helper functions
+ *
+ * These functions present a simpler interface to Xilinx' FIFO driver (XLlFifo_*)
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of S2SS. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#ifndef _FIFO_H_
+#define _FIFO_H_
+
+#include <sys/types.h>
+
+#include <xilinx/xstatus.h>
+#include <xilinx/xllfifo.h>
+
+int fifo_init(XLlFifo *fifo, char *baseaddr, char *axi_baseaddr);
+
+ssize_t fifo_write(XLlFifo *fifo, char *buf, size_t len, int irq);
+
+ssize_t fifo_read(XLlFifo *fifo, char *buf, size_t len, int irq);
+
+#endif /* _FIFO_H_ */

include/villas/fpga/model.h

@@ -0,0 +1,100 @@
+/** Interface to Xilinx System Generator Models via PCIe
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ *********************************************************************************/
+ 
+#ifndef _MODEL_H_
+#define _MODEL_H_
+
+#include <stdlib.h>
+#include <inttypes.h>
+
+#include <villas/list.h>
+
+#include "xsg.h"
+
+enum model_type {
+	MODEL_TYPE_HLS,
+	MODEL_TYPE_XSG
+};
+
+struct model {
+	char *name;			/**< Name / Identifier of model */
+	void *baseaddr;			/**< Base of register map. */
+
+	enum model_type type;		/**< Model type. */
+
+	struct list parameters;		/**< List of model parameters. */
+
+	union {
+		struct xsg_model xsg;	/**< XSG specific model data */
+		//struct hls_model hls;	/**< HLS specific model data */
+	};
+};
+
+enum model_param_type {
+	MODEL_PARAM_TYPE_UFIX,
+	MODEL_PARAM_TYPE_FIX,
+	MODEL_PARAM_TYPE_FLOAT,
+	MODEL_PARAM_TYPE_BOOLEAN
+};
+
+enum model_param_direction {
+	MODEL_PARAM_IN,
+	MODEL_PARAM_OUT,
+	MODEL_PARAM_INOUT
+};
+
+union model_param_value {
+	uint32_t ufix;
+	int32_t  fix;
+	float    flt;
+	bool     bol;
+};
+
+struct model_param {
+	char *name;				/**< Name of the parameter */
+
+	enum model_param_direction direction;	/**< Read / Write / Read-write? */
+	enum model_param_type type;		/**< Data type. Integers are represented by MODEL_GW_TYPE_(U)FIX with model_gw::binpt == 0 */
+
+	int binpt;				/**< Binary point for type == MODEL_GW_TYPE_(U)FIX */
+	int offset;				/**< Register offset to model::baseaddress */
+
+	union model_param_value default_value;
+
+	struct model *model;			/**< A pointer to the model structure to which this parameters belongs to. */
+};
+
+int model_init(struct model *m, const char *xml);
+
+void model_destroy(struct model *m);
+
+void model_dump(struct model *m);
+
+void model_param_destroy(struct model_param *r);
+
+void model_param_add(struct model *m, const char *name, enum model_param_direction dir, enum model_param_type type);
+
+char * xsg_get_info(struct xsg_model *x, const char *key);
+
+/** Read a model parameter.
+ *
+ * Note: the data type of the register is taken into account.
+ * All datatypes are converted to double.
+ */
+int model_param_read(struct model_param *p, double *v);
+
+/** Update a model parameter.
+ *
+ * Note: the data type of the register is taken into account.
+ * The double argument will be converted to the respective data type of the
+ * GatewayIn/Out block.
+ */
+int model_param_write(struct model_param *p, double v);
+
+#endif /* _MODEL_H_ */

include/villas/fpga/rtds_axis.h

@@ -0,0 +1,43 @@
+/** Driver for AXI Stream wrapper around RTDS_InterfaceModule (rtds_axis )
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of S2SS. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#ifndef _RTDS_AXIS_H_
+#define _RTDS_AXIS_H_
+
+#define RTDS_HZ				100000000 // 100 MHz
+
+#define RTDS_AXIS_MAX_TX		64	/**< The amount of values which is supported by the vfpga card */
+#define RTDS_AXIS_MAX_RX		64	/**< The amount of values which is supported by the vfpga card */
+
+/* Register offsets */
+#define RTDS_AXIS_SR_OFFSET		0x00	/**< Status Register (read-only). See RTDS_AXIS_SR_* constant. */
+#define RTDS_AXIS_CR_OFFSET		0x04	/**< Control Register (read/write) */
+#define RTDS_AXIS_TSCNT_LOW_OFFSET	0x08	/**< Lower 32 bits of timestep counter (read-only). */
+#define RTDS_AXIS_TSCNT_HIGH_OFFSET	0x0C	/**< Higher 32 bits of timestep counter (read-only). */
+#define RTDS_AXIS_TS_PERIOD_OFFSET	0x10	/**< Period in clock cycles of previous timestep (read-only). */
+#define RTDS_AXIS_COALESC_OFFSET	0x14	/**< IRQ Coalescing register (read/write). */
+#define RTDS_AXIS_VERSION_OFFSET	0x18	/**< 16 bit version field passed back to the rack for version reporting (visible from “status” command, read/write). */
+#define RTDS_AXIS_MRATE_RTDS2AXIS	0x1C	/**< */
+#define RTDS_AXIS_MRATE_AXIS2RTDS	0x20	/**< */
+
+/* Status register bits */
+#define RTDS_AXIS_SR_CARDDETECTED	(1 << 0)/**< ‘1’ when RTDS software has detected and configured card. */
+#define RTDS_AXIS_SR_LINKUP		(1 << 1)/**< ‘1’ when RTDS communication link has been negotiated. */
+#define RTDS_AXIS_SR_TX_FULL		(1 << 2)/**< Tx buffer is full, writes that happen when UserTxFull=’1’ will be dropped (Throttling / buffering is performed by hardware). */
+#define RTDS_AXIS_SR_TX_INPROGRESS	(1 << 3)/**< Indicates when data is being put on link. */
+#define RTDS_AXIS_SR_CASE_RUNNING	(1 << 4)/**< There is currently a simulation running. */
+
+/* Control register bits */
+#define RTDS_AXIS_CR_DISABLE_LINK	0	/**< Disable SFP TX when set */
+
+void rtds_axis_dump(char *baseaddr);
+
+double rtds_axis_dt(char *baseaddr);
+
+#endif /* _RTDS_AXIS_H_ */

include/villas/fpga/switch.h

@@ -0,0 +1,21 @@
+/** AXI Stream interconnect related helper functions
+ *
+ * These functions present a simpler interface to Xilinx' AXI Stream switch driver (XAxis_Switch_*)
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of S2SS. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#ifndef _SWITCH_H_
+#define _SWITCH_H_
+
+#include <xilinx/xaxis_switch.h>
+
+int switch_init(XAxis_Switch *sw, char *baseaddr, int micnt, int sicnt);
+
+int switch_connect(XAxis_Switch *sw, int mi, int si);
+
+#endif /* _SWITCH_H_ */

include/villas/fpga/xsg.h

@@ -0,0 +1,54 @@
+/** Interface to Xilinx System Generator Models via VILLASfpga
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2016, Steffen Vogel
+ *   This file is part of S2SS. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ *********************************************************************************/
+
+#ifndef _XSG_H_
+#define _XSG_H_
+
+#define XSG_MAGIC		0xDEADBABE
+
+/* Forward declaration */
+struct model;
+
+enum xsg_block_type {
+	XSG_BLOCK_GATEWAY_IN	= 0x1000,
+	XSG_BLOCK_GATEWAY_OUT	= 0x1001,
+	XSG_BLOCK_INFO		= 0x2000
+};
+
+struct xsg_model {
+	int version;
+
+	char *map;
+	size_t maplen;
+
+	struct list infos;
+};
+
+struct xsg_info {
+	char *field;
+	char *value;
+};
+
+int xsg_init_from_map(struct model *m);
+
+int xsg_init_from_xml(struct model *m, const char *xml);
+
+void xsg_destroy(struct xsg_model *x);
+
+void xsg_dump(struct xsg_model *x);
+
+void xsg_info_destroy(struct xsg_info *i);
+
+/** Read the XSG model information from ROM */
+int xsg_map_read(void *offset, void *dst, size_t len);
+
+/** Parse binary model information from ROM */
+int xsg_map_parse(uint32_t *map, size_t len, struct list *parameters, struct list *infos);
+
+#endif /* _XSG_H_ */

include/villas/kernel/pci.h

@@ -0,0 +1,21 @@
+/** Linux PCI helpers
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of S2SS. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#ifndef _PCI_H_
+#define _PCI_H_
+
+#include <pci/pci.h>
+
+struct pci_dev * pci_find_device(struct pci_access *pacc, struct pci_filter *f);
+
+int pci_attach_driver(struct pci_dev *d, const char *driver);
+
+int pci_get_iommu_group(struct pci_dev *pdev);
+
+#endif /* _PCI_H_ */

include/villas/kernel/vfio.h

@@ -0,0 +1,104 @@
+/** Virtual Function IO wrapper around kernel API
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ *********************************************************************************/
+
+#ifndef _VFIO_H_
+#define _VFIO_H_
+
+#include <stdbool.h>
+#include <pci/pci.h>
+
+#include <linux/vfio.h>
+#include <linux/pci_regs.h>
+
+#include <villas/list.h>
+
+#define VFIO_DEV(x)	"/dev/vfio/" x
+
+struct vfio_group {
+	int fd;						/**< VFIO group file descriptor */
+	int index;					/**< Index of the IOMMU group as listed under /sys/kernel/iommu_groups/ */
+
+	struct vfio_group_status status;		/**< Status of group */
+
+	struct list devices;
+
+	struct vfio_container *container;		/**< The VFIO container to which this group is belonging */
+};
+
+struct vfio_dev {
+	char *name;				/**< Name of the device as listed under /sys/kernel/iommu_groups/[vfio_group::index]/devices/ */
+	int fd;					/**< VFIO device file descriptor */
+
+	struct vfio_device_info info;
+	struct vfio_irq_info *irqs;
+	struct vfio_region_info *regions;
+	
+	void **mappings;
+	
+	int *msi_efds;				/**< Array of assigned eventfs for MSI handling */
+	int *msi_irqs;				/**< Linux assigned IRQ number for MSI (see /proc/interrupts) */
+
+	struct pci_dev *pdev;			/**< libpci handle of the device */
+	struct vfio_group *group;		/**< The VFIO group this device belongs to */
+};
+
+struct vfio_container {
+	int fd;
+	int version;
+	int extensions;
+
+	struct list groups;
+};
+
+/** Initialize a new VFIO container. */
+int vfio_init(struct vfio_container *c);
+
+/** Initialize a VFIO group and attach it to an existing VFIO container. */
+int vfio_group_attach(struct vfio_group *g, struct vfio_container *c, int index);
+
+/** Initialize a VFIO device, lookup the VFIO group it belongs to, create the group if not already existing. */
+int vfio_dev_attach(struct vfio_dev *d, struct vfio_container *c, const char *name, int index);
+
+/** Initialie a VFIO-PCI device (uses vfio_dev_attach() internally) */
+int vfio_pci_attach(struct vfio_dev *d, struct vfio_container *c, struct pci_dev *pdev);
+
+/** Hot resets a VFIO-PCI device */
+int vfio_pci_reset(struct vfio_dev *d);
+
+/** Create a new eventfd and binds it to the MSI irqs of the device */
+int vfio_pci_msi_fd(struct vfio_dev *d, uint32_t mask);
+
+/** Enable memory accesses and bus mastering for PCI device */
+int vfio_pci_enable(struct vfio_dev *d);
+
+/** Reset a VFIO device */
+int vfio_dev_reset(struct vfio_dev *d);
+
+/** Release memory and close container */
+int vfio_destroy(struct vfio_container *c);
+
+/** Release memory of group */
+void vfio_group_destroy(struct vfio_group *g);
+
+/** Release memory of device */
+void vfio_dev_destroy(struct vfio_dev *g);
+
+/** Print a dump of all attached groups and their devices including regions and IRQs */
+void vfio_dump(struct vfio_container *c);
+
+/** Map a device memory region to the application address space (e.g. PCI BARs) */
+void * vfio_map_region(struct vfio_dev *d, int idx);
+
+/** Allocate a virtual memory region and map it for DMA access from the devices */
+void * vfio_map_dma(struct vfio_container *c, size_t size, size_t pgsize, uint64_t phyaddr);
+
+/** munmap() a region which has been mapped by vfio_map_region() */
+int vfio_unmap_region(struct vfio_dev *d, int idx);
+
+#endif /* _VFIO_H_ */

include/villas/nodes/vfpga.h

@@ -0,0 +1,103 @@
+/** Node type: VILLASfpga
+ *
+ * This file implements the vfpga node-type.
+ *
+ * @file
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited. 
+ */
+/**
+ * @addtogroup vfpga VILLASnode
+ * @ingroup node
+ * @{
+ *********************************************************************************/
+
+#ifndef _VFPGA_H_
+#define _VFPGA_H_
+
+#include <xilinx/xtmrctr.h>
+#include <xilinx/xintc.h>
+#include <xilinx/xllfifo.h>
+#include <xilinx/xaxis_switch.h>
+#include <xilinx/xaxidma.h>
+
+#include "kernel/vfio.h"
+
+#include "fpga/switch.h"
+#include "fpga/model.h"
+#include "fpga/dma.h"
+#include "fpga/fifo.h"
+#include "fpga/rtds_axis.h"
+
+#include <pci/pci.h>
+
+#include "nodes/vfpga.h"
+#include "node.h"
+#include "list.h"
+
+#define VFPGA_BAR		0	/**< The Base Address Register which is mmap()ed to the User Space */
+
+struct vfpga {
+	struct pci_filter filter;
+
+	enum {
+		vfpga_MODE_FIFO,
+		vfpga_MODE_DMA
+	} mode;
+
+	int features;
+
+	struct list models;		/**< List of XSG and HLS model blocks on FPGA. */
+	struct vfio_dev vd;		/**< VFIO device handle. */
+
+	/* Xilinx IP blocks */
+	XTmrCtr tmr;
+	XLlFifo fifo;
+	XAxiDma dma_simple;
+	XAxiDma dma_sg;
+	XAxis_Switch sw;
+
+	char *map;			/**< PCI BAR0 mapping for register access */
+	char *dma;			/**< DMA mapped memory */
+	
+	size_t maplen;
+	size_t dmalen;
+};
+
+/** @see node_vtable::init */
+int vfpga_init(int argc, char * argv[], config_setting_t *cfg);
+
+/** @see node_vtable::deinit */
+int vfpga_deinit();
+
+/** @see node_vtable::parse */
+int vfpga_parse(struct node *n, config_setting_t *cfg);
+
+/** @see node_vtable::print */
+char * vfpga_print(struct node *n);
+
+/** @see node_vtable::open */
+int vfpga_open(struct node *n);
+
+/** @see node_vtable::close */
+int vfpga_close(struct node *n);
+
+/** @see node_vtable::read */
+int vfpga_read(struct node *n, struct sample *smps[], unsigned cnt);
+
+/** @see node_vtable::write */
+int vfpga_write(struct node *n, struct sample *smps[], unsigned cnt);
+
+//////////
+
+int vfpga_init2(struct vfpga *f, struct vfio_container *vc, struct pci_dev *pdev);
+
+int vfpga_deinit2(struct vfpga *f);
+
+int vfpga_reset(struct vfpga *f);
+
+void vfpga_dump(struct vfpga *f);
+
+#endif /** _VFPGA_H_ @} */

lib/fpga/dma.c

@@ -0,0 +1,409 @@
+/** DMA related helper functions
+ *
+ * These functions present a simpler interface to Xilinx' DMA driver (XAxiDma_*)
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASfpga. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#include <sys/types.h>
+#include <unistd.h>
+
+#include <villas/log.h>
+
+#include "utils.h"
+#include "fpga/dma.h"
+
+int dma_write_complete(XAxiDma *xdma, int irq)
+{
+	int processed, ret;
+
+	XAxiDma_Bd *bd;
+	XAxiDma_BdRing *ring = XAxiDma_GetTxRing(xdma);
+
+	/* Wait until the one BD TX transaction is done */
+	while ((processed = XAxiDma_BdRingFromHw(ring, XAXIDMA_ALL_BDS, &bd)) == 0) {
+		if (irq >= 0)
+			wait_irq(irq);
+	}
+
+	/* Free all processed TX BDs for future transmission */
+	ret = XAxiDma_BdRingFree(ring, processed, bd);
+	if (ret != XST_SUCCESS) {
+		info("Failed to free %d tx BDs %d", processed, ret);
+		return -1;
+	}
+	
+	return processed;
+}
+
+int dma_read_complete(XAxiDma *xdma, int irq)
+{
+	return 0;
+}
+
+ssize_t dma_write(XAxiDma *xdma, char *buf, size_t len, int irq)
+{
+	int ret;
+	
+	if (xdma->HasSg) {
+
+		XAxiDma_BdRing *ring;
+		XAxiDma_Bd *bd;
+
+		ring = XAxiDma_GetTxRing(xdma);
+
+		ret = XAxiDma_BdRingAlloc(ring, 1, &bd);
+		if (ret != XST_SUCCESS)
+			return -1;
+
+		/* Set up the BD using the information of the packet to transmit */
+		ret = XAxiDma_BdSetBufAddr(bd, (uintptr_t) buf);
+		if (ret != XST_SUCCESS) {
+			info("Tx set buffer addr %p on BD %p failed %d", buf, bd, ret);
+			return -1;
+		}
+
+		ret = XAxiDma_BdSetLength(bd, len, ring->MaxTransferLen);
+		if (ret != XST_SUCCESS) {
+			info("Tx set length %zu on BD %p failed %d", len, bd, ret);
+			return -1;
+		}
+
+		/* Set SOF / EOF / ID */
+		XAxiDma_BdSetCtrl(bd, XAXIDMA_BD_CTRL_TXEOF_MASK | XAXIDMA_BD_CTRL_TXSOF_MASK);
+		XAxiDma_BdSetId(bd, (uintptr_t) buf);
+
+		/* Give the BD to DMA to kick off the transmission. */
+		ret = XAxiDma_BdRingToHw(ring, 1, bd);
+		if (ret != XST_SUCCESS) {
+			info("to hw failed %d", ret);
+			return -1;
+		}
+		
+		dma_write_complete(xdma, irq);
+	}
+	else {
+		ret = XAxiDma_SimpleTransfer(xdma, (uintptr_t) buf, len, XAXIDMA_DMA_TO_DEVICE);
+		if (ret != XST_SUCCESS) {
+			warn("Failed DMA transfer");
+			return -1;
+		}
+
+		if (irq >= 0) {
+			wait_irq(irq);
+			XAxiDma_IntrAckIrq(xdma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
+		}
+		else {
+			while (XAxiDma_Busy(xdma, XAXIDMA_DMA_TO_DEVICE))
+				__asm__("nop");
+		}
+	}
+
+	return len;
+}
+
+ssize_t dma_read(XAxiDma *xdma, char *buf, size_t len, int irq)
+{
+	int ret;
+	
+	if (xdma->HasSg) {
+		int freecnt, processed;
+
+		XAxiDma_BdRing *ring;
+		XAxiDma_Bd *bd;
+
+		ring = XAxiDma_GetRxRing(xdma);
+
+		processed = 0;
+		do {
+			/* Wait until the data has been received by the Rx channel */
+			while (XAxiDma_BdRingFromHw(ring, 1, &bd) == 0) {
+				if (irq >= 0)
+					wait_irq(irq);
+			}
+			
+			//char *bdbuf = XAxiDma_BdGetBufAddr(bd);
+			//size_t bdlen = XAxiDma_BdGetActualLength(bd, XAXIDMA_MAX_TRANSFER_LEN);
+
+			//memcpy(buf, bdbuf, bdlen);
+			//buf += bdlen;
+
+			processed++;
+		} while (XAxiDma_BdGetSts(bd) & XAXIDMA_BD_STS_RXEOF_MASK);
+
+		/* Free all processed RX BDs for future transmission */
+		ret = XAxiDma_BdRingFree(ring, processed, bd);
+		if (ret != XST_SUCCESS) {
+			info("Failed to free %d rx BDs %d", processed, ret);
+			return XST_FAILURE;
+		}
+
+		/* Return processed BDs to RX channel so we are ready to receive new
+		 * packets:
+		 *    - Allocate all free RX BDs
+		 *    - Pass the BDs to RX channel
+		 */
+		freecnt = XAxiDma_BdRingGetFreeCnt(ring);
+		ret = XAxiDma_BdRingAlloc(ring, freecnt, &bd);
+		if (ret != XST_SUCCESS) {
+			info("bd alloc failed");
+			return -1;
+		}
+
+		ret = XAxiDma_BdRingToHw(ring, freecnt, bd);
+		if (ret != XST_SUCCESS) {
+			info("Submit %d rx BDs failed %d", freecnt, ret);
+			return -1;
+		}
+	}
+	else {
+		ret = XAxiDma_SimpleTransfer(xdma, (uintptr_t) buf, len, XAXIDMA_DEVICE_TO_DMA);
+		if (ret != XST_SUCCESS)
+			warn("Failed DMA transfer");
+
+		if (irq >= 0) {
+			wait_irq(irq);
+			XAxiDma_IntrAckIrq(xdma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
+		}
+		else {
+			while (XAxiDma_Busy(xdma, XAXIDMA_DEVICE_TO_DMA))
+				__asm__("nop");
+		}
+	}
+
+	return len;
+}
+
+ssize_t dma_ping_pong(XAxiDma *xdma, char *src, char *dst, size_t len, int s2mm_irq)
+{
+	int ret;
+
+	/* Prepare S2MM transfer */
+	ret = XAxiDma_SimpleTransfer(xdma, (uintptr_t) dst, len, XAXIDMA_DEVICE_TO_DMA);
+	if (ret != XST_SUCCESS)
+		warn("Failed DMA transfer");
+
+	/* Start MM2S transfer */
+	ret = XAxiDma_SimpleTransfer(xdma, (uintptr_t) src, len, XAXIDMA_DMA_TO_DEVICE);
+	if (ret != XST_SUCCESS) {
+		warn("Failed DMA transfer");
+		return -1;
+	}
+
+	/* Wait for completion */
+	if (s2mm_irq >= 0) {
+		wait_irq(s2mm_irq);
+		XAxiDma_IntrAckIrq(xdma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
+	}
+	else {
+		while (XAxiDma_Busy(xdma, XAXIDMA_DEVICE_TO_DMA))
+			__asm__("nop");
+	}
+	
+	return XAxiDma_ReadReg(xdma->RegBase + XAXIDMA_RX_OFFSET, XAXIDMA_BUFFLEN_OFFSET);
+}
+
+static int dma_setup_bdring(XAxiDma_BdRing *ring, struct dma_mem *bdbuf)
+{
+	int delay = 0;
+	int coalesce = 1;
+	int ret, cnt;
+
+	XAxiDma_Bd clearbd;
+
+	/* Disable all RX interrupts before RxBD space setup */
+	XAxiDma_BdRingIntDisable(ring, XAXIDMA_IRQ_ALL_MASK);
+
+	/* Set delay and coalescing */
+	XAxiDma_BdRingSetCoalesce(ring, coalesce, delay);
+
+	/* Setup Rx BD space */
+	cnt = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT, bdbuf->len);
+	ret = XAxiDma_BdRingCreate(ring, bdbuf->base_phys, bdbuf->base_virt, XAXIDMA_BD_MINIMUM_ALIGNMENT, cnt);
+
+	if (ret != XST_SUCCESS) {
+		info("RX create BD ring failed %d", ret);
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Setup an all-zero BD as the template for the Rx channel.
+	 */
+	XAxiDma_BdClear(&clearbd);
+	ret = XAxiDma_BdRingClone(ring, &clearbd);
+	if (ret != XST_SUCCESS) {
+		info("RX clone BD failed %d", ret);
+		return XST_FAILURE;
+	}
+	
+	return XST_SUCCESS;
+}
+
+static int dma_setup_rx(XAxiDma *AxiDmaInstPtr, struct dma_mem *bdbuf, struct dma_mem *rxbuf, size_t maxlen)
+{
+	int ret;
+	
+	XAxiDma_BdRing *ring;
+	XAxiDma_Bd *bd, *curbd;
+
+	uint32_t freecnt;
+	uintptr_t rxptr;
+
+	ring = XAxiDma_GetRxRing(AxiDmaInstPtr);
+	ret = dma_setup_bdring(ring, bdbuf);
+	if (ret != XST_SUCCESS)
+		return -1;
+
+	/* Attach buffers to RxBD ring so we are ready to receive packets */
+	freecnt = XAxiDma_BdRingGetFreeCnt(ring);
+	ret = XAxiDma_BdRingAlloc(ring, freecnt, &bd);
+	if (ret != XST_SUCCESS) {
+		info("RX alloc BD failed %d", ret);
+		return XST_FAILURE;
+	}
+
+	curbd = bd;
+	rxptr = rxbuf->base_phys;
+	for (int i = 0; i < freecnt; i++) {
+		ret = XAxiDma_BdSetBufAddr(curbd, rxptr);
+
+		if (ret != XST_SUCCESS) {
+			info("Set buffer addr %#lx on BD %p failed %d", rxptr, curbd, ret);
+			return XST_FAILURE;
+		}
+
+		ret = XAxiDma_BdSetLength(curbd, maxlen, ring->MaxTransferLen);
+		if (ret != XST_SUCCESS) {
+			info("Rx set length %zu on BD %p failed %d", maxlen, curbd, ret);
+			return XST_FAILURE;
+		}
+
+		/* Receive BDs do not need to set anything for the control
+		 * The hardware will set the SOF/EOF bits per stream ret */
+		XAxiDma_BdSetCtrl(curbd, 0);
+		XAxiDma_BdSetId(curbd, rxptr);
+
+		rxptr += maxlen;
+		curbd = (XAxiDma_Bd *) XAxiDma_BdRingNext(ring, curbd);
+	}
+
+	/* Clear the receive buffer, so we can verify data */
+	memset((void *) (uintptr_t) rxbuf->base_virt, 0, rxbuf->len);
+
+	ret = XAxiDma_BdRingToHw(ring, freecnt, bd);
+	if (ret != XST_SUCCESS) {
+		info("RX submit hw failed %d", ret);
+		return XST_FAILURE;
+	}
+
+	/* Start RX DMA channel */
+	ret = XAxiDma_BdRingStart(ring);
+	if (ret != XST_SUCCESS) {
+		info("RX start hw failed %d", ret);
+
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+static int dma_setup_tx(XAxiDma *AxiDmaInstPtr, struct dma_mem *bd)
+{
+	int ret;
+
+	XAxiDma_BdRing *ring;
+
+	ring = XAxiDma_GetTxRing(AxiDmaInstPtr);
+	ret = dma_setup_bdring(ring, bd);
+	if (ret != XST_SUCCESS)
+		return -1;
+
+	/* Start the TX channel */
+	ret = XAxiDma_BdRingStart(ring);
+	if (ret != XST_SUCCESS) {
+		info("failed start bdring txsetup %d", ret);
+		return XST_FAILURE;
+	}
+	
+
+	return XST_SUCCESS;
+}
+
+int dma_init(XAxiDma *xdma, char *baseaddr, enum dma_mode mode, struct dma_mem *bd, struct dma_mem *rx, size_t maxlen)
+{
+	int ret, sgincld;
+
+	XAxiDma_Config xdma_cfg = {
+		.BaseAddr = (uintptr_t) baseaddr,
+		.HasStsCntrlStrm = 0,
+		.HasMm2S = 1,
+		.HasMm2SDRE = 0,
+		.Mm2SDataWidth = 32,
+		.HasS2Mm = 1,
+		.HasS2MmDRE = 0, /* Data Realignment Engine */
+		.S2MmDataWidth = 32,
+		.HasSg = (mode == DMA_MODE_SG) ? 1 : 0,
+		.Mm2sNumChannels = 1,
+		.S2MmNumChannels = 1,
+		.Mm2SBurstSize = 64,
+		.S2MmBurstSize = 64,
+		.MicroDmaMode = 0,
+		.AddrWidth = 32
+	};
+	
+	ret = XAxiDma_CfgInitialize(xdma, &xdma_cfg);
+	if (ret != XST_SUCCESS) {
+		info("Initialization failed %d", ret);
+		return -1;
+	}
+
+	/* Check if correct DMA type */
+	sgincld = XAxiDma_In32((uintptr_t) baseaddr + XAXIDMA_TX_OFFSET+ XAXIDMA_SR_OFFSET) &
+		  XAxiDma_In32((uintptr_t) baseaddr + XAXIDMA_RX_OFFSET+ XAXIDMA_SR_OFFSET) &
+		  XAXIDMA_SR_SGINCL_MASK;
+
+	if ((mode == DMA_MODE_SIMPLE && sgincld == XAXIDMA_SR_SGINCL_MASK) ||
+	    (mode == DMA_MODE_SG     && sgincld != XAXIDMA_SR_SGINCL_MASK)) {
+		info("This is not a %s DMA controller", (mode == DMA_MODE_SG) ? "SG" : "Simple");
+		return -1;
+	}
+
+	/* Perform selftest */
+	ret = XAxiDma_Selftest(xdma);
+	if (ret != XST_SUCCESS) {
+		info("DMA selftest failed");
+		return -1;
+	}
+
+	/* Setup Buffer Descriptor rings for SG DMA */
+	if (mode == DMA_MODE_SG) {
+		/* Split BD memory equally between Rx and Tx rings */
+		struct dma_mem bd_rx = {
+			.base_virt = bd->base_virt,
+			.base_phys = bd->base_phys,
+			.len = bd->len / 2
+		};
+		struct dma_mem bd_tx = {
+			.base_virt = bd->base_virt + bd_rx.len,
+			.base_phys = bd->base_phys + bd_rx.len,
+			.len = bd->len - bd_rx.len
+		};
+
+		ret = dma_setup_rx(xdma, &bd_rx, rx, maxlen);
+		if (ret != XST_SUCCESS)
+			return -1;
+
+		ret = dma_setup_tx(xdma, &bd_tx);
+		if (ret != XST_SUCCESS)
+			return -1;
+	}
+
+	/* Enable completion interrupts for both channels */
+	XAxiDma_IntrEnable(xdma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
+	XAxiDma_IntrEnable(xdma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
+
+	return 0;
+}

lib/fpga/fifo.c

@@ -0,0 +1,65 @@
+/** FIFO related helper functions
+ *
+ * These functions present a simpler interface to Xilinx' FIFO driver (XLlFifo_*)
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASfpga. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#include <unistd.h>
+
+#include <villas/utils.h>
+
+#include "utils.h"
+#include "fpga/fifo.h"
+
+int fifo_init(XLlFifo *fifo, char *baseaddr, char *axi_baseaddr)
+{
+	int ret;
+
+	XLlFifo_Config fifo_cfg = {
+		.BaseAddress = (uintptr_t) baseaddr,
+		.Axi4BaseAddress = (uintptr_t) axi_baseaddr,
+		.Datainterface = (axi_baseaddr == NULL) ? 0 : 1 /* use AXI4 for Data, AXI4-Lite for control */
+	};
+	
+	ret = XLlFifo_CfgInitialize(fifo, &fifo_cfg, (uintptr_t) baseaddr);
+	if (ret != XST_SUCCESS)
+		return -1;
+
+	XLlFifo_IntEnable(fifo, XLLF_INT_RC_MASK);
+
+	return 0;
+}
+
+ssize_t fifo_write(XLlFifo *fifo, char *buf, size_t len, int irq)
+{
+	XLlFifo_Write(fifo, buf, len);
+	XLlFifo_TxSetLen(fifo, len);
+
+	return len;
+}
+
+ssize_t fifo_read(XLlFifo *fifo, char *buf, size_t len, int irq)
+{
+	size_t nextlen = 0;
+
+	while (XLlFifo_RxOccupancy(fifo) == 0) {
+		if (irq >= 0)
+			wait_irq(irq);
+		else
+			__asm__("nop");
+	}
+
+	/* Get length of next frame */
+	nextlen = MIN(XLlFifo_RxGetLen(fifo), len);
+
+	/* Read from FIFO */
+	XLlFifo_Read(fifo, buf, nextlen);
+	
+	XLlFifo_IntClear(fifo, XLLF_INT_RC_MASK);
+
+	return nextlen;
+}

lib/fpga/model.c

@@ -0,0 +1,136 @@
+/** Interface to Xilinx System Generator Models via PCIe
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ *********************************************************************************/
+
+#include <stdint.h>
+#include <time.h>
+#include <string.h>
+#include <math.h>
+
+#include <villas/utils.h>
+#include <villas/log.h>
+
+#include "fpga/model.h"
+#include "fpga/xsg.h"
+
+int model_init(struct model *m, const char *xml)
+{
+	/** @todo: parse XML model descriptions */
+
+	list_init(&m->parameters);
+
+	return 0;
+}
+
+void model_destroy(struct model *m)
+{
+	list_destroy(&m->parameters, (dtor_cb_t) model_param_destroy, true);
+}
+
+void model_dump(struct model *m)
+{
+	const char *param_type[] = { "UFix", "Fix", "Float", "Boolean" };
+	const char *model_types[] = { "HLS", "XSG" };
+	const char *parameter_dirs[] = { "In", "Out", "In/Out" };
+
+	info("Model: %s (baseaddr=%p, type=%s)", m->name, m->baseaddr, model_types[m->type]);
+	
+	{ INDENT
+		info("Parameters:");
+		list_foreach(struct model_param *p, &m->parameters) { INDENT
+			if (p->direction == MODEL_PARAM_IN)
+				info("%#x: %s (%s) = %.3f %s %u",
+					p->offset,
+					p->name,
+					parameter_dirs[p->direction],
+					p->default_value.flt,
+					param_type[p->type],
+					p->binpt
+				);
+			else if (p->direction == MODEL_PARAM_OUT)
+				info("%#x: %s (%s)",
+					p->offset,
+					p->name,
+					parameter_dirs[p->direction]
+				);
+		}
+
+		switch (m->type) {
+			case MODEL_TYPE_HLS:
+				//hls_dump(&m->hls);
+				break;
+			case MODEL_TYPE_XSG:
+				xsg_dump(&m->xsg);
+				break;
+		}
+	}
+}
+
+int model_param_read(struct model_param *p, double *v)
+{
+	union model_param_value *ptr = p->offset + p->model->baseaddr;
+
+	switch (p->type) {
+		case MODEL_PARAM_TYPE_UFIX:
+			*v = (double) ptr->ufix / (1 << p->binpt);
+			break;
+
+		case MODEL_PARAM_TYPE_FIX:
+			*v = (double) ptr->fix / (1 << p->binpt);
+			break;
+
+		case MODEL_PARAM_TYPE_FLOAT:
+			*v = (double) ptr->flt;
+			break;
+			
+		case MODEL_PARAM_TYPE_BOOLEAN:
+			*v = (double) ptr->ufix ? 1 : 0;
+	}
+
+	return 0;
+}
+
+int model_param_write(struct model_param *p, double v)
+{
+	union model_param_value *ptr = p->offset + p->model->baseaddr;
+
+	switch (p->type) {
+		case MODEL_PARAM_TYPE_UFIX:
+			ptr->ufix = (uint32_t) (v * (1 << p->binpt));
+			break;
+
+		case MODEL_PARAM_TYPE_FIX:
+			ptr->fix = (int32_t) (v * (1 << p->binpt));
+			break;
+
+		case MODEL_PARAM_TYPE_FLOAT:
+			ptr->flt = (float) v;
+			break;
+			
+		case MODEL_PARAM_TYPE_BOOLEAN:
+			ptr->bol = (bool) v;
+			break;
+	}
+
+	return 0;
+}
+
+void model_param_add(struct model *m, const char *name, enum model_param_direction dir, enum model_param_type type)
+{
+	struct model_param *p = alloc(sizeof(struct model_param));
+	
+	p->name = strdup(name);
+	p->type = type;
+	p->direction = dir;
+	
+	list_push(&m->parameters, p);
+}
+
+void model_param_destroy(struct model_param *p)
+{
+	free(p->name);
+}

lib/fpga/rtds_axis.c

@@ -0,0 +1,49 @@
+/** Driver for AXI Stream wrapper around RTDS_InterfaceModule (rtds_axis )
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of S2SS. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#include <stdint.h>
+
+#include "log.h"
+#include "utils.h"
+
+#include "fpga/rtds_axis.h"
+
+void rtds_axis_dump(char *baseaddr)
+{
+	/* Check RTDS_Axis registers */
+	uint32_t *rtds = (uint32_t *) baseaddr;
+
+	uint32_t sr = rtds[RTDS_AXIS_SR_OFFSET/4];
+	info("RTDS AXI Stream interface details");
+	{ INDENT
+		info("RTDS status:  %#08x", sr);
+		{ INDENT
+			info("Card detected:  %s", sr & RTDS_AXIS_SR_CARDDETECTED ? GRN("yes") : RED("no"));
+			info("Link up:        %s", sr & RTDS_AXIS_SR_LINKUP ? GRN("yes") : RED("no"));
+			info("TX queue full:  %s", sr & RTDS_AXIS_SR_TX_FULL ? RED("yes") : GRN("no"));
+			info("TX in progress: %s", sr & RTDS_AXIS_SR_TX_INPROGRESS ? YEL("yes") : "no");
+			info("Case running:   %s", sr & RTDS_AXIS_SR_CASE_RUNNING ? GRN("yes") : RED("no"));
+		}
+
+		info("RTDS control: %#08x", rtds[RTDS_AXIS_CR_OFFSET/4]);
+		info("RTDS IRQ coalesc: %u", rtds[RTDS_AXIS_COALESC_OFFSET/4]);
+		info("RTDS IRQ version: %#06x", rtds[RTDS_AXIS_VERSION_OFFSET/4]);
+		info("RTDS IRQ multi-rate RTDS2AXIS: %u", rtds[RTDS_AXIS_MRATE_RTDS2AXIS/4]);
+		info("RTDS IRQ multi-rate AXIS2RTDS: %u", rtds[RTDS_AXIS_MRATE_AXIS2RTDS/4]);
+
+		info("RTDS timestep counter: %lu", (uint64_t) rtds[RTDS_AXIS_TSCNT_LOW_OFFSET/4] | (uint64_t) rtds[RTDS_AXIS_TSCNT_HIGH_OFFSET/4] << 32);
+		info("RTDS timestep period:  %.3f uS", rtds_axis_dt(baseaddr) * 1e6);
+	}
+}
+
+double rtds_axis_dt(char *baseaddr)
+{
+	uint32_t *rtds = (uint32_t *) baseaddr;
+
+	return (double) rtds[RTDS_AXIS_TS_PERIOD_OFFSET/4] / RTDS_HZ;
+}

lib/fpga/switch.c

@@ -0,0 +1,49 @@
+/** AXI Stream interconnect related helper functions
+ *
+ * These functions present a simpler interface to Xilinx' AXI Stream switch driver (XAxis_Switch_*)
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of S2SS. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#include "fpga/switch.h"
+
+int switch_init(XAxis_Switch *sw, char *baseaddr, int micnt, int sicnt)
+{
+	int ret;
+
+	/* Setup AXI-stream switch */
+	XAxis_Switch_Config sw_cfg = {
+		.BaseAddress = (uintptr_t) baseaddr,
+		.MaxNumMI = micnt,
+		.MaxNumSI = sicnt
+	};
+	
+	ret = XAxisScr_CfgInitialize(sw, &sw_cfg, (uintptr_t) baseaddr);
+	if (ret != XST_SUCCESS)
+		return -1;
+
+#if 0
+	ret = XAxisScr_SelfTest(sw);
+	if (ret != TRUE)
+		return -1;
+#endif
+
+	/* Disable all masters */
+	XAxisScr_RegUpdateDisable(sw);
+	XAxisScr_MiPortDisableAll(sw);
+	XAxisScr_RegUpdateEnable(sw);
+
+	return 0;
+}
+
+int switch_connect(XAxis_Switch *sw, int mi, int si)
+{
+	XAxisScr_RegUpdateDisable(sw);
+	XAxisScr_MiPortEnable(sw, mi, si);
+	XAxisScr_RegUpdateEnable(sw);
+
+	return 0;
+}

lib/fpga/xsg.c

@@ -0,0 +1,176 @@
+/** Interface to Xilinx System Generator Models via VILLASfpga
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ *********************************************************************************/
+
+#include <stdint.h>
+#include <string.h>
+#include <math.h>
+#include <sys/types.h>
+
+#include <villas/list.h>
+#include <villas/utils.h>
+#include <villas/log.h>
+
+#include "fpga/model.h"
+#include "fpga/xsg.h"
+#include "utils.h"
+
+int xsg_init_from_map(struct model *m)
+{
+	int ret;
+	struct xsg_model *x = &m->xsg;
+
+	list_init(&x->infos);
+
+	x->map = alloc(1024);
+
+	x->maplen = xsg_map_read(m->baseaddr, x->map, 1024 / 4);
+	if (x->maplen < 0)
+		return -1;
+
+	debug(5, "XSG: memory map length = %#zx", x->maplen);
+
+	ret = xsg_map_parse((uint32_t *) x->map, x->maplen, &m->parameters, &x->infos);
+	if (ret)
+		return -2;
+
+	m->name = xsg_get_info(x, "Name");
+
+	return 0;
+}
+
+int xsg_init_from_xml(struct model *m, const char *xml)
+{
+	/** @todo: parse Simulink .mdl file here (XML based) */
+
+	return -1;
+}
+
+void xsg_destroy(struct xsg_model *x)
+{
+	list_destroy(&x->infos, (dtor_cb_t) xsg_info_destroy, true);
+
+	free(x->map);
+}
+
+char * xsg_get_info(struct xsg_model *x, const char *key)
+{
+	struct xsg_info *info = list_lookup(&x->infos, key);
+
+	return info ? info->value : NULL;
+}
+
+void xsg_info_destroy(struct xsg_info *i)
+{
+	free(i->field);
+	free(i->value);
+}
+
+void xsg_dump(struct xsg_model *x)
+{
+	info("XSG Infos:");
+	list_foreach(struct xsg_info *i, &x->infos) { INDENT
+		info("%s: %s", i->field, i->value);
+	}
+}
+
+static uint32_t xsg_map_checksum(uint32_t *map, size_t len)
+{
+	uint32_t chks = 0;
+	for (int i = 2; i < len-1; i++)
+		chks += map[i];
+
+	return chks; /* moduluo 2^32 because of overflow */
+}
+
+int xsg_map_parse(uint32_t *map, size_t len, struct list *parameters, struct list *infos)
+{
+#define copy_string(off) strndup((char *) (data + (off)), (length - (off)) * 4);
+
+	struct model_param *p;
+	struct xsg_info *info;
+	
+	int i;
+	
+	if (map[0] != XSG_MAGIC)
+		error("Invalid magic: %#x", map[0]);
+
+	for (i = 2; i < len-1;) {
+		uint16_t type   = map[i] & 0xFFFF;
+		uint16_t length = map[i] >> 16;
+		uint32_t *data  = &map[i+1];
+		
+		switch (type) {
+			case XSG_BLOCK_GATEWAY_IN:
+			case XSG_BLOCK_GATEWAY_OUT:
+				if (length < 4)
+					break; /* block is to small to describe a gateway */
+			
+				p = alloc(sizeof(*p));
+
+				p->name          =  copy_string(3);
+				p->default_value.flt =  *((float *) &data[1]);
+				p->offset        = data[2];
+				p->direction     = type & 0x1;
+				p->type          = (data[0] >> 0) & 0xFF;
+				p->binpt         = (data[0] >> 8) & 0xFF;
+
+				list_push(parameters, p);
+				break;
+
+			case XSG_BLOCK_INFO:
+				info = alloc(sizeof(*info));
+
+				info->field = copy_string(0);
+				info->value = copy_string((int) ceil((double) (strlen(info->field) + 1) / 4))
+				
+				list_push(infos, info);
+				break;
+
+			default:
+				warn("Unknown block type: %#06x", type);
+		}
+		
+		i += length + 1;
+	}
+	
+	if (xsg_map_checksum(map, len) != map[i])
+		error("XSG: Invalid checksum");
+
+	return 0;
+
+#undef copy_string
+}
+
+int xsg_map_read(void *baseaddr, void *dst, size_t len)
+{
+#define get_word(a) ({ *addr = a; *data; })
+
+	volatile uint32_t *addr = baseaddr + 0x00;
+	volatile uint32_t *data = baseaddr + 0x04;
+
+	uint32_t *map = dst;
+	uint32_t  maplen, magic;
+
+	/* Check start DW */
+	magic = get_word(0);
+	if (magic != XSG_MAGIC)
+		return -1;
+
+	maplen = get_word(1);
+	if (maplen < 3)
+		return -2;
+
+	/* Read Data */
+	int i;
+	for (i = 0; i < MIN(maplen, len); i++)
+		map[i] = get_word(i);
+
+	return i;
+
+#undef get_word
+}

lib/gtfpga.c

@@ -1,192 +0,0 @@
-/** Node type: GTFPGA (Xilinx ML507)
- *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
- * @copyright 2015-2016, Steffen Vogel
- *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
- *   Unauthorized copying of this file, via any medium is strictly prohibited.
- *********************************************************************************/
-
-#include <stdio.h>
-#include <inttypes.h>
-#include <fcntl.h>
-#include <unistd.h>
-#include <sys/mman.h>
-
-#include "gtfpga.h"
-#include "config.h"
-#include "utils.h"
-#include "timing.h"
-#include "utils.h"
-#include "kernel.h"
-
-static struct pci_access *pacc;
-
-static void gtfpga_debug(char *msg, ...) {
-	va_list ap;
-
-	va_start(ap, msg);
-	log_vprint(LOG_LVL_DEBUG, msg, ap);
-	va_end(ap);
-}
-
-int gtfpga_init(int argc, char * argv[], config_setting_t *cfg)
-{
-	if (getuid() != 0)
-		error("The gtfpga node-type requires superuser privileges!");
-
-	pacc = pci_alloc();		/* Get the pci_access structure */
-	if (!pacc)
-		error("Failed to allocate PCI access structure");
-
-	pci_init(pacc);			/* Initialize the PCI library */
-
-	pacc->error = (log_cb_t) error;	/* Replace logging and debug functions */
-	pacc->warning = (log_cb_t) warn;
-	pacc->debug = gtfpga_debug;
-
-	pci_scan_bus(pacc);		/* We want to get the list of devices */
-
-	return 0;
-}
-
-int gtfpga_deinit()
-{
-	pci_cleanup(pacc);
-
-	return 0;
-}
-
-int gtfpga_parse(struct node *n, config_setting_t *cfg)
-{
-	struct gtfpga *g = n->_vd;
-
-	const char *slot, *id, *err;
-	config_setting_t *cfg_slot, *cfg_id;
-
-	pci_filter_init(NULL, &g->filter);
-
-	cfg_slot = config_setting_get_member(cfg, "slot");
-	if (cfg_slot) {
-		slot = config_setting_get_string(cfg_slot);
-		if (slot) {
-			err = pci_filter_parse_slot(&g->filter, (char*) slot);
-			if (err)
-				cerror(cfg_slot, "%s", err);
-		}
-		else
-			cerror(cfg_slot, "Invalid slot format");
-	}
-
-	cfg_id = config_setting_get_member(cfg, "id");
-	if (cfg_id) {
-		id = config_setting_get_string(cfg_id);
-		if (id) {
-			err = pci_filter_parse_id(&g->filter, (char*) id);
-			if (err)
-				cerror(cfg_id, "%s", err);
-		}
-		else
-			cerror(cfg_slot, "Invalid id format");
-	}
-
-	if (!config_setting_lookup_float(cfg, "rate", &g->rate))
-		g->rate = 0;
-
-	return 0;
-}
-
-char * gtfpga_print(struct node *n)
-{
-	struct gtfpga *g = n->_vd;
-
-	if (g->dev) {
-		return strf("rate=%.1f slot=%04"PRIx16":%02"PRIx8":%02"PRIx8".%"PRIx8
-			" id=%04"PRIx16":%04"PRIx16" class=%04"PRIx16" irq=%d (%s)", g->rate,
-			g->dev->domain, g->dev->bus, g->dev->dev, g->dev->func, g->dev->vendor_id, g->dev->device_id,
-			g->dev->device_class, g->dev->irq, g->name);
-	}
-	else {
-		return strf("rate=%.1f slot=%02"PRIx8":%02"PRIx8".%"PRIx8" id=%04"PRIx16":%04"PRIx16, g->rate,
-			g->filter.bus, g->filter.device, g->filter.func,
-			g->filter.vendor, g->filter.device);
-	}
-}
-
-static struct pci_dev * gtfpga_find_device(struct pci_filter *f)
-{
-	struct pci_dev *d;
-
-	/* Iterate over all devices */
-	for (d = pacc->devices; d; d = d->next) {
-		if (pci_filter_match(f, d))
-			return d;
-	}
-
-	return NULL;
-}
-
-int gtfpga_open(struct node *n)
-{
-	struct gtfpga *g = n->_vd;
-	struct pci_dev *dev;
-
-	dev = gtfpga_find_device(&g->filter);
-	if (!dev)
-		error("No GTFPGA card found");
-
-	g->dev = dev;
-
-	/* @todo VFIO */
-
-	return 0;
-}
-
-int gtfpga_close(struct node *n)
-{
-	struct gtfpga *g = n->_vd;
-
-	/* @todo VFIO */
-
-	return 0;
-}
-
-int gtfpga_read(struct node *n, struct pool *pool, int cnt)
-{
-	struct gtfpga *g = n->_vd;
-
-	/* Wait for IRQ */
-	uint64_t fired;
-	read(g->fd_irq, &fired, sizeof(fired));
-
-	/* Copy memory mapped data */
-	/** @todo */
-
-	return 0;
-}
-
-/** @todo implement */
-int gtfpga_write(struct node *n, struct pool *pool, int cnt)
-{
-	struct gtfpga *g = n->_vd;
-
-	/* Copy memory mapped data */
-	/** @todo */
-
-	return 0;
-}
-
-static struct node_type vt = {
-	.name		= "gtfpga",
-	.description	= "GTFPGA PCIe card (libpci)",
-	.vectorize	= 0,
-	.parse		= gtfpga_parse,
-	.print		= gtfpga_print,
-	.open		= gtfpga_open,
-	.close		= gtfpga_close,
-	.read		= gtfpga_read,
-	.write		= gtfpga_write,
-	.init		= gtfpga_init,
-	.deinit		= gtfpga_deinit
-};
-
-REGISTER_NODE_TYPE(&vt)

lib/kernel/pci.c

@@ -0,0 +1,75 @@
+/** Linux PCI helpers
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <libgen.h> 
+#include <unistd.h>
+
+#include "log.h"
+
+#include "kernel/pci.h"
+#include "config.h"
+
+struct pci_dev * pci_find_device(struct pci_access *pacc, struct pci_filter *f)
+{
+	struct pci_dev *d;
+
+	/* Iterate over all devices */
+	for (d = pacc->devices; d; d = d->next) {
+		if (pci_filter_match(f, d))
+			return d;
+	}
+
+	return NULL;
+}
+
+int pci_attach_driver(struct pci_dev *d, const char *driver)
+{
+	FILE *f;
+	char fn[256];
+
+	/* Add new ID to driver */
+	snprintf(fn, sizeof(fn), "%s/bus/pci/drivers/%s/new_id", SYSFS_PATH, driver);
+	f = fopen(fn, "w");
+	if (!f)
+		serror("Failed to add PCI id to %s driver (%s)", driver, fn);
+
+	debug(5, "Adding ID to %s module: %04x %04x", driver, d->vendor_id, d->device_id);
+	fprintf(f, "%04x %04x", d->vendor_id, d->device_id);
+	fclose(f);
+
+	/* Bind to driver */
+	snprintf(fn, sizeof(fn), "%s/bus/pci/drivers/%s/bind", SYSFS_PATH, driver);
+	f = fopen(fn, "w");
+	if (!f)
+		serror("Failed to bind PCI device to %s driver (%s)", driver, fn);
+
+	debug(5, "Bind device to %s driver", driver);
+	fprintf(f, "%04x:%02x:%02x.%x\n", d->domain, d->bus, d->dev, d->func);
+	fclose(f);
+
+	return 0;
+}
+
+int pci_get_iommu_group(struct pci_dev *pdev)
+{
+	int ret;
+	char *group, link[1024], sysfs[1024];
+
+	snprintf(sysfs, sizeof(sysfs), "%s/bus/pci/devices/%04x:%02x:%02x.%x/iommu_group", SYSFS_PATH,
+		pdev->domain, pdev->bus, pdev->dev, pdev->func);
+
+	ret = readlink(sysfs, link, sizeof(link));
+	if (ret < 0)
+		return -1;
+
+	group = basename(link);
+
+	return atoi(group);
+}

lib/kernel/vfio.c

@@ -0,0 +1,625 @@
+/** Virtual Function IO wrapper around kernel API
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#define _DEFAULT_SOURCE
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <string.h>
+
+#include <sys/ioctl.h>
+#include <sys/mman.h>
+#include <sys/eventfd.h>
+
+
+#include "utils.h"
+#include "log.h"
+
+#include "config.h"
+
+#include "kernel/kernel.h"
+#include "kernel/vfio.h"
+#include "kernel/pci.h"
+
+static const char *vfio_pci_region_names[] = {
+	"PCI_BAR0",		// VFIO_PCI_BAR0_REGION_INDEX,
+	"PCI_BAR1",		// VFIO_PCI_BAR1_REGION_INDEX,
+	"PCI_BAR2",		// VFIO_PCI_BAR2_REGION_INDEX,
+	"PCI_BAR3",		// VFIO_PCI_BAR3_REGION_INDEX,
+	"PCI_BAR4",		// VFIO_PCI_BAR4_REGION_INDEX,
+	"PCI_BAR5",		// VFIO_PCI_BAR5_REGION_INDEX,
+	"PCI_ROM",		// VFIO_PCI_ROM_REGION_INDEX,
+	"PCI_CONFIG",		// VFIO_PCI_CONFIG_REGION_INDEX,
+	"PCI_VGA"		//  VFIO_PCI_INTX_IRQ_INDEX,
+};
+
+static const char *vfio_pci_irq_names[] = {
+	"PCI_INTX",		// VFIO_PCI_INTX_IRQ_INDEX,
+	"PCI_MSI", 		// VFIO_PCI_MSI_IRQ_INDEX,
+	"PCI_MSIX",		// VFIO_PCI_MSIX_IRQ_INDEX,
+	"PCI_ERR", 		// VFIO_PCI_ERR_IRQ_INDEX,
+	"PCI_REQ"		// VFIO_PCI_REQ_IRQ_INDEX,
+};
+
+/* Helpers */
+int vfio_get_iommu_name(int index, char *buf, size_t len)
+{
+	FILE *f;
+	char fn[256];
+
+	snprintf(fn, sizeof(fn), "/sys/kernel/iommu_groups/%d/name", index);
+
+	f = fopen(fn, "r");
+	if (!f)
+		return -1;
+
+	int ret = fgets(buf, len, f) == buf ? 0 : -1;
+	
+	/* Remove trailing newline */
+	char *c = strrchr(buf, '\n');
+	if (c)
+		*c = 0;
+
+	fclose(f);
+
+	return ret;
+}
+
+/* Destructors */
+int vfio_destroy(struct vfio_container *v)
+{
+	int ret;
+
+	/* Release memory and close fds */
+	list_destroy(&v->groups, (dtor_cb_t) vfio_group_destroy, true);
+
+	/* Close container */
+	ret = close(v->fd);
+	if (ret < 0)
+		return -1;
+
+	debug(5, "VFIO: closed container: fd=%d", v->fd);
+
+	return 0;
+}
+
+void vfio_group_destroy(struct vfio_group *g)
+{
+	int ret;
+
+	list_destroy(&g->devices, (dtor_cb_t) vfio_dev_destroy, false);
+	
+	ret = ioctl(g->fd, VFIO_GROUP_UNSET_CONTAINER);
+	if (ret)
+		return;
+
+	debug(5, "VFIO: released group from container: group=%u", g->index);
+
+	ret = close(g->fd);
+	if (ret)
+		return;
+
+	debug(5, "VFIO: closed group: group=%u, fd=%d", g->index, g->fd);
+}
+
+void vfio_dev_destroy(struct vfio_dev *d)
+{
+	int ret;
+
+	for (int i = 0; i < d->info.num_regions; i++)
+		vfio_unmap_region(d, i);
+
+	/* Check if this is really a vfio-pci device */
+	if (d->info.flags & VFIO_DEVICE_FLAGS_PCI) {
+		for (int i = 0; i < d->irqs[VFIO_PCI_MSI_IRQ_INDEX].count; i++)
+			close(d->msi_efds[i]);
+
+		free(d->msi_efds);
+	}
+
+	ret = close(d->fd);
+	if (ret)
+		return;
+
+	debug(5, "VFIO: closed device: name=%s, fd=%d", d->name, d->fd);
+	
+	free(d->mappings);
+	free(d->name);
+}
+
+/* Constructors */
+int vfio_init(struct vfio_container *v)
+{
+	int ret;
+
+	/* Initialize datastructures */
+	memset(v, 0, sizeof(*v));
+	
+	list_init(&v->groups);
+
+	/* Load VFIO kernel module */
+	if (kernel_module_load("vfio"))
+		error("Failed to load kernel module: %s", "vfio");
+
+	/* Open VFIO API */
+	v->fd = open(VFIO_DEV("vfio"), O_RDWR);
+	if (v->fd < 0)
+		error("Failed to open VFIO container");
+
+	/* Check VFIO API version */
+	v->version = ioctl(v->fd, VFIO_GET_API_VERSION);
+	if (v->version < 0 || v->version != VFIO_API_VERSION)
+		error("Failed to get VFIO version");
+
+	/* Check available VFIO extensions (IOMMU types) */
+	v->extensions = 0;
+	for (int i = 1; i < VFIO_DMA_CC_IOMMU; i++) {
+		ret = ioctl(v->fd, VFIO_CHECK_EXTENSION, i);
+		if (ret < 0)
+			error("Failed to get VFIO extensions");
+		else if (ret > 0)
+			v->extensions |= (1 << i);
+	}
+
+	return 0;
+}
+
+int vfio_group_attach(struct vfio_group *g, struct vfio_container *c, int index)
+{
+	int ret;
+	char buf[128];
+
+	g->index = index;
+	g->container = c;
+	
+	list_init(&g->devices);
+	
+	/* Open group fd */
+	snprintf(buf, sizeof(buf), VFIO_DEV("%u"), g->index);
+	g->fd = open(buf, O_RDWR);
+	if (g->fd < 0)
+		serror("Failed to open VFIO group: %u", g->index);
+
+	/* Claim group ownership */
+	ret = ioctl(g->fd, VFIO_GROUP_SET_CONTAINER, &c->fd);
+	if (ret < 0)
+		serror("Failed to attach VFIO group to container");
+	
+	/* Set IOMMU type */
+	ret = ioctl(c->fd, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU);
+	if (ret < 0)
+		serror("Failed to set IOMMU type of container");
+
+	/* Check group viability and features */
+	g->status.argsz = sizeof(g->status);
+
+	ret = ioctl(g->fd, VFIO_GROUP_GET_STATUS, &g->status);
+	if (ret < 0)
+		serror("Failed to get VFIO group status");
+	
+	if (!(g->status.flags & VFIO_GROUP_FLAGS_VIABLE))
+		error("VFIO group is not available: bind all devices to the VFIO driver!");
+	
+	list_push(&c->groups, g);
+
+	return 0;
+}
+
+int vfio_pci_attach(struct vfio_dev *d, struct vfio_container *c, struct pci_dev *pdev)
+{
+	char name[32];
+	int ret;
+	
+	/* Load PCI bus driver for VFIO */
+	if (kernel_module_load("vfio_pci"))
+		error("Failed to load kernel driver: %s", "vfio_pci");
+	
+	/* Bind PCI card to vfio-pci driver*/
+	ret = pci_attach_driver(pdev, "vfio-pci");
+	if (ret)
+		error("Failed to attach device to driver");
+
+	/* Get IOMMU group of device */
+	int index = pci_get_iommu_group(pdev);
+	if (index < 0)
+		error("Failed to get IOMMU group of device");
+
+	/* VFIO device name consists of PCI BDF */
+	snprintf(name, sizeof(name), "%04x:%02x:%02x.%x", pdev->domain, pdev->bus, pdev->dev, pdev->func);
+
+	ret = vfio_dev_attach(d, c, name, index);
+	if (ret < 0)
+		return ret;
+	
+	/* Check if this is really a vfio-pci device */
+	if (!(d->info.flags & VFIO_DEVICE_FLAGS_PCI)) {
+		vfio_dev_destroy(d);
+		return -1;
+	}
+
+	d->pdev = pdev;
+
+	/* Initialize MSI irqs */
+	d->msi_efds = alloc(sizeof(int) * d->irqs[VFIO_PCI_MSI_IRQ_INDEX].count);
+	d->msi_irqs = alloc(sizeof(int) * d->irqs[VFIO_PCI_MSI_IRQ_INDEX].count);
+	for (int i = 0; i < d->irqs[VFIO_PCI_MSI_IRQ_INDEX].count; i++) {
+		d->msi_efds[i] = -1;
+		d->msi_irqs[i] = -1;
+	}
+
+	return 0;
+}
+
+int vfio_dev_attach(struct vfio_dev *d, struct vfio_container *c, const char *name, int index)
+{
+	int ret;
+	struct vfio_group *g = NULL;
+	
+	/* Check if group already exists */
+	list_foreach(struct vfio_group *h, &c->groups) {
+		if (h->index == index)
+			g = h;
+	}
+	
+	if (!g) {
+		g = alloc(sizeof(struct vfio_group));
+
+		/* Aquire group ownership */
+		ret = vfio_group_attach(g, c, index);
+		if (ret)
+			error("Failed to attach to IOMMU group: %u", index);
+		
+		info("Attached new group %u to VFIO container", g->index);
+	}
+
+	d->group = g;
+	d->name = strdup(name);
+
+	/* Open device fd */
+	d->fd = ioctl(g->fd, VFIO_GROUP_GET_DEVICE_FD, d->name);
+	if (d->fd < 0)
+		serror("Failed to open VFIO device: %s", d->name);
+
+	/* Get device info */
+	d->info.argsz = sizeof(d->info);
+
+	ret = ioctl(d->fd, VFIO_DEVICE_GET_INFO, &d->info);
+	if (ret < 0)
+		serror("Failed to get VFIO device info for: %s", d->name);
+
+	d->irqs     = alloc(d->info.num_irqs    * sizeof(struct vfio_irq_info));
+	d->regions  = alloc(d->info.num_regions * sizeof(struct vfio_region_info));
+	d->mappings = alloc(d->info.num_regions * sizeof(void *));
+
+	/* Get device regions */
+	for (int i = 0; i < d->info.num_regions && i < 8; i++) {
+		struct vfio_region_info *region = &d->regions[i];
+
+		region->argsz = sizeof(*region);
+		region->index = i;
+
+		ret = ioctl(d->fd, VFIO_DEVICE_GET_REGION_INFO, region);
+		if (ret < 0)
+			serror("Failed to get regions of VFIO device: %s", d->name);
+	}
+
+	/* Get device irqs */
+	for (int i = 0; i < d->info.num_irqs; i++) {
+		struct vfio_irq_info *irq = &d->irqs[i];
+
+		irq->argsz = sizeof(*irq);
+		irq->index = i;
+
+		ret = ioctl(d->fd, VFIO_DEVICE_GET_IRQ_INFO, irq);
+		if (ret < 0)
+			serror("Failed to get IRQs of VFIO device: %s", d->name);
+	}
+	
+	list_push(&d->group->devices, d);
+
+	return 0;
+}
+
+int vfio_pci_reset(struct vfio_dev *d)
+{
+	int ret;
+
+	/* Check if this is really a vfio-pci device */
+	if (!(d->info.flags & VFIO_DEVICE_FLAGS_PCI))
+		return -1;
+
+	size_t reset_infolen = sizeof(struct vfio_pci_hot_reset_info) + sizeof(struct vfio_pci_dependent_device) * 64;
+	size_t resetlen = sizeof(struct vfio_pci_hot_reset) + sizeof(int32_t) * 1;
+
+	struct vfio_pci_hot_reset_info *reset_info = alloc(reset_infolen);
+	struct vfio_pci_hot_reset *reset = alloc(resetlen);
+
+	reset_info->argsz = reset_infolen;
+	reset->argsz = resetlen;
+
+	ret = ioctl(d->fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, reset_info);
+	if (ret)
+		return ret;
+
+	debug(5, "VFIO: dependent devices for hot-reset:");
+	for (int i = 0; i < reset_info->count; i++) { INDENT
+		struct vfio_pci_dependent_device *dd = &reset_info->devices[i];
+		debug(5, "%04x:%02x:%02x.%01x: iommu_group=%u", dd->segment, dd->bus, PCI_SLOT(dd->devfn), PCI_FUNC(dd->devfn), dd->group_id);
+
+		if (dd->group_id != d->group->index)
+			return -3;
+	}
+
+	reset->count = 1;
+	reset->group_fds[0] = d->group->fd;
+
+	ret = ioctl(d->fd, VFIO_DEVICE_PCI_HOT_RESET, reset);
+
+	free(reset_info);
+
+	return ret;
+}
+
+int vfio_pci_msi_findirqs(struct vfio_dev *d)
+{
+	FILE *f;
+	char *end, *col, *last, line[1024];
+	int ret, vector;
+	
+	f = fopen("/proc/interrupts", "r");
+	if (!f)
+		return -1;
+
+	/* Ignore header line */
+	fgets(line, sizeof(line), f);
+
+	while (fgets(line, sizeof(line), f)) {
+		col = strtok(line, " ");
+
+		/* IRQ number is in first column */
+		int irq = strtol(col, &end, 10);
+		if (col == end)
+			continue;
+
+		/* Find last column of line */
+		while ((col = strtok(NULL, " ")))
+			last = col;
+
+		char name[13];
+		ret = sscanf(last, "vfio-msi[%u](%12[0-9:])", &vector, name);
+		if (ret == 2) { /* match was successful */
+			if (strstr(d->name, name) == d->name) /* device matches */
+				d->msi_irqs[vector] = irq;
+		}
+	}
+	
+	fclose(f);
+
+	return 0;
+}
+
+int vfio_pci_msi_fd(struct vfio_dev *d, uint32_t mask)
+{
+	int efd, ret;
+	struct vfio_irq_info *msi_irqs = &d->irqs[VFIO_PCI_MSI_IRQ_INDEX];
+	struct vfio_irq_set *irq_set;
+	size_t irq_setlen;
+	
+	/* Check if this is really a vfio-pci device */
+	if (!(d->info.flags & VFIO_DEVICE_FLAGS_PCI))
+		return -1;
+
+	/* Check if already assigned */
+	for (int i = 0; i < MIN(sizeof(mask) * 8, msi_irqs->count); i++) {
+		if ((mask & (1 << i)) && (d->msi_efds[i] >= 0))
+			return -1;
+	}
+
+	/* Create new eventfd */
+	efd = eventfd(0, 0);
+	if (efd < 0)
+		return -3;
+
+	/* Assign new efd */
+	for (int i = 0; i < MIN(sizeof(mask) * 8, msi_irqs->count); i++) {
+		if (mask & (1 << i))
+			d->msi_efds[i] = efd;
+	}
+
+	irq_setlen = sizeof(struct vfio_irq_set) + msi_irqs->count * (sizeof(d->msi_efds[0]));
+	irq_set = alloc(irq_setlen);
+
+	irq_set->argsz = irq_setlen;
+	irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER;
+	irq_set->index = VFIO_PCI_MSI_IRQ_INDEX;
+	irq_set->count = msi_irqs->count;
+	irq_set->start = 0;
+	
+	/* We need to disable the complete MSI index first before adding new ones */
+	if (msi_irqs->flags & VFIO_IRQ_INFO_NORESIZE) {
+		memset(&irq_set->data[0], 0xFF, msi_irqs->count * sizeof(d->msi_efds[0]));
+
+		ret = ioctl(d->fd, VFIO_DEVICE_SET_IRQS, irq_set);
+		if (ret)
+			return -4;
+	}
+
+	memcpy(&irq_set->data[0], d->msi_efds, msi_irqs->count * sizeof(d->msi_efds[0]));
+
+	ret = ioctl(d->fd, VFIO_DEVICE_SET_IRQS, irq_set);
+	if (ret)
+		return -4;
+
+	/* Find corresponding Linux IRQ numbers */
+	ret = vfio_pci_msi_findirqs(d);
+	if (ret)
+		return -5;
+
+	free(irq_set);
+
+	return efd;
+}
+
+int vfio_pci_enable(struct vfio_dev *d)
+{
+	int ret;
+	uint32_t reg;
+	off_t offset = ((off_t) VFIO_PCI_CONFIG_REGION_INDEX << 40) + PCI_COMMAND;
+
+	/* Check if this is really a vfio-pci device */
+	if (!(d->info.flags & VFIO_DEVICE_FLAGS_PCI))
+		return -1;
+
+	ret = pread(d->fd, &reg, sizeof(reg), offset);
+	if (ret != sizeof(reg))
+		return -1;
+
+	/* Enable memory access and PCI bus mastering which is required for DMA */
+	reg |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+
+	ret = pwrite(d->fd, &reg, sizeof(reg), offset);
+	if (ret != sizeof(reg))
+		return -1;
+
+	return 0;
+}
+
+int vfio_dev_reset(struct vfio_dev *d)
+{
+	if (d->info.flags & VFIO_DEVICE_FLAGS_RESET)
+		return ioctl(d->fd, VFIO_DEVICE_RESET);
+	else
+		return -1; /* not supported by this device */
+}
+
+void vfio_dump(struct vfio_container *v)
+{
+	info("VFIO Version: %u", v->version);
+	info("VFIO Extensions: %#x", v->extensions);
+
+	list_foreach(struct vfio_group *g, &v->groups) {
+		info("VFIO Group %u, viable=%u, container=%d", g->index,
+			(g->status.flags & VFIO_GROUP_FLAGS_VIABLE) > 0,
+			(g->status.flags & VFIO_GROUP_FLAGS_CONTAINER_SET) > 0
+		);
+
+		list_foreach(struct vfio_dev *d, &g->devices) { INDENT
+			info("Device %s: regions=%u, irqs=%u, flags=%#x", d->name,
+				d->info.num_regions,
+				d->info.num_irqs,
+				d->info.flags
+			);
+
+			for (int i = 0; i < d->info.num_regions && i < 8; i++) { INDENT
+				struct vfio_region_info *region = &d->regions[i];
+
+				if (region->size > 0)
+					info("Region %u %s: size=%#llx, offset=%#llx, flags=%u",
+						region->index, (d->info.flags & VFIO_DEVICE_FLAGS_PCI) ? vfio_pci_region_names[i] : "",
+						region->size,
+						region->offset,
+						region->flags
+					);
+			}
+			
+			for (int i = 0; i < d->info.num_irqs; i++) { INDENT
+				struct vfio_irq_info *irq = &d->irqs[i];
+
+				if (irq->count > 0)
+					info("IRQ %u %s: count=%u, flags=%u",
+						irq->index, (d->info.flags & VFIO_DEVICE_FLAGS_PCI ) ? vfio_pci_irq_names[i] : "",
+						irq->count,
+						irq->flags
+				);
+			}
+		}
+	}
+}
+
+void * vfio_map_region(struct vfio_dev *d, int idx)
+{
+	struct vfio_region_info *r = &d->regions[idx];
+
+	if (!(r->flags & VFIO_REGION_INFO_FLAG_MMAP))
+		return MAP_FAILED;
+
+	d->mappings[idx] = mmap(NULL, r->size, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_32BIT, d->fd, r->offset);
+	
+	return d->mappings[idx];
+}
+
+void * vfio_map_dma(struct vfio_container *c, size_t size, size_t pgsize, uint64_t phyaddr)
+{
+	void *vaddr;
+	int ret, pgbits, flags;
+	size_t defpgsize;
+
+	defpgsize = sysconf(_SC_PAGESIZE);
+	if (!pgsize)
+		pgsize = defpgsize;
+
+	pgbits = 8 * sizeof(unsigned long long) - __builtin_clzll((unsigned long long) pgsize) - 1;
+
+	debug(3, "pgsize = %#zx", pgsize);
+	debug(3, "defpgsize = %#zx", defpgsize);
+
+	flags = MAP_PRIVATE | MAP_ANONYMOUS | MAP_32BIT;
+	if (pgsize != defpgsize) /* Map as Hugepages */
+		flags |= MAP_HUGETLB | (pgbits << MAP_HUGE_SHIFT);
+
+	vaddr = mmap(0, size, PROT_READ | PROT_WRITE, flags, 0, 0);
+	if (vaddr == MAP_FAILED)
+		return MAP_FAILED;
+
+	debug(3, "Allocated VM for DMA mapping at: %p", vaddr);
+	
+	struct vfio_iommu_type1_dma_map dma_map = {
+		.argsz = sizeof(struct vfio_iommu_type1_dma_map),
+		.vaddr = (uint64_t) vaddr,
+		.size = size,
+		.iova = phyaddr,
+		.flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE
+	};
+
+	ret = ioctl(c->fd, VFIO_IOMMU_MAP_DMA, &dma_map);
+	if (ret)
+		serror("Failed to create DMA mapping");
+
+	info("DMA map size=%#llx, iova=%#llx, vaddr=%#llx", dma_map.size, dma_map.iova, dma_map.vaddr);
+
+	return vaddr;
+}
+
+int vfio_unmap_region(struct vfio_dev *d, int idx)
+{
+	struct vfio_region_info *r = &d->regions[idx];
+	
+	if (!d->mappings[idx])
+		return -1; /* was not mapped */
+	
+	debug(3, "VFIO: unmap region %u from device", idx);
+	
+	return munmap(d->mappings[idx], r->size);
+}
+
+int vfio_unmap_dma(struct vfio_container *c)
+{
+	struct vfio_iommu_type1_dma_unmap dma_unmap = {
+		.argsz = sizeof(struct vfio_iommu_type1_dma_unmap),
+		.flags = 0,
+		.iova = 0, /* IO virtual address */
+		.size = 0  /* Size of mapping (bytes) */
+	};
+
+	debug(3, "VFIO: unmap DMA region from device");
+	
+	return ioctl(c->fd, VFIO_IOMMU_UNMAP_DMA, &dma_unmap);
+}

lib/nodes/vfpga.c

@@ -0,0 +1,353 @@
+/** Node type: VILLASfpga
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ *********************************************************************************/
+
+#include <stdio.h>
+#include <inttypes.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <sys/mman.h>
+
+#include "kernel/kernel.h"
+#include "kernel/pci.h"
+
+#include "nodes/vfpga.h"
+
+#include "config.h"
+#include "config-fpga.h"
+#include "utils.h"
+#include "timing.h"
+
+static struct pci_access *pacc;
+
+typedef void(*log_cb_t)(char *, ...);
+
+int vfpga_init2(struct vfpga *f, struct vfio_container *vc, struct pci_dev *pdev)
+{
+	int ret;
+
+	list_init(&f->models);
+	
+	f->features = 0;
+
+	if (pdev->vendor_id != PCI_VID_XILINX)
+		error("This is not a Xilinx FPGA board!");
+
+	/* Attach PCIe card to VFIO container */
+	ret = vfio_pci_attach(&f->vd, vc, pdev);
+	if (ret)
+		error("Failed to attach VFIO device");
+
+	/* Setup IRQs */
+	for (int i = 0; i < f->vd.irqs[VFIO_PCI_MSI_IRQ_INDEX].count; i++) {
+		ret = vfio_pci_msi_fd(&f->vd, (1 << i));
+		if (ret < 0)
+			serror("Failed to create eventfd for IRQ: ret=%d", f->vd.msi_efds[i]);
+	}
+
+	/* Map PCIe BAR */
+	f->map = vfio_map_region(&f->vd, VFIO_PCI_BAR0_REGION_INDEX);
+	if (f->map == MAP_FAILED)
+		serror("Failed to mmap() BAR0");
+	
+	/* Map DMA accessible memory */
+	f->dma = vfio_map_dma(f->vd.group->container, 0x10000, 0x1000, 0x0);
+	if (f->dma == MAP_FAILED)
+		serror("Failed to mmap() DMA");
+
+	/* Enable memory access and PCI bus mastering for DMA */
+	ret = vfio_pci_enable(&f->vd);
+	if (ret)
+		serror("Failed to enable PCI device");
+	
+#if 1
+	/* Trigger internal reset of fpga card / PCIe endpoint */
+	ret = vfpga_reset(f);
+	if (ret)
+		serror("Failed to reset fpga card");
+#endif
+
+	/* Reset / detect PCI device */
+	ret = vfio_pci_reset(&f->vd);
+	if (ret)
+		serror("Failed to reset PCI device");
+
+	/* Initialize Interrupt controller */
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IMR_OFFSET, 0);
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IAR_OFFSET, 0xFFFFFFFF); /* Acknowlege all pending IRQs */
+	usleep(1000);
+
+	/* Setup Vectors */
+	for (int i = 0; i < 16; i++)
+		XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IVAR_OFFSET + i * sizeof(uint32_t), i);
+
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IMR_OFFSET, 0xFFFFFFFF); /* Use fast acknowlegement for all IRQs */
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, 0x00000000);
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_MER_OFFSET, XIN_INT_HARDWARE_ENABLE_MASK | XIN_INT_MASTER_ENABLE_MASK);
+
+#ifdef HAS_SWITCH
+	/* Initialize AXI4-Sream crossbar switch */
+	ret = switch_init(&f->sw, f->map + BASEADDR_SWITCH, AXI_SWITCH_NUM, AXI_SWITCH_NUM);
+	if (ret)
+		error("Failed to initialize switch");
+#endif
+
+#ifdef HAS_XSG
+	/* Initialize System Generator model */
+	struct model *m = alloc(sizeof(struct model));
+	m->baseaddr = f->map + BASEADDR_XSG;
+	m->type = MODEL_TYPE_XSG;
+
+	ret = model_init(m, NULL);
+	if (ret)
+		error("Failed to init model: %d", ret);
+
+	ret = xsg_init_from_map(m);
+	if (ret)
+		error("Failed to init XSG model: %d", ret);
+	
+	list_push(&f->models, m);
+#endif
+
+#ifdef HAS_FIFO_MM
+	/* Initialize AXI4-Stream Memory Mapped FIFO */
+	ret = fifo_init(&f->fifo, f->map + BASEADDR_FIFO_MM, f->map + BASEADDR_FIFO_MM_AXI4);
+	if (ret)
+		error("Failed to initialize FIFO");
+#endif
+
+#ifdef HAS_DMA_SG
+	/* Initialize Scatter Gather DMA controller */
+	struct dma_mem bd = {
+		.base_virt = (uintptr_t) f->map + BASEADDR_BRAM,
+		.base_phys = BASEADDR_BRAM,
+		.len = 0x2000
+	};
+	struct dma_mem rx = {
+		.base_virt = (uintptr_t) f->dma,
+		.base_phys = BASEADDR_HOST,
+		.len = 0x10000
+	};
+
+	ret = dma_init(&f->dma_sg, f->map + BASEADDR_DMA_SG, DMA_MODE_SG, &bd, &rx, sizeof(uint32_t) * 64);
+	if (ret)
+		return -1;
+#endif
+
+#ifdef HAS_DMA_SIMPLE
+	/* Initialize Simple DMA controller */
+	ret = dma_init(&f->dma_simple, f->map + BASEADDR_DMA_SIMPLE, DMA_MODE_SIMPLE, 0, 0, 0);
+	if (ret)
+		return -1;
+#endif
+
+#ifdef HAS_TIMER
+	/* Initialize timer */
+	XTmrCtr_Config tmr_cfg = {
+		.BaseAddress = (uintptr_t) f->map + BASEADDR_TIMER,
+		.SysClockFreqHz = AXI_HZ
+	};
+
+	XTmrCtr_CfgInitialize(&f->tmr, &tmr_cfg, (uintptr_t) f->map + BASEADDR_TIMER);
+	XTmrCtr_InitHw(&f->tmr);
+#endif
+
+	return 0;
+}
+
+int vfpga_deinit2(struct vfpga *f)
+{
+	list_destroy(&f->models, (dtor_cb_t) model_destroy, true);
+
+	return 0;
+}
+
+int vfpga_reset(struct vfpga *f)
+{
+	int ret;
+	char state[4096];
+
+	/* Save current state of PCI configuration space */
+	ret = pread(f->vd.fd, state, sizeof(state), (off_t) VFIO_PCI_CONFIG_REGION_INDEX << 40);
+	if (ret != sizeof(state))
+		return -1;
+
+	uint32_t *rst_reg = (uint32_t *) (f->map + BASEADDR_RESET);
+
+	info("Reset fpga");
+	rst_reg[0] = 1;
+
+	usleep(100000);
+
+	/* Restore previous state of PCI configuration space */
+	ret = pwrite(f->vd.fd, state, sizeof(state), (off_t) VFIO_PCI_CONFIG_REGION_INDEX << 40);
+	if (ret != sizeof(state))
+		return -1;
+
+	info("Reset status = %#x", *rst_reg);
+
+	return 0;
+}
+
+/* Dump some details about the fpga card */
+void vfpga_dump(struct vfpga *f)
+{
+	char namebuf[128];
+	char *name;
+
+	name = pci_lookup_name(pacc, namebuf, sizeof(namebuf), PCI_LOOKUP_DEVICE, f->vd.pdev->vendor_id, f->vd.pdev->device_id);
+	pci_fill_info(f->vd.pdev, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_CLASS);	/* Fill in header info we need */
+
+	info("Found fpga card: %s", name);
+	{ INDENT
+		info("slot=%04x:%02x:%02x.%d", f->vd.pdev->domain, f->vd.pdev->bus, f->vd.pdev->dev, f->vd.pdev->func);
+		info("vendor=%04x", f->vd.pdev->vendor_id);
+		info("device=%04x", f->vd.pdev->device_id);
+		info("class=%04x", f->vd.pdev->device_class);
+	}
+	info("BAR0 mapped at %p", f->map);
+
+	vfio_dump(f->vd.group->container);
+}
+
+static void vfpga_debug(char *msg, ...) {
+	va_list ap;
+
+	va_start(ap, msg);
+	log_vprint(LOG_LVL_DEBUG, msg, ap);
+	va_end(ap);
+}
+
+int vfpga_init(int argc, char * argv[], config_setting_t *cfg)
+{
+	if (getuid() != 0)
+		error("The vfpga node-type requires superuser privileges!");
+
+	pacc = pci_alloc();		/* Get the pci_access structure */
+	if (!pacc)
+		error("Failed to allocate PCI access structure");
+
+	pci_init(pacc);			/* Initialize the PCI library */
+
+	pacc->error = (log_cb_t) error;	/* Replace logging and debug functions */
+	pacc->warning = (log_cb_t) warn;
+	pacc->debug = vfpga_debug;
+
+	pci_scan_bus(pacc);		/* We want to get the list of devices */
+
+	return 0;
+}
+
+int vfpga_deinit()
+{
+	pci_cleanup(pacc);
+
+	return 0;
+}
+
+int vfpga_parse(struct node *n, config_setting_t *cfg)
+{
+	struct vfpga *v = n->_vd;
+
+	const char *slot, *id, *err;
+	config_setting_t *cfg_slot, *cfg_id;
+
+	pci_filter_init(NULL, &v->filter);
+
+	cfg_slot = config_setting_get_member(cfg, "slot");
+	if (cfg_slot) {
+		slot = config_setting_get_string(cfg_slot);
+		if (slot) {
+			err = pci_filter_parse_slot(&v->filter, (char*) slot);
+			if (err)
+				cerror(cfg_slot, "%s", err);
+		}
+		else
+			cerror(cfg_slot, "Invalid slot format");
+	}
+
+	cfg_id = config_setting_get_member(cfg, "id");
+	if (cfg_id) {
+		id = config_setting_get_string(cfg_id);
+		if (id) {
+			err = pci_filter_parse_id(&v->filter, (char*) id);
+			if (err)
+				cerror(cfg_id, "%s", err);
+		}
+		else
+			cerror(cfg_slot, "Invalid id format");
+	}
+
+	return 0;
+}
+
+char * vfpga_print(struct node *n)
+{
+	struct vfpga *v = n->_vd;
+
+	return strf("slot=%02"PRIx8":%02"PRIx8".%"PRIx8" id=%04"PRIx16":%04"PRIx16,
+		v->filter.bus, v->filter.device, v->filter.func,
+		v->filter.vendor, v->filter.device);
+}
+
+int vfpga_open(struct node *n)
+{
+	struct vfpga *v = n->_vd;
+	struct pci_dev *dev;
+
+	dev = pci_find_device(pacc, &v->filter);
+	if (!dev)
+		error("No vfpga card found");
+
+	/* @todo */
+
+	return 0;
+}
+
+int vfpga_close(struct node *n)
+{
+//	struct vfpga *v = n->_vd;
+
+	/* @todo */
+
+	return 0;
+}
+
+int vfpga_read(struct node *n, struct sample *smps[], unsigned cnt)
+{
+//	struct vfpga *v = n->_vd;
+
+	/** @todo */
+
+	return 0;
+}
+
+/** @todo implement */
+int vfpga_write(struct node *n, struct sample *smps[], unsigned cnt)
+{
+//	struct vfpga *v = n->_vd;
+
+	/** @todo */
+
+	return 0;
+}
+
+static struct node_type vt = {
+	.name		= "vfpga",
+	.description	= "VILLASfpga PCIe card (libpci)",
+	.vectorize	= 0,
+	.parse		= vfpga_parse,
+	.print		= vfpga_print,
+	.open		= vfpga_open,
+	.close		= vfpga_close,
+	.read		= vfpga_read,
+	.write		= vfpga_write,
+	.init		= vfpga_init,
+	.deinit		= vfpga_deinit
+};
+
+REGISTER_NODE_TYPE(&vt)

lib/utils.c

@@ -202,4 +202,94 @@ void * memdup(const void *src, size_t bytes)
 	memcpy(dst, src, bytes);
 	
 	return dst;
+}
+
+#include <stdio.h>
+#include <stdint.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <ctype.h>
+
+#include "utils.h"
+
+uint64_t wait_irq(int irq)
+{
+	ssize_t ret;
+	uint64_t cnt;
+
+	ret = read(irq, &cnt, sizeof(cnt));
+	if (ret != sizeof(cnt))
+		return 0;
+
+	return cnt;
+}
+
+int read_random(char *buf, size_t len)
+{
+	int ret, fd;
+	
+	fd = open("/dev/urandom", O_RDONLY);
+	if (fd < 0)
+		return -1;
+	
+	ret = read(fd, buf, len);
+	if (ret != len)
+		ret = -1;
+	else
+		ret = 0;
+
+	close(fd);
+
+	return ret;
+}
+
+void printb(void *mem, size_t len)
+{
+	uint8_t *mem8 = (uint8_t *) mem;
+
+	for (int i = 0; i < len; i++) {
+		printf("%02hx ", mem8[i]);
+
+		if (i % 16 == 15)
+			printf("\n");
+	}
+}
+
+void printdw(void *mem, size_t len)
+{
+	int columns = 4;
+
+	uint32_t *mem32 = (uint32_t *) mem;
+
+	for (int i = 0; i < len; i++) {
+		if (i % columns == 0)
+			printf("%#x: ", i * 4);
+
+		printf("%08x ", mem32[i]);
+		
+		char *memc = (char *) &mem32[i];
+		printf("%c%c%c%c ",
+			isprint(memc[0]) ? memc[0] : ' ',
+			isprint(memc[1]) ? memc[1] : ' ',
+			isprint(memc[2]) ? memc[2] : ' ',
+			isprint(memc[3]) ? memc[3] : ' '
+		);
+
+		if ((i+1) % columns == 0)
+			printf("\n");
+	}
+}
+
+void rdtsc_sleep(uint64_t nanosecs, uint64_t start)
+{
+	uint64_t cycles;
+
+	cycles = (double) nanosecs / (1e9 / 3392389000);
+	
+	if (start == 0)
+		start = rdtscp();
+	
+	do {
+		__asm__("nop");
+	} while (rdtscp() - start < cycles);
 }

src/fpga-bench.c

@@ -0,0 +1,159 @@
+/** Benchmarks for VILLASfpga
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <villas/utils.h>
+#include <villas/hist.h>
+#include <villas/log.h>
+#include <villas/nodes/vfpga.h>
+
+#include "config.h"
+#include "config-fpga.h"
+
+#define BENCH_EXP_MIN	2	// 1 << 2 = 4 Bytes
+#define BENCH_EXP_MAX	17	// 1 << 17 = 128 MiB
+
+#define BENCH_ROUNDS	10000
+#define BENCH_WARMUP	2000
+
+/* List of available benchmarks */
+enum benchmarks {
+	BENCH_FIFO,
+	BENCH_DMA_SIMPLE,
+	BENCH_DMA_SG,
+	MAX_BENCHS
+};
+
+static int bench_run(struct vfpga *f, int polling, int bench)
+{
+	struct hist hist;
+	uint64_t start, stop;
+	
+	hist_create(&hist, 0, 0, 1);
+
+	int irq_fifo     = polling ? -1 : f->vd.msi_efds[MSI_FIFO_MM];
+	int irq_dma_mm2s = polling ? -1 : f->vd.msi_efds[MSI_DMA_MM2S];
+	int irq_dma_s2mm = polling ? -1 : f->vd.msi_efds[MSI_DMA_S2MM];
+	
+	char *src, *dst;
+	size_t len;
+
+	for (int exp = BENCH_EXP_MIN; exp < BENCH_EXP_MAX; exp++) {
+		size_t sz = 1 << exp;
+		
+		hist_reset(&hist);
+		read_random(src, len);
+		memset(dst, 0, len);
+
+		info("Running bench with size: %#zx", sz);
+
+		for (int i = 0; i < BENCH_ROUNDS + BENCH_WARMUP; i++) {
+			start = rdtscp();
+
+			switch (bench) {
+				case BENCH_FIFO:
+					fifo_write(&f->fifo, src, len, irq_fifo);
+					fifo_read(&f->fifo, src, len, irq_fifo);
+					break;
+				case BENCH_DMA_SG:
+					dma_write(&f->dma_sg, src, len, irq_dma_mm2s);
+					dma_read(&f->dma_sg, src, len, irq_dma_s2mm);
+					break;
+				case BENCH_DMA_SIMPLE:
+					dma_write(&f->dma_simple, src, len, irq_dma_mm2s);
+					dma_read(&f->dma_simple, src, len, irq_dma_s2mm);
+					break;
+			}
+			
+			stop = rdtscp();
+
+			if (memcmp(src, dst, len))
+				warn("Compare failed");
+
+			if (i > BENCH_WARMUP)
+				hist_put(&hist, stop - start);
+		}
+
+		hist_dump(&hist);
+	}
+
+	hist_destroy(&hist);
+}
+
+int bench_dm(struct vfpga *f)
+{
+	int irq_fifo, irq_dma_mm2s, irq_dma_s2mm;
+	int polling = true;
+	int ret;
+
+	/* Loopback all datamovers */
+	switch_connect(&f->sw, AXIS_SWITCH_DMA_SIMPLE, AXIS_SWITCH_DMA_SIMPLE);
+	switch_connect(&f->sw, AXIS_SWITCH_DMA_SG, AXIS_SWITCH_DMA_SG);
+	switch_connect(&f->sw, AXIS_SWITCH_FIFO_MM, AXIS_SWITCH_FIFO_MM);
+
+	for (polling = 0; polling <= 1; polling++) {
+		for (int i = 0; i < MAX_BENCHS; i++)
+			bench_run(f, polling, i);
+	}
+
+	return 0;
+}
+
+int bench_memcpy(struct vfpga *f)
+{
+	uint64_t start, end, total = 0;
+
+#if 1
+	char *src = f->map;
+	char *dst = alloc(1 << 13);
+#else
+	char *dst = f->map;
+	char *src = alloc(1 << 13);
+	read_random(src, 1 << 13);
+#endif
+
+	char *srcb = src;
+	for (int i = 0; i < 1 << 13; i++)
+		srcb[i] = i;
+
+	unsigned long long runs = 10000;
+	
+	fgetc(stdin);
+	
+	//memcpy(dst, src, 0xFF);
+	
+	for (int i = 0; i < 64; i++)
+		dst[i] = src[i];
+	
+	fgetc(stdin);
+
+	for (int exp = 0; exp < 14; exp++) {
+		size_t len = 1 << exp;
+
+		for (int i = 0; i < runs; i++) {
+			/* Clear cache */
+			for (char *p = src; p < src + len; p += 64)
+				__builtin_ia32_clflush(p);
+
+	//		for (char *p = f->dma; p < src + len; p += 64)
+	//			__builtin_ia32_clflush(p);
+
+			/* Start measurement */
+			start = rdtscp();
+			memcpy(dst, src, len);
+			end = rdtscp();
+		
+			total += end - start;
+		}
+		
+		info("avg. clk cycles for %u bytes = %u", len, total / runs);
+		usleep(100000);
+	}
+}

src/fpga-tests.c

@@ -0,0 +1,404 @@
+/** Test procedures for VILLASfpga
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ *********************************************************************************/
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <fcntl.h>
+#include <poll.h>
+#include <time.h>
+
+#include <villas/utils.h>
+#include <villas/nodes/vfpga.h>
+
+#include "fpga-tests.h"
+#include "config.h"
+#include "config-fpga.h"
+
+//#include "cbuilder/cbmodel.h"
+
+#define TEST_LEN 0x1000
+
+#define CPU_HZ 3392389000
+
+int test_intc(struct vfpga *f)
+{
+	uint32_t ier, isr;
+
+	/* Save old IER */
+	ier = XIntc_In32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET);
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier | 0xFF00);
+
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_ISR_OFFSET, 0xFF00);
+
+	debug(3, "Wait for 8 SW triggerd interrupts");
+	for (int i = 0; i < 8; i++)
+		wait_irq(f->vd.msi_efds[i+8]);
+
+	isr = XIntc_In32((uintptr_t) f->map + BASEADDR_INTC + XIN_ISR_OFFSET);
+	
+	/* Restore IER */
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier);
+
+	return (isr & 0xFF00) ? -1 : 0; /* ISR should get cleared by MSI_Grant_signal */
+}
+
+#ifdef HAS_XSG
+int test_xsg(struct vfpga *f, const char *name)
+{
+	struct model *m;
+
+	m = list_lookup(&f->models, name);
+	if (m) {
+		model_dump(m);
+
+		list_foreach(struct model_param *p, &m->parameters) {
+			if (p->direction == MODEL_PARAM_IN) {
+				model_param_write(p, p->default_value.flt);
+				info("Param '%s' updated to: %f", p->name, p->default_value.flt);
+			}
+		}
+
+		if (strcmp(m->name, "xsg_multiply_add") == 0) {
+			switch_connect(&f->sw, AXIS_SWITCH_DMA_SIMPLE, AXIS_SWITCH_XSG);
+			switch_connect(&f->sw, AXIS_SWITCH_XSG, AXIS_SWITCH_DMA_SIMPLE);
+
+			float *src = (float *) f->dma;
+			float *dst = (float *) f->dma + TEST_LEN;
+			
+			for (int i = 0; i < 6; i++)
+				src[i] = 1.1 * (i+1);
+
+			ssize_t len = dma_ping_pong(&f->dma_simple, virt_to_dma(src, f->dma), virt_to_dma(dst, f->dma), 6 * sizeof(float), -1);
+			if (len != 6 * sizeof(float))
+				error("Failed to to ping pong DMA transfer: %zd", len);
+
+			for (int i = 0; i < 6; i++)
+				info("src[%d] = %f", i, src[i]);
+			for (int i = 0; i < 6; i++)
+				info("dst[%d] = %f", i, dst[i]);
+		}
+	}
+	else
+		warn("There is no model named '%s'", name);
+
+	return 0;
+}
+#endif
+
+#ifdef HAS_FIFO_MM
+int test_fifo(struct vfpga *f)
+{
+	int ret;
+	ssize_t len;
+	uintptr_t baseaddr = (uintptr_t) (f->map + BASEADDR_FIFO_MM);
+	char src[255], dst[255];
+	uint32_t ier;
+
+	/* Save old IER */
+	ier = XIntc_In32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET);
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier | (1 << MSI_FIFO_MM));
+
+	/* Get some random data to compare */
+	memset(dst, 0, sizeof(dst));
+	ret = read_random((char *) src, sizeof(src));
+	if (ret)
+		error("Failed to get random data");
+
+	ret = switch_connect(&f->sw, AXIS_SWITCH_FIFO_MM, AXIS_SWITCH_FIFO_MM);
+	if (ret)
+		error("Failed to configure switch");
+
+	len = fifo_write(&f->fifo, (char *) src, sizeof(src), f->vd.msi_efds[MSI_FIFO_MM]);
+	if (len != sizeof(src))
+		error("Failed to send to FIFO");
+
+	len = fifo_read(&f->fifo, (char *) dst, sizeof(dst), f->vd.msi_efds[MSI_FIFO_MM]);
+	if (len != sizeof(dst))
+		error("Failed to read from FIFO");
+
+	/* Restore IER */
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier);
+
+	/* Compare data */
+	return memcmp(src, dst, sizeof(src));
+}
+#endif
+
+#if defined(HAS_DMA_SG) || defined(HAS_DMA_SIMPLE)
+int test_dma(struct vfpga *f)
+{
+	int ret;
+	ssize_t len;
+	uint32_t ier;
+
+	/* Save old IER */
+	ier = XIntc_In32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET);
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier | (1 << MSI_DMA_MM2S) | (1 << MSI_DMA_S2MM));
+
+	ret = switch_connect(&f->sw, AXIS_SWITCH_DMA_SIMPLE, AXIS_SWITCH_DMA_SIMPLE);
+	if (ret)
+		error("Failed to configure switch");
+
+#ifdef HAS_DMA_SG
+	/* Memory for buffer descriptors and RX */
+	struct dma_mem bd = {
+		.base_virt = (uintptr_t) f->map + BASEADDR_BRAM,
+		.base_phys = BASEADDR_BRAM,
+		.len = 8 * 1024
+	};
+	
+	struct dma_mem rx = {
+		.base_virt = (uintptr_t) f->dma + TEST_LEN,
+		.base_phys = BASEADDR_HOST + TEST_LEN,
+		.len = TEST_LEN
+	};
+#endif
+
+	/* Get some random data to compare */
+	char *src = f->dma;
+	char *dst = f->dma + TEST_LEN;
+
+	ret = read_random(src, TEST_LEN);
+	if (ret)
+		error("Failed to get random data");
+
+#if 0
+	len = dma_write(&f->dma_simple, virt_to_dma(src, f->dma), TEST_LEN, -1);//f->vd.msi_efds[MSI_DMA_MM2S]);
+	if (len != TEST_LEN)
+		error("Failed to send to DMAC: %zd", len);
+
+	len = dma_read(&f->dma_simple, virt_to_dma(dst, f->dma), TEST_LEN, -1);//f->vd.msi_efds[MSI_DMA_S2MM]);
+	if (len != TEST_LEN)
+		error("Failed to send to DMAC: %zd", len);
+#else
+	len = dma_ping_pong(&f->dma_simple, virt_to_dma(src, f->dma), virt_to_dma(dst, f->dma), TEST_LEN, f->vd.msi_efds[MSI_DMA_S2MM]);
+	if (len != TEST_LEN)
+		error("Failed to to ping pong DMA transfer: %zd", len);
+#endif
+
+	/* Restore IER */
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier);
+
+	/* Check received data */
+	return memcmp(src, dst, TEST_LEN);
+}
+#endif
+
+#ifdef HAS_TIMER
+int test_timer(struct vfpga *f)
+{
+	int ret;
+	bool success;
+	uint32_t ier;
+
+	/* Save old IER */
+	ier = XIntc_In32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET);
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier | (1 << MSI_TMRCTR0));
+
+	XTmrCtr_SetOptions(&f->tmr, 0, XTC_EXT_COMPARE_OPTION | XTC_DOWN_COUNT_OPTION);
+	XTmrCtr_SetResetValue(&f->tmr, 0, AXI_HZ / 125);
+	XTmrCtr_Start(&f->tmr, 0);
+
+	struct pollfd pfd = {
+		.fd = f->vd.msi_efds[MSI_TMRCTR0],
+		.events = POLLIN
+	};
+
+	ret = poll(&pfd, 1, 1000);
+	if (ret == 1) {
+		uint64_t counter = wait_irq(f->vd.msi_efds[MSI_TMRCTR0]);
+
+		info("Got IRQ: counter = %llu", counter);
+
+		if (counter == 1)
+			return 0;
+		else
+			warn("Counter was not 1");
+	}
+
+	/* Restore IER */
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier);
+
+	return -1;
+}
+#endif
+
+#ifdef HAS_RTDS_AXIS
+int test_rtds_cbuilder(struct vfpga *f)
+{
+	int ret;
+	int values_tx = 1;
+	int values_rx;
+	uint32_t tsc = 0, ovfl = 0;
+	ssize_t len;
+	uint32_t ier;
+
+	/* Save old IER */
+	ier = XIntc_In32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET);
+//	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier | (1 << MSI_DMA_MM2S) | (1 << MSI_DMA_S2MM));
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier | (1 << MSI_RTDS_OVF));
+
+	/* Dump RTDS AXI Stream state */
+	rtds_axis_dump(f->map + BASEADDR_RTDS);
+
+	/* Get some random data to compare */
+	float *data_rx = (uint32_t *) (f->dma);
+	float *data_tx = (uint32_t *) (f->dma + 0x1000);
+
+	/* Setup crossbar switch */
+	switch_connect(&f->sw, AXIS_SWITCH_RTDS, AXIS_SWITCH_DMA_SIMPLE);
+	switch_connect(&f->sw, AXIS_SWITCH_DMA_SIMPLE, AXIS_SWITCH_RTDS);
+
+	/* Disable blocking Overflow status */
+	int flags = fcntl(f->vd.msi_efds[MSI_RTDS_OVF], F_GETFL, 0);
+	fcntl(f->vd.msi_efds[MSI_RTDS_OVF], F_SETFL, flags | O_NONBLOCK);
+	
+	/* Initialize CBuilder model */
+	double mdl_dt = rtds_axis_dt(f->map + BASEADDR_RTDS);
+	double mdl_params[] = {
+		1,	/**< R2 = 1 Ohm */
+		0.001	/**< C2 = 1000 uF */
+	};
+	double mdl_inputs[1];
+	double mdl_outputs[1];
+
+	cbmodel_init(&mdl_params, mdl_dt);
+
+	while (1) {
+		/* Check for overflow */
+		ovfl += wait_irq(f->vd.msi_efds[MSI_RTDS_OVF]);
+		if (tsc % (int) (1.0 / mdl_dt) == 0)
+			warn("Missed %u timesteps", ovfl);
+		
+		break;
+
+		/* Read data from RTDS */
+		len = dma_read(&f->dma_simple, virt_to_dma(data_rx, f->dma), 0x1000, -1);
+		uint64_t start = rdtscp();
+		XAxiDma_IntrAckIrq(&f->dma_simple, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
+
+		values_rx = len / sizeof(uint32_t);
+
+		mdl_inputs[0] = data_rx[0]; /* cast to double */
+		
+		/* Run CBuilder model */
+		cbmodel_step(mdl_inputs, mdl_outputs);
+		
+		data_tx[0] = mdl_outputs[0]; /* cast to float */
+
+		/* Send data to RTDS */
+		len = dma_write(&f->dma_simple, virt_to_dma(data_tx, f->dma), sizeof(uint32_t) * values_tx, -1);
+		XAxiDma_IntrAckIrq(&f->dma_simple, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
+	}
+
+	/* Restore IER */
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier);
+
+	return 0;
+}
+
+int test_rtds_rtt(struct vfpga *f)
+{
+	int ret;
+	int values_tx = 64;
+	int values_rx;
+	uint32_t tsc = 0, ovfl = 0;
+	ssize_t len;
+	uint32_t ier;
+
+	/* Save old IER */
+	ier = XIntc_In32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET);
+//	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier | (1 << MSI_DMA_MM2S) | (1 << MSI_DMA_S2MM));
+
+	/* Dump RTDS AXI Stream state */
+	rtds_axis_dump(f->map + BASEADDR_RTDS);
+
+	/* Get some random data to compare */
+	uint32_t *data_rx = (uint32_t *) (f->dma);
+	uint32_t *data_tx = (uint32_t *) (f->dma + 0x1000);
+
+	int switch_port;
+#if DATAMOVER == RTDS_DM_FIFO
+	switch_port = AXIS_SWITCH_FIFO_MM;
+#elif DATAMOVER == RTDS_DM_DMA_SIMPLE
+	switch_port = AXIS_SWITCH_DMA_SIMPLE;
+#elif DATAMOVER == RTDS_DM_DMA_SG
+	switch_port = AXIS_SWITCH_DMA_SG;
+#endif
+
+	/* Setup crossbar switch */
+	switch_connect(&f->sw, AXIS_SWITCH_RTDS, switch_port);
+	switch_connect(&f->sw, switch_port, AXIS_SWITCH_RTDS);
+
+	/* Disable blocking Overflow status */
+	int flags = fcntl(f->vd.msi_efds[MSI_RTDS_OVF], F_GETFL, 0);
+	fcntl(f->vd.msi_efds[MSI_RTDS_OVF], F_SETFL, flags | O_NONBLOCK);
+
+	int irq_fifo = f->vd.msi_efds[MSI_FIFO_MM];
+	int rtt2_prev, rtt2;
+
+	while (1) {
+#if 0		/* Wait for TS */
+		tsc += wait_irq(f->vd.msi_efds[MSI_RTDS_TS]);
+#else
+		tsc++;
+#endif
+
+#if 0		/* Check for overflow */
+		ovfl += wait_irq(f->vd.msi_efds[MSI_RTDS_OVF]);
+		if (tsc % 20000 == 0)
+			warn("Missed %u timesteps", ovfl);
+#endif
+
+#if DATAMOVER == RTDS_DM_FIFO
+retry:		len = fifo_read(&f->fifo, (char *) data_rx, 0x1000, irq_fifo);
+		if (XLlFifo_RxOccupancy(&f->fifo) > 0 )
+			goto retry;
+#elif DATAMOVER == RTDS_DM_DMA_SIMPLE
+		len = dma_read(&f->dma_simple, virt_to_dma(data_rx, f->dma), 0x1000, -1);//f->vd.msi_efds[MSI_DMA_S2MM]);
+		uint64_t start = rdtscp();
+		XAxiDma_IntrAckIrq(&f->dma_simple, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
+#elif DATAMOVER == RTDS_DM_DMA_SG
+		len = dma_read(&f->dma_sg, virt_to_dma(data_rx, f->dma), 0x1000, f->vd.msi_efds[MSI_DMA_S2MM]);
+#endif
+		values_rx = len / sizeof(uint32_t);
+
+		for (int i = 0; i < values_tx; i++)
+			data_tx[i] = data_rx[i];
+		
+		data_tx[3] = tsc;
+
+		if (data_rx[3] == 0)
+			tsc = 0;
+		
+		int rtt = tsc - data_rx[3];
+		
+		rtt2_prev = rtt2;
+		rtt2 = tsc - data_rx[0];
+
+		rdtsc_sleep(30000, start);
+
+#if DATAMOVER == RTDS_DM_FIFO
+		len = fifo_write(&f->fifo, (char *) data_tx, sizeof(uint32_t) * values_tx, irq_fifo);
+		if (len != sizeof(uint32_t) * values_tx)
+			error("Failed to send to FIFO");
+#elif DATAMOVER == RTDS_DM_DMA_SIMPLE
+		len = dma_write(&f->dma_simple, virt_to_dma(data_tx, f->dma), sizeof(uint32_t) * values_tx, -1);//f->vd.msi_efds[MSI_DMA_MM2S]);
+		XAxiDma_IntrAckIrq(&f->dma_simple, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
+#elif DATAMOVER == RTDS_DM_DMA_SG
+		len = dma_write(&f->dma_sg, virt_to_dma(data_tx, f->dma), sizeof(uint32_t) * values_tx, f->vd.msi_efds[MSI_DMA_MM2S]);
+#endif
+	}
+
+	/* Restore IER */
+	XIntc_Out32((uintptr_t) f->map + BASEADDR_INTC + XIN_IER_OFFSET, ier);
+
+	return 0;
+}
+#endif

src/fpga.c

@@ -0,0 +1,165 @@
+/** VILLASfpga utility for tests and benchmarks
+ *
+ * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @copyright 2015-2016, Steffen Vogel
+ *   This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
+ *   Unauthorized copying of this file, via any medium is strictly prohibited.
+ **********************************************************************************/
+ 
+#include <stdlib.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <dirent.h>
+#include <errno.h>
+#include <sys/mman.h>
+#include <fcntl.h>
+#include <getopt.h>
+#include <sched.h>
+
+#include <villas/log.h>
+#include <villas/timing.h>
+#include <villas/utils.h>
+#include <villas/nodes/vfpga.h>
+#include <villas/kernel/pci.h>
+#include <villas/kernel/kernel.h>
+
+#include "config.h"
+#include "config-fpga.h"
+
+#include "fpga-tests.h"
+#include "fpga-bench.h"
+
+static struct pci_access *pacc;
+
+void usage(char *name)
+{
+	printf("Usage: %s [ARGS]\n", name);
+	printf("  -d    Set log level\n");
+	printf("  -i    ID pair of PCI device: [vendor]:[device][:class]\n");
+	printf("  -s    Slot of PCI device: [[[domain]:][bus]:][slot][.[func]]\n\n");
+	printf("fpga PCIutil %s (built on %s %s)\n",
+		VERSION, __DATE__, __TIME__);
+	printf(" copyright 2014-2015, Institute for Automation of Complex Power Systems, EONERC\n");
+	printf(" Steffen Vogel <StVogel@eonerc.rwth-aachen.de>\n");
+}
+
+int main(int argc, char *argv[])
+{
+	int ret;
+	char *err;
+
+	struct vfpga fpga;
+	struct vfio_container vc;
+	struct pci_dev *pdev;
+	struct pci_filter filter;
+
+	/* Init libpci */
+	pacc = pci_alloc();		/* Get the pci_access structure */
+	pci_init(pacc);			/* Initialize the PCI library */
+	pci_scan_bus(pacc);		/* We want to get the list of devices */
+	pci_filter_init(pacc, &filter);
+
+	/* Default filter */
+	filter.vendor = PCI_VID_XILINX;
+	filter.device = PCI_PID_VFPGA;
+	
+	/* Parse arguments */
+	char c, *endptr;
+	while ((c = getopt (argc, argv, "i:s:d:")) != -1) {
+		switch (c) {
+			case 's':
+				err = pci_filter_parse_slot(&filter, optarg);
+				if (err)
+					error("Failed to parse slot: %s", err);
+				break;
+
+			case 'i':
+				err = pci_filter_parse_id(&filter, optarg);
+				if (err)
+					error("Failed to parse ID: %s", err);
+				break;
+			
+			case 'd':
+				log_setlevel(strtoul(optarg, &endptr, 10), ~0);
+				break;	
+
+			case '?':
+			default:
+				usage(argv[0]);
+		}
+	}
+
+	/* Search for fpga card */
+	pdev = pci_find_device(pacc, &filter);
+	if (!pdev)
+		error("Failed to find PCI device");
+
+	/* Get VFIO handles and details */
+	ret = vfio_init(&vc);
+	if (ret)
+		serror("Failed to initialize VFIO");
+
+	/* Initialize fpga card */
+	ret = vfpga_init2(&fpga, &vc, pdev);
+	if (ret)
+		error("Failed to initialize fpga card");
+
+	vfpga_dump(&fpga);
+
+	/* Setup scheduler */
+	cpu_set_t set = integer_to_cpuset(AFFINITY);
+
+	ret = sched_setaffinity(0, sizeof(set), &set);
+	if (ret)
+		serror("Failed to pin thread");
+
+	ret = sched_setscheduler(0, SCHED_FIFO, &(struct sched_param) { .sched_priority = PRIORITY });
+	if (ret)
+		serror("Failed to change scheduler");
+
+	for (int i = 0; i < fpga.vd.irqs[VFIO_PCI_MSI_IRQ_INDEX].count; i++) {
+		ret = kernel_irq_setaffinity(fpga.vd.msi_irqs[i], AFFINITY, NULL);
+		if (ret)
+			serror("Failed to change affinity of VFIO-MSI interrupt");
+	}
+
+	/* Start tests */
+	ret = test_intc(&fpga);
+	info("INTC Test: %s", (ret == 0) ? GRN("passed") : RED("failed"));
+
+	ret = test_xsg(&fpga, "xsg_multiply_add");
+	info("XSG Test: %s", (ret == 0) ? GRN("passed") : RED("failed"));
+
+//	ret = test_timer(&fpga);
+//	info("Timer Test: %s", (ret == 0) ? GRN("passed") : RED("failed"));
+
+//	ret = test_fifo(&fpga);
+//	info("FIFO Test: %s", (ret == 0) ? GRN("passed") : RED("failed"));
+
+	ret = test_dma(&fpga);
+	info("DMA Test: %s", (ret == 0) ? GRN("passed") : RED("failed"));
+
+//	ret = test_rtds_rtt(&fpga);
+//	info("RTDS RTT Test: %s", (ret == 0) ? GRN("passed") : RED("failed"));
+
+//	ret = test_rtds_cbuilder(&fpga);
+//	info("RTDS RTT Test: %s", (ret == 0) ? GRN("passed") : RED("failed"));
+
+	/* Start benchmarks */
+#if 0
+	ret = bench_memcpy(&fpga);
+#endif
+
+	/* Shutdown */
+	ret = vfpga_deinit2(&fpga);
+	if (ret)
+		error("Failed to de-initialize fpga card");
+
+	ret = vfio_destroy(&vc);
+	if (ret)
+		error("Failed to deinitialize VFIO module");
+
+	pci_cleanup(pacc);
+
+	return 0;
+}

src/server.c

@@ -8,18 +8,17 @@
 
 #include <stdlib.h>
 #include <string.h>
-
 #include <signal.h>
 #include <unistd.h>
-
 #include <sched.h>
 
 #include "config.h"
-#include "utils.h"
-#include "cfg.h"
-#include "path.h"
-#include "node.h"
-#include "kernel.h"
+
+#include <villas/utils.h>
+#include <villas/cfg.h>
+#include <villas/path.h>
+#include <villas/node.h>
+#include <villas/kernel/kernel.h>
 
 #ifdef ENABLE_OPAL_ASYNC
   #include "opal.h"

thirdparty/opal/README.txt

@@ -1,7 +0,0 @@
-This directory contains the libOpalAsyncApi library and
-several smaller OPAL-RT related dependencies.
-
-It's included for testing purposes.
-
-The contents of this directory are a subset of the libraries which are
-on the OPAL simulators itself at: /usr/opalrt/common/

thirdparty/opal/include_target/AsyncApi.h

@@ -1,670 +0,0 @@
-/*-------------------------------------------------------------------
- *	OPAL-RT Technologies inc
- *
- *	Copyright (C) 1999. All rights reserved.
- *
- *	File name =			$Workfile: AsyncApi.h $
- *	SourceSafe path =	$Logfile: /SIMUPAR/soft/common/include_target/AsyncApi.h $
- *	SourceSafe rev. =	$Revision: 2.14 $
- *	Last checked in =	$Date: 2009/06/04 01:39:35 $
- *	Last updated =		$Modtime: 8/14/02 3:43p $
- *	Last modified by =	$Author: irenep $
- *
- *-----------------------------------------------------------------*/
-
-/*-------------------------------------------------------------------
- *
- *  Abstract:
- *
- *-----------------------------------------------------------------*/
-
-#ifndef OPAL_ASYNC_MEM_H
-
-#define OPAL_ASYNC_MEM_H
-
-#if defined(__QNXNTO__)
-	#include <semaphore.h>
-	#include <inttypes.h>
-#endif
-#include <math.h>
-
-//typedef unsigned char byte;
-//typedef unsigned short word;
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif
-
-// NOTE : Copié du fichier OpalRtMain.h
-typedef enum
-{
-/*	0	*/	STATE_ERROR,
-/*	1	*/	STATE_PAUSE,
-/*	2	*/	STATE_LOAD,
-/*	3	*/	STATE_RUN,
-/*	4	*/	STATE_SINGLE_STEP,
-/*	5	*/	STATE_RESET,
-/*	6	*/	STATE_STOP,
-/*	7	*/	STATE_WAIT_SC
-} RUN_STATE;
-
-
-typedef enum
-{
-	OP_ASYNC_WAIT_FOR_DATA,
-	OP_ASYNC_PREPARE_DATA,
-	OP_ASYNC_DATA_READY
-} OpalAsyncStatusCode;
-
-
-/* Send icon mode actually supported */
-#define	NEED_REPLY_BEFORE_NEXT_SEND	0
-#define	NEED_REPLY_NOW				1
-#define	DONT_NEED_REPLY				2
-
-/* Define to support multi-plateforme */
-# ifndef UINT64_T
-#  if defined(__i386__) && defined(__linux__)
-#    define UINT64_T unsigned long long
-#  endif
-#  if defined(_MSC_VER)
-#    define UINT64_T unsigned __int64
-#  endif
-#  if defined(__QNXNTO__)
-#    define UINT64_T uint64_t
-#  endif
-# endif
-# ifdef UINT64_T
-#  if defined(__i386__) && defined(__linux__)
- __extension__
-#  endif
-# endif /* UINT64_T */
-
-
-/****************************************************************************************
-*
-* Name :	OpalOpenAsyncMem
-*
-* Input Parameters :
-*		sizeOfMemory :	the size in bytes of the shared memory.
-*							
-*		mem_name :		the name of shared memory.
-*
-* Output Parameters :	NIL
-*		
-* Return :	EOK		success
-*			ENOMEM	Insufficient memory available.
-*			EIO		Cannot open shared memory.
-* 
-* Description :	Open the shared memory for futur acces.
-*
-*****************************************************************************************/
-int	OpalOpenAsyncMem(int	sizeOfMemory,const char *mem_name);
-
-
-/****************************************************************************************
-*
-* Name :	OpalCloseAsyncMem
-*
-* Input Parameters :
-*		sizeOfMemory :	Size of the shared memory.
-*							
-*		mem_name :		Name of shared memory.
-*
-* Output Parameters :	NIL
-*		
-* Return :	EOK		success
-*			EIO		Cannot close shared memory.
-* 
-* Description :	Close the shared memory
-*
-*****************************************************************************************/
-int	OpalCloseAsyncMem(int	sizeOfMemory,const char *mem_name);
-
-
-/****************************************************************************************
-*
-* Name :	OpalGetNbAsyncSendIcon
-*
-* Input Parameters :	NIL
-*
-* Output Parameters :	
-*		nbIcon :	pointer to a integer variable
-*		
-* Return :	EOK		success
-* 
-* Description :	Gives the number of send icon registered to the controller.
-*
-*****************************************************************************************/
-int	OpalGetNbAsyncSendIcon(int	*nbIcon);
-
-
-/****************************************************************************************
-*
-* Name :	OpalGetNbAsyncRecvIcon
-*
-* Input Parameters :	NIL
-*
-* Output Parameters :
-*		nbIcon :	pointer to a integer variable
-*
-* Return :	EOK		success
-* 
-* Description :	Gives the number of receive icon registered to the controller.
-*
-*****************************************************************************************/
-int	OpalGetNbAsyncRecvIcon(int	*nbIcon);
-
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncCtrlParameters
-*
-* Input Parameters :
-*		size :		the size in bytes of the parameters structure.
-*
-* Output Parameters :	
-*		ParamPtr :	pointer to a parameters structure.
-*		
-* Return :	EOK		success
-*			E2BIG	size parameter are too big.
-*			ENOEXEC pointer error, version error or shmem error
-* 
-* Description :	Give all the parameters of the controller icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncCtrlParameters(void	*ParamPtr,int	size);
-
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncSendIconDataLength
-*
-* Input Parameters :	
-*		SendID	:	ID of the icon
-*
-* Output Parameters :
-*		length	:	pointer to a integer variable
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*  
-* Description :	Gives the data length of the send icon specified with SendID parameter.
-*
-*****************************************************************************************/
-int	OpalGetAsyncSendIconDataLength(int	*length, unsigned int SendID);
-
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncSendIconMode
-*
-* Input Parameters :	
-*		SendID	:	ID of the icon
-*
-* Output Parameters :
-*		mode	:	pointer to a integer variable
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*  
-* Description :	Gives the mode of the send icon specified with SendID parameter.
-*				(See at the top of this file for mode definition)
-*
-*****************************************************************************************/
-int	OpalGetAsyncSendIconMode(int	*mode, unsigned int SendID);
-
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncRecvIconDataLength
-*
-* Input Parameters :	
-*		RecvID	:	ID of the icon
-*
-* Output Parameters :
-*		length	:	pointer to a integer variable
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*  
-* Description :	Gives the data length of the recv icon specified with RecvID parameter.
-*
-*****************************************************************************************/
-int	OpalGetAsyncRecvIconDataLength(int	*length, unsigned int RecvID);
-
-
-/****************************************************************************************
-*
-* Name :	OpalWaitForAsyncSendRequest
-*
-* Input Parameters :	NIL
-*
-* Output Parameters :
-*		SendID	:	pointer to a integer variable
-*		
-* Return :	EOK		success
-*			ENODEV	No send icon registered.
-*  
-* Description :	Gives the ID of the icon who call a send request.
-*
-*****************************************************************************************/
-int	OpalWaitForAsyncSendRequest(unsigned int	*SendID);
-
-/****************************************************************************************
-*
-* Name :	OpalAsyncSendRequestDone
-*
-* Input Parameters :	
-*		SendID	:	ID of the icon
-*
-* Output Parameters :	nil
-*		
-* Return :	EOK		success
-*			ENODEV	No send icon registered.
-*			EINVAL	invalid ID
-*  
-* Description :	Reply to a specific send icon.
-*
-*****************************************************************************************/
-int	OpalAsyncSendRequestDone(unsigned int	SendID);
-
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncSendIconData
-*
-* Input Parameters :	
-*		size	:	size in bytes of the data buffer.
-*		SendID	:	ID of the icon.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the data are stored.
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*			ENODEV	no send icon registered
-*			E2BIG	size are too big.
-*  
-* Description :	Get the data for the specific send icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncSendIconData(void	*dataPtr, int size, unsigned int SendID);
-
-/****************************************************************************************
-* Name :	OpalGetSubsetAsyncSendIconData
-*
-* Input Parameters :	
-*		offset	:	offset in bytes of the data buffer to be get
-*		size	:	size in bytes of the data buffer to get.
-*		SendID	:	ID of the icon.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the data are stored.
-*		
-* Return :	EOK		succes
-*			EINVAL	invalid ID
-*			ENODEV	no send icon registered
-*			E2BIG	size are too big.
-*  
-* Description :	Get one subset of the data for the specific send icon.
-*               OpalGetSubsetAsyncSendIconData(buf,0,size,sendId) 
-*				is the same as OpalGetAsyncSendIconData(buf,size,sendId) 
-*
-*****************************************************************************************/
-
-int OpalGetSubsetAsyncSendIconData(double *dataPtr, int offset, int size, unsigned int SendID);
-
-
-
-
-/****************************************************************************************
-*
-* Name :	OpalSetAsyncRecvIconData
-*
-* Input Parameters :	
-*		size	:	size in bytes of the data buffer.
-*		RecvID	:	ID of the icon.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the data are stored.
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*			ENODEV	no send icon registered
-*			E2BIG	size are too big.
-*  
-* Description :	Set the data for the specific recv icon.
-*
-*****************************************************************************************/
-int	OpalSetAsyncRecvIconData(void	*dataPtr, int size, unsigned int RecvID);
-
-/****************************************************************************************
-*
-* Name :	OpalSetSubsetAsyncRecvIconData
-*
-* Input Parameters :	
-*		offset	:	offset in bytes of the data buffer to be set
-*		size	:	size in bytes of the data buffer.to be set
-*		RecvID	:	ID of the icon.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the data are stored.
-*		
-* Return :	EOK		succes
-*			EINVAL	invalid ID
-*			ENODEV	no send icon registered
-*			E2BIG	size are too big.
-*  
-* Description :	Set one subset of the data for the specific recv icon.
-*               OpalSetSubsetAsyncRecvIconData(buf,0,size,recvId) 
-*				is the same as OpalSetAsyncRecvIconData(buf,size,recvId) 
-*
-*****************************************************************************************/
-int	OpalSetSubsetAsyncRecvIconData(double *dataPtr,int offset,int size, unsigned int RecvID);
-
-
-/****************************************************************************************
-*
-* Name :	OpalSetAsyncSendIconError
-*
-* Input Parameters :	
-*		Error	:	error code returned to the send icon.
-*		SendID	:	ID of the icon.
-*
-* Output Parameters :	NIL
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*			ENODEV	no send icon registered
-*  
-* Description :	Set the error code for the specific send icon.
-*
-*****************************************************************************************/
-int	OpalSetAsyncSendIconError(double Error, unsigned int SendID);
-
-
-/****************************************************************************************
-*
-* Name :	OpalSetAsyncRecvIconError
-*
-* Input Parameters :	
-*		Error	:	error code returned to the receive icon.
-*		RecvID	:	ID of the icon.
-*
-* Output Parameters :	NIL
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*			ENODEV	no receive icon registered
-*  
-* Description :	Set the error code for the specific receive icon.
-*
-*****************************************************************************************/
-int	OpalSetAsyncRecvIconError(double Error, unsigned int RecvID);
-
-
-/****************************************************************************************
-*
-* Name :	OpalSetAsyncRecvIconStatus
-*
-* Input Parameters :	
-*		Status	:	status code returned to the recveive icon.
-*		RecvID	:	ID of the icon.
-*
-* Output Parameters :	NIL
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*			ENODEV	no receive icon registered
-*  
-* Description :	Set the status code for the specific receive icon.
-*
-*****************************************************************************************/
-int	OpalSetAsyncRecvIconStatus(double Status, unsigned int RecvID);
-
-/****************************************************************************************
-*
-* Name :	OpalSetAsyncRecvIconStatus
-*
-* Input Parameters :	
-*		Status	:	status code returned to the recveive icon.
-*		RecvID	:	ID of the icon.
-*
-* Output Parameters :	NIL
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*			ENODEV	no receive icon registered
-*  
-* Description :	Set the status code for the specific receive icon.
-*
-*****************************************************************************************/
-int	OpalSetAsyncRecvIconStatusMult(double Status, unsigned int RecvID);
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncRecvIconTimeout
-*
-* Input Parameters :	
-*		RecvID	:	ID of the icon.
-*
-* Output Parameters :
-*		timeout	:	pointer to a double.
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*			ENODEV	no recv icon registered
-*  
-* Description :	Get the timout for the specific receive icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncRecvIconTimeout(double	*timeout, unsigned int RecvID);
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncSendIDList
-*
-* Input Parameters :	
-*		size	:	size in bytes of the data buffer.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the data are stored.
-*		
-* Return :	EOK		success
-*			ENODEV	no send icon registered
-*			E2BIG	invalid size.
-*  
-* Description :	Get the ID list of all Send icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncSendIDList(void	*dataPtr, int size);
-
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncRecvIDList
-*
-* Input Parameters :	
-*		size	:	size in bytes of the data buffer.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the data are stored.
-*		
-* Return :	EOK		success
-*			ENODEV	no Recv icon registered
-*			E2BIG	invalid size.
-*  
-* Description :	Get the ID list of all Recv icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncRecvIDList(void	*dataPtr, int size);
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncSendParameters
-*
-* Input Parameters :	
-*		size	:	size in bytes of the data buffer.
-*		SendID	:	ID of the icon.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the data are stored.
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*			ENODEV	no send icon registered
-*  
-* Description :	Get all parameters of the specific Send icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncSendParameters(void	*dataPtr, int size, unsigned int SendID);
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncSendExtFloatParameters
-*
-* Input Parameters :	
-*		size	:	size in bytes of the data buffer.
-*		SendID	:	ID of the icon.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the exterended is to be stored.
-*		
-* Return :	number of parameters
-*  
-* Description :	Get all extended parameters of the specific Send icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncSendExtFloatParameters(void	*dataPtr, int size, unsigned int SendID);
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncRecvParameters
-*
-* Input Parameters :	
-*		size	:	size in bytes of the data buffer.
-*		RecvID	:	ID of the icon.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the data are stored.
-*		
-* Return :	EOK		success
-*			EINVAL	invalid ID
-*			ENODEV	no send icon registered
-*  
-* Description :	Get all parameters of the specific Recv icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncRecvParameters(void	*dataPtr, int size, unsigned int RecvID);
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncRecvExtFloatParameters
-*
-* Input Parameters :	
-*		size	:	size in bytes of the data buffer.
-*		SendID	:	ID of the icon.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the exterended is to be stored.
-*		
-* Return :	number of parameters
-*  
-* Description :	Get all extended parameters of the specific recv icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncRecvExtFloatParameters(void	*dataPtr, int size, unsigned int RecvID);
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncCtrlExtFloatParameters
-*
-* Input Parameters :	
-*		size	:	size in bytes of the data buffer.
-*		SendID	:	ID of the icon.
-*
-* Output Parameters :
-*		dataPtr	:	pointer where the exterended is to be stored.
-*		
-* Return :	number of parameters
-*  
-* Description :	Get all extended parameters of the specific ctrl icon.
-*
-*****************************************************************************************/
-int	OpalGetAsyncCtrlExtFloatParameters(void	*dataPtr, int size);
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncModelState 
-*
-* Input Parameters :	NIL
-*
-* Output Parameters :	NIL
-*		
-* Return :		STATE_ERROR			
-*				STATE_PAUSE			
-*				STATE_LOAD			
-*				STATE_RUN			
-*				STATE_SINGLE_STEP	
-*				STATE_RESET			
-*				STATE_STOP			
-*				STATE_WAIT_SC		
-*  
-* Description :	Returns the state of the model
-*
-*****************************************************************************************/
-int OpalGetAsyncModelState (void);
-
-// RT is defined coz these prototypes are reuired only on target site
-// and long long are not supported on Windows
-#if defined(RT)
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncStartExecCpuTime 
-*
-* Input Parameters :	NIL
-*
-* Output Parameters :	NIL
-*		
-* Return :		
-* Description :	This function returns the cuurent CPU time counter read at start of execution
-*
-*****************************************************************************************/
-int OpalGetAsyncStartExecCpuTime( void * ParamPtr, UINT64_T * time );
-
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncStartPauseCpuTime 
-*
-* Input Parameters :	NIL
-*
-* Output Parameters :	NIL
-*		
-* Return :		
-* Description :	This function returns the cuurent CPU time counter read at start of execution
-*
-*****************************************************************************************/
-int OpalGetAsyncStartPauseCpuTime( void * ParamPtr, UINT64_T * time );
-/****************************************************************************************
-*
-* Name :	OpalGetAsyncModelTime
-*
-* Input Parameters :	NIL
-*
-* Output Parameters :	NIL
-*		
-* Return :		
-* Description :	This function get a CPU time close to model sync, and the current modelTime
-*
-*****************************************************************************************/
-int OpalGetAsyncModelTime( void * ParamPtr, unsigned long long * CPUtime, double * modelTime);
-#endif
-
-unsigned atoh (const char * ptr);
-unsigned ascii_to_hexa (char * str);
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif  // #ifndef OPAL_ASYNC_MEM_H
-

thirdparty/opal/include_target/OpalGenAsyncParamCtrl.h

@@ -1,96 +0,0 @@
-/*-------------------------------------------------------------------
- *	OPAL-RT Technologies inc
- *
- *	Copyright (C) 1999. All rights reserved.
- *
- *	File name =			$Workfile: OpalGenAsyncParamCtrl.h $
- *	SourceSafe path =	$Logfile: /SIMUPAR/soft/common/include_target/OpalGenAsyncParamCtrl.h $
- *	SourceSafe rev. =	$Revision: 2.8 $
- *	Last checked in =	$Date: 2009/12/15 14:42:27 $
- *	Last updated =		$Modtime: 7/31/02 10:25a $
- *	Last modified by =	$Author: AntoineKeirsbulck $
- *
- *-----------------------------------------------------------------*/
-
-/*-------------------------------------------------------------------
- *
- *  Abstract:
- *
- *-----------------------------------------------------------------*/
-
-#include "OpalTypes.h"
-
-#ifndef OPAL_GENASYCPARAM_CTRL_H
-#define OPAL_GENASYCPARAM_CTRL_H
-
-#define	SENDASYNC_NB_FLOAT_PARAM		5
-#define	SENDASYNC_NB_STRING_PARAM		5
-#define	SENDASYNC_MAX_STRING_LENGTH		1000
-
-#define	RECVASYNC_NB_FLOAT_PARAM		5
-#define	RECVASYNC_NB_STRING_PARAM		5
-#define	RECVASYNC_MAX_STRING_LENGTH		1000
-
-#define	GENASYNC_NB_FLOAT_PARAM			12
-#define	GENASYNC_NB_STRING_PARAM		12
-#define	GENASYNC_MAX_STRING_LENGTH		1000
-
-
-// Align bytes
-#if defined(__GNUC__)
-#	undef	GNUPACK
-#	define	GNUPACK(x)		__attribute__ ((aligned(x),packed))
-#else
-#	undef	GNUPACK
-#	define	GNUPACK(x)
-#	if defined(__sgi)
-#		pragma pack(1)
-#	else
-#		pragma pack (push, 1)
-#	endif
-#endif
-
-
-//------------ LocalData ---------------
-typedef struct
-{
-	unsigned char	controllerID														;// ignored GNUPACK(1);
-	double			FloatParam[GENASYNC_NB_FLOAT_PARAM]									GNUPACK(1);
-	char			StringParam[GENASYNC_NB_STRING_PARAM][GENASYNC_MAX_STRING_LENGTH]	;// ignored GNUPACK(1);
-	UINT64_T		execStartCpuTime													GNUPACK(1);
-	UINT64_T		pauseStartCpuTime													GNUPACK(1);
-#ifdef RT
-	unsigned long long	modelSyncCpuTime												GNUPACK(1);
-#else
-	UINT64_T		modelSyncCpuTime													GNUPACK(1);
-#endif
-	double			modelTime															GNUPACK(1);
-
-} Opal_GenAsyncParam_Ctrl;
-
-
-typedef struct
-{
-	double			FloatParam[SENDASYNC_NB_FLOAT_PARAM]								GNUPACK(1);
-	char			StringParam[SENDASYNC_NB_STRING_PARAM][SENDASYNC_MAX_STRING_LENGTH]	;// ignored GNUPACK(1);
-
-} Opal_SendAsyncParam;
-
-typedef struct
-{
-	double			FloatParam[RECVASYNC_NB_FLOAT_PARAM]								GNUPACK(1);
-	char			StringParam[RECVASYNC_NB_STRING_PARAM][RECVASYNC_MAX_STRING_LENGTH]	;// ignored GNUPACK(1);
-
-} Opal_RecvAsyncParam;
-
-#if defined(__GNUC__)
-#	undef	GNUPACK
-#else
-#	if defined(__sgi)
-#		pragma pack(0)
-#	else
-#		pragma pack (pop)
-#	endif
-#endif
-
-#endif  // #ifndef OPAL_GENASYCPARAM_CTRL_H

thirdparty/opal/include_target/OpalPrint.h

@@ -1,110 +0,0 @@
-/*-------------------------------------------------------------------
- *	OPAL-RT Technologies inc
- *
- *	Copyright (C) 1999. All rights reserved.
- *
- *	File name =			$Workfile: OpalPrint.h $
- *	SourceSafe path =	$Logfile: /SIMUPAR/soft/common/include_target/OpalPrint.h $
- *	SourceSafe rev. =	$Revision: 2.3 $
- *	Last checked in =	$Date: 2004/08/13 19:35:48 $
- *	Last updated =		$Modtime: 03-10-14 16:58 $Author: djibriln $
- *
- *-----------------------------------------------------------------*/
-
-#ifndef OPALPRINT_H
-#define OPALPRINT_H
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif
-
-#if defined (RTLAB) && !defined(IS_COMPILED_IN_CONTROLLER)  && !defined(IS_COMPILED_IN_METACONTROLLER)
-	int	OpalPrint(const char *format, ... );
-#else
-	#define OpalPrint printf
-#endif
-
-
-	/****************************************************************************************
-	*
-	* Name :	OpalSystemCtrl_Register
-	*
-	* Input Parameters :
-	*		sysShMemName :	The name of shared memory.
-	*							
-	* Output Parameters :	NIL
-	*		
-	* Return :	EOK		Succes
-	*			-1		Cannot open shared memory.
-	* 
-	* Description :	Enable the OpalPrint function to send message via the OpalDisplay by opening a shared memory.
-	*
-	*		NOTE:	RTLAB must be defined before including this file (OpalPrint.h)
-	*
-	*****************************************************************************************/	
-	int	OpalSystemCtrl_Register(char *sysShMemName); 
-
-	/****************************************************************************************
-	*
-	* Name :	OpalSystemCtrl_UnRegister
-	*
-	* Input Parameters :
-	*		sysShMemName :	The name of shared memory.
-	*							
-	* Output Parameters :	NIL
-	*		
-	* Return :	EOK		Succes
-	* 
-	* Description :	Close the OpalPrint shared memory.
-	*
-	*		NOTE:	RTLAB must be defined before including this file (OpalPrint.h)
-	*
-	*****************************************************************************************/	
-	int OpalSystemCtrl_UnRegister(char *sysMemName);
-
-
-	/****************************************************************************************
-	*
-	* Name :	OpalSendFileName
-	*
-	* Input Parameters :
-	*		fileName :	Name of the file to be retrieved on reset
-	*		fileMode :  Specify 'a' for "Ascii", 'b' for "Binary"
-	*		fileType :  Set to 0. For internal use only.
-	*							
-	* Output Parameters :	NIL
-	*		
-	* Return :	EOK		Succes
-	* 
-	* Description :	Sends the name and type of a file so that RT-LAB retrieves it on reset.
-	*
-	*		NOTE:	RTLAB must be defined before including this file (OpalPrint.h)
-	*
-	*****************************************************************************************/	
-	int	OpalSendFileName(char *fileName, char fileMode, int fileType);
-
-	/****************************************************************************************
-	*
-	* Name :	OpalSendClosedFileName
-	*
-	* Input Parameters :
-	*		fileName :	Name of the file to be retrieved
-	*
-	* Output Parameters :	NIL
-	*
-	* Return :	EOK		Succes
-	*
-	* Description :	Sends the name of a file ready to be retrieved.
-	*
-	*		NOTE:	RTLAB must be defined before including this file (OpalPrint.h)
-	*
-	*****************************************************************************************/
-	int	OpalSendClosedFileName(char *fileName);
-
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif

thirdparty/opal/include_target/OpalTypes.h

@@ -1,734 +0,0 @@
-/*-------------------------------------------------------------------
- *	OPAL-RT Technologies inc
- *
- *	Copyright (C) 1999. All rights reserved.
-
- *	File name =			$RCSfile: OpalTypes.h,v $
- *	CVS  path =			$Source: /git/RT-LAB/RT-LAB/soft/common/include_target/OpalTypes.h,v $
- *	CVS  rev. =			$Revision: 1.8 $
- *	Last checked in =	$Date: 2010/07/07 15:53:08 $
- *	Last modified by =	$Author: AntoineKeirsbulck $
- *
- *-----------------------------------------------------------------*/
-
-/*-------------------------------------------------------------------
- *
- *  Abstract:
- *      Data types for use with MATLAB/SIMULINK and the Real-Time Workshop.
- *      Data types for use with XMATH/SYSTEMBUILD and AutoCode.
- *
- *      When compiling stand-alone model code, data types can be overridden
- *      via compiler switches.
- *
- *-----------------------------------------------------------------*/
-
-#ifndef __OPALTYPES__
-#define __OPALTYPES__
-
-#ifdef _WIN32
-	#ifndef WIN32
-	#define WIN32
-	#endif
-#endif
-
-#if defined(__QNXNTO__)
-#	include <inttypes.h>
-#endif
-
-/* =========================================================================
-	MATLAB
-	Inclure les types de tmwtypes.h (de Matlab) seulement si ce dernier
-	n'a pas déjà été inclus, sinon on a des erreurs de redefinition
-	avec gcc. Tous ce qui est inclus entre le #if qui suit et le #endif
-	correspondant est une copie du contenu de tmwtypes.h. Pour inclure
-	d'autre types, s'assurer de les mettre en dehors de la région délimitée
-	par ces #if __TMWTYPES__ / #endif
-*/
-#if ! defined(__TMWTYPES__)
-#include <limits.h>
-
-#ifndef __MWERKS__
-# ifdef __STDC__
-#  include <float.h>
-# else
-#  define FLT_MANT_DIG 24
-#  define DBL_MANT_DIG 53
-# endif
-#endif
-
-/*
- *      The following data types cannot be overridden when building MEX files.
- */
-#ifdef MATLAB_MEX_FILE
-# undef CHARACTER_T
-# undef INTEGER_T
-# undef BOOLEAN_T
-# undef REAL_T
-# undef TIME_T
-#endif
-
-/*
- *      The following define is used to emulate when all integer types are
- *      32-bits.  This is the case for TI C30/C40 DSPs which are RTW targets.
- */
-#ifdef DSP32
-# define INT8_T    int
-# define UINT8_T   unsigned int
-# define INT16_T   int
-# define UINT16_T  unsigned int
-#endif
-
-/*
- * The uchar_T, ushort_T and ulong_T types are needed for compilers which do
- * not allow defines to be specified, at the command line, with spaces in them.
- */
-
-typedef unsigned char  uchar_T;
-typedef unsigned short ushort_T;
-typedef unsigned long  ulong_T;
-
-
-
-/*=======================================================================*
- * Fixed width word size data types:                                     *
- *   int8_T, int16_T, int32_T     - signed 8, 16, or 32 bit integers     *
- *   uint8_T, uint16_T, uint32_T  - unsigned 8, 16, or 32 bit integers   *
- *   real32_T, real64_T           - 32 and 64 bit floating point numbers *
- *=======================================================================*/
-
-#ifndef INT8_T
-# if CHAR_MIN == -128
-#   define INT8_T char
-# elif SCHAR_MIN == -128
-#   define INT8_T signed char
-# endif
-#endif
-#ifdef INT8_T
-  typedef INT8_T int8_T;
-# ifndef UINT8_T
-#   define UINT8_T unsigned char
-# endif
-  typedef UINT8_T uint8_T;
-#endif
-
-
-#ifndef INT16_T
-# if SHRT_MAX == 0x7FFF
-#  define INT16_T short
-# elif INT_MAX == 0x7FFF
-#  define INT16_T int
-# endif
-#endif
-#ifdef INT16_T
- typedef INT16_T int16_T;
-#endif
-
-
-#ifndef UINT16_T
-# if SHRT_MAX == 0x7FFF    /* can't compare with USHRT_MAX on some platforms */
-#  define UINT16_T unsigned short
-# elif INT_MAX == 0x7FFF
-#  define UINT16_T unsigned int
-# endif
-#endif
-#ifdef UINT16_T
-  typedef UINT16_T uint16_T;
-#endif
-
-
-#ifndef INT32_T
-# if INT_MAX == 0x7FFFFFFF
-#  define INT32_T int
-# elif LONG_MAX == 0x7FFFFFFF
-#  define INT32_T long
-# endif
-#endif
-#ifdef INT32_T
- typedef INT32_T int32_T;
-#endif
-
-
-#ifndef UINT32_T
-# if INT_MAX == 0x7FFFFFFF
-#  define UINT32_T unsigned int
-# elif LONG_MAX == 0x7FFFFFFF
-#  define UINT32_T unsigned long
-# endif
-#endif
-#ifdef UINT32_T
- typedef UINT32_T uint32_T;
-#endif
-
-
-#ifndef REAL32_T
-# ifndef __MWERKS__
-#  if FLT_MANT_DIG >= 23
-#    define REAL32_T float
-#  endif
-# else
-#    define REAL32_T float
-# endif
-#endif
-#ifdef REAL32_T
-typedef REAL32_T real32_T;
-#endif
-
-#ifndef REAL64_T
-# ifndef __MWERKS__
-#  if DBL_MANT_DIG >= 52
-#    define REAL64_T double
-#  endif
-# else
-#    define REAL64_T double
-# endif
-#endif
-#ifdef REAL64_T
-  typedef REAL64_T real64_T;
-#endif
-
-/*=======================================================================*
- * Fixed width word size data types:                                     *
- *   int64_T                      - signed 64 bit integers               *
- *   uint64_T                     - unsigned 64 bit integers             *
- *=======================================================================*/
-
-#ifndef INT64_T
-# if defined(__alpha) || (defined(_MIPS_SZLONG) && (_MIPS_SZLONG == 64))
-#   define INT64_T long
-#   define FMT64 ""
-# endif
-# if defined(__LP64__)
-#   define INT64_T long
-#   define FMT64 "L"
-# endif
-# if defined(__i386__) && defined(__linux__)
-#   define INT64_T long long
-#   define FMT64 "L"
-# endif
-# if defined(_MSC_VER)
-#   define INT64_T __int64
-#   define FMT64 "I64"
-# endif
-# if defined(__QNXNTO__)
-#   define INT64_T int64_t
-#  endif
-#endif
-#ifdef INT64_T
-# if defined(__i386__) && defined(__linux__)
- __extension__
-# endif
- typedef INT64_T int64_T;
-#endif
-
-
-#ifndef UINT64_T
-# if defined(__alpha) || (defined(_MIPS_SZLONG) && (_MIPS_SZLONG == 64))
-#   define UINT64_T unsigned long
-# endif
-# if defined(__LP64__)
-#   define UINT64_T unsigned long
-# endif
-# if defined(__i386__) && defined(__linux__)
-#   define UINT64_T unsigned long long
-# endif
-# if defined(_MSC_VER)
-#   define UINT64_T unsigned __int64
-# endif
-# if defined(__QNXNTO__)
-#   define UINT64_T uint64_t
-#endif
-#endif
-#ifdef UINT64_T
-# if defined(__i386__) && defined(__linux__)
- __extension__
-# endif
- typedef UINT64_T uint64_T;
-#endif
-
-
-/*================================================================*
- *  Fixed-point data types:                                       *
- *     fixpoint_T     - 16 or 32-bit unsigned integers            *
- *     sgn_fixpoint_T - 16 or 32-bit signed integers              *
- *  Note, when building fixed-point applications, real_T is equal *
- *  to fixpoint_T and time_T is a 32-bit unsigned integer.        *
- *================================================================*/
-
-#ifndef FIXPTWS
-# define FIXPTWS 32
-#endif
-#if FIXPTWS != 16 && FIXPTWS != 32
-  "--> fixed-point word size (FIXPTWS) must be 16 or 32 bits"
-#endif
-
-#if FIXPTWS == 16
-  typedef uint16_T fixpoint_T;
-  typedef int16_T  sgn_fixpoint_T;
-#else
-  typedef uint32_T fixpoint_T;
-  typedef int32_T  sgn_fixpoint_T;
-#endif
-
-#ifdef FIXPT
-# define REAL_T fixpoint_T
-# define TIME_T uint32_T
-#endif
-
-
-
-/*===========================================================================*
- * General or logical data types where the word size is not guaranteed.      *
- *  real_T     - possible settings include real32_T, real64_T, or fixpoint_T *
- *  time_T     - possible settings include real64_T or uint32_T              *
- *  boolean_T                                                                *
- *  char_T                                                                   *
- *  int_T                                                                    *
- *  uint_T                                                                   *
- *  byte_T                                                                   *
- *===========================================================================*/
-
-#ifndef REAL_T
-# ifdef REAL64_T
-#   define REAL_T real64_T
-# else
-#   ifdef REAL32_T
-#     define REAL_T real32_T
-#   endif
-# endif
-#endif
-#ifdef REAL_T
-  typedef REAL_T real_T;
-#endif
-
-#ifndef TIME_T
-#  ifdef REAL_T
-#    define TIME_T real_T
-#  endif
-#endif
-#ifdef TIME_T
-  typedef TIME_T time_T;
-#endif
-
-#ifndef BOOLEAN_T
-# if defined(UINT8_T)
-#   define BOOLEAN_T UINT8_T
-# else
-#   define BOOLEAN_T unsigned int
-# endif
-#endif
-typedef BOOLEAN_T boolean_T;
-
-
-#ifndef CHARACTER_T
-#define CHARACTER_T char
-#endif
-typedef CHARACTER_T char_T;
-
-
-#ifndef INTEGER_T
-#define INTEGER_T int
-#endif
-typedef INTEGER_T int_T;
-
-
-#ifndef UINTEGER_T
-#define UINTEGER_T unsigned
-#endif
-typedef UINTEGER_T uint_T;
-
-
-#ifndef BYTE_T
-#define BYTE_T unsigned char
-#endif
-typedef BYTE_T byte_T;
-
-
-/*===========================================================================*
- * Define Complex Structures                                                 *
- *===========================================================================*/
-
-#ifndef CREAL32_T
-#  ifdef REAL32_T
-    typedef struct {
-      real32_T re, im;
-    } creal32_T;
-#    define CREAL32_T creal32_T
-#  endif
-#endif
-
-#ifndef CREAL64_T
-#  ifdef REAL64_T
-    typedef struct {
-      real64_T re, im;
-    } creal64_T;
-#    define CREAL64_T creal64_T
-#  endif
-#endif
-
-#ifndef CREAL_T
-#  ifdef REAL_T
-    typedef struct {
-      real_T re, im;
-    } creal_T;
-#    define CREAL_T creal_T
-#  endif
-#endif
-
-#ifndef CINT8_T
-#  ifdef INT8_T
-    typedef struct {
-      int8_T re, im;
-    } cint8_T;
-#    define CINT8_T cint8_T
-#  endif
-#endif
-
-#ifndef CUINT8_T
-#  ifdef UINT8_T
-    typedef struct {
-      uint8_T re, im;
-    } cuint8_T;
-#    define CUINT8_T cuint8_T
-#  endif
-#endif
-
-#ifndef CINT16_T
-#  ifdef INT16_T
-    typedef struct {
-      int16_T re, im;
-    } cint16_T;
-#    define CINT16_T cint16_T
-#  endif
-#endif
-
-#ifndef CUINT16_T
-#  ifdef UINT16_T
-    typedef struct {
-      uint16_T re, im;
-    } cuint16_T;
-#    define CUINT16_T cuint16_T
-#  endif
-#endif
-
-#ifndef CINT32_T
-#  ifdef INT32_T
-    typedef struct {
-      int32_T re, im;
-    } cint32_T;
-#    define CINT32_T cint32_T
-#  endif
-#endif
-
-#ifndef CUINT32_T
-#  ifdef UINT32_T
-    typedef struct {
-      uint32_T re, im;
-    } cuint32_T;
-#    define CUINT32_T cuint32_T
-#  endif
-#endif
-
-#else /* defined(__TMWTYPES__) */
-
-#ifdef OP_MATLABR12
-
-#ifndef INT64_T
-# if defined(__alpha) || (defined(_MIPS_SZLONG) && (_MIPS_SZLONG == 64))
-#   define INT64_T long
-#   define FMT64 ""
-# endif
-# if defined(__LP64__)
-#   define INT64_T long
-#   define FMT64 "L"
-# endif
-# if defined(__i386__) && defined(__linux__)
-#   define INT64_T long long
-#   define FMT64 "L"
-# endif
-# if defined(_MSC_VER)
-#   define INT64_T __int64
-#   define FMT64 "I64"
-# endif
-# if defined(__QNXNTO__)
-#   define INT64_T int64_t
-#  endif
-#endif
-#ifdef INT64_T
-# if defined(__i386__) && defined(__linux__)
- __extension__
-# endif
- typedef INT64_T int64_T;
-#endif
-
-# ifndef UINT64_T
-#  if defined(__alpha) || (defined(_MIPS_SZLONG) && (_MIPS_SZLONG == 64))
-#    define UINT64_T unsigned long
-#  endif
-# if defined(__LP64__)
-#   define UINT64_T unsigned long
-# endif
-#  if defined(__i386__) && defined(__linux__)
-#    define UINT64_T unsigned long long
-#  endif
-#  if defined(_MSC_VER)
-#    define UINT64_T unsigned __int64
-#  endif
-#  if defined(__QNXNTO__)
-#    define UINT64_T uint64_t
-#  endif
-# endif
-# ifdef UINT64_T
-#  if defined(__i386__) && defined(__linux__)
- __extension__
-#  endif
-typedef UINT64_T uint64_T;
-# endif /* UINT64_T */
-#endif /* OP_MATLABR12 */
-
-#endif /* ! defined(_	__) */
-/*
-  MATLAB
-  ===========================================================================
-*/
-
-/*=======================================================================*
- * Min and Max:                                                          *
- *   int8_T, int16_T, int32_T     - signed 8, 16, or 32 bit integers     *
- *   uint8_T, uint16_T, uint32_T  - unsigned 8, 16, or 32 bit integers   *
- *=======================================================================*/
-
-#define  OP_MAX_int8_T      ((int8_T)(127))            /* 127  */
-#define  OP_MIN_int8_T      ((int8_T)(-128))           /* -128 */
-#define  OP_MAX_uint8_T     ((uint8_T)(255))           /* 255  */
-#define  OP_MIN_uint8_T     ((uint8_T)(0))
-
-#define  OP_MAX_int16_T     ((int16_T)(32767))         /* 32767 */
-#define  OP_MIN_int16_T     ((int16_T)(-32768))        /* -32768 */
-#define  OP_MAX_uint16_T    ((uint16_T)(65535))        /* 65535 */
-#define  OP_MIN_uint16_T    ((uint16_T)(0))
-
-#define  OP_MAX_int32_T     ((int32_T)(2147483647))    /* 2147483647  */
-#define  OP_MIN_int32_T     ((int32_T)(-2147483647-1)) /* -2147483648 */
-#define  OP_MAX_uint32_T    ((uint32_T)(0xFFFFFFFFU))  /* 4294967295  */
-#define  OP_MIN_uint32_T    ((uint32_T)(0))
-
-#ifdef INT64_T
-#define  OP_MAX_int64_T     ((int64_T)(9223372036854775807))
-#define  OP_MIN_int64_T     ((int64_T)(-9223372036854775807-1))
-#endif
-#ifdef UINT64_T
-#define  OP_MAX_uint64_T    ((uint64_T)(0xFFFFFFFFFFFFFFFFULL))
-#define  OP_MIN_uint64_T    ((uint64_T)(0))
-#endif
-
-/*
-*
-*	Equivalent type between SIMULINK and SYSTEMBUILD
-*
-*/
-#ifndef _SA_TYPES
-#define _SA_TYPES
-	typedef	real_T		RT_FLOAT;
-	typedef int_T		RT_INTEGER;
-	typedef boolean_T	RT_BOOLEAN;
-	typedef time_T		RT_DURATION;
-#endif	/* _SA_TYPES */
-
-
-#ifndef FALSE
-	#define FALSE       0
-#endif
-#ifndef TRUE
-	#define TRUE        1
-#endif
-
-
-#ifdef INT64_T
-#	if ! defined(LONGLONG_MAX)
-#		define LONGLONG_MAX		OP_MAX_int64_T
-#	endif
-#	if ! defined(LONGLONG_MIN)
-#		define LONGLONG_MIN		OP_MIN_int64_T
-#	endif
-#endif
-#ifdef UINT64_T
-#	if ! defined(ULONGLONG_MAX)
-#		define ULONGLONG_MAX	OP_MAX_uint64_T
-#	endif
-#endif
-
-
-// Some define for partability
-#if defined(WIN32)	/* =============================================================== */
-
-	typedef unsigned int		pid_t;
-	typedef int					pthread_t;
-#	ifndef PATH_MAX
-#		define PATH_MAX (MAX_PATH)
-#	endif
-#	define OP_SLEEP( msec )		Sleep( msec )
-#	define pthread_self			GetCurrentThreadId
-#	define vsnprintf			_vsnprintf
-#	define snprintf				_snprintf
-#	define FILE_ALL_RW_PERMS	(_S_IWRITE | _S_IREAD)
-
-#elif defined(__QNX__)	/* =========================================================== */
-
-#	if ! defined(_IEEE1394_H_)
-	typedef int				HANDLE;
-#	endif /*  ! _IEEE1394_H_ */
-	typedef int				HMODULE;
-
-#	if defined(__QNXNTO__)
-
-#		define _MAX_PATH	(PATH_MAX)
-//#ifndef _strdup
-//#		define _strdup(s)	strdup(s)
-//#endif
-#		define _strlwr(s)	strlwr(s)
-
-#	else /*  ! __QNXNTO  */
-
-		typedef int				pthread_t;
-#		define pthread_self		getpid
-
-#	endif /* __QNXNTO__  */
-
-#	define MAX_PATH (PATH_MAX)
-#	define OP_SLEEP( msec )		delay( msec )
-//#	define _getcwd(b,l)			getcwd(b,l)
-
-#	define FILE_ALL_RW_PERMS	(S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH)
-
-
-#elif defined(__linux__)	/* ======================================================= */
-
-	typedef int				HANDLE;
-	typedef int				HMODULE;
-#	define MAX_PATH (PATH_MAX)
-#	define _MAX_PATH (PATH_MAX)
-
-#	include <sys/time.h>
-#	define OP_SLEEP( msec )						\
-	{	struct timeval tv;						\
-		tv.tv_sec = (msec) / 1000;				\
-		tv.tv_usec = ((msec) % 1000) * 1000;	\
-		select(0, NULL, NULL, NULL, &tv);		\
-	}
-
-//#ifndef _strdup
-//#	define _strdup(s)			strdup(s)
-//#endif
-//#	define _getcwd(b,l)			getcwd(b,l)
-//#	define _access(s1,s2)		access(s1,s2)
-//#	define _alloca(s)			alloca(s)
-//#	define _mkdir(s)			mkdir(s)
-#	define stricmp(s1,s2)		strcasecmp(s1,s2)
-#	define strnicmp(s1,s2,n)	strncasecmp(s1,s2,n)
-#	define FILE_ALL_RW_PERMS	(S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH)
-
-#elif defined(__sun__) || defined(__sgi)
-	typedef int HANDLE;
-	typedef int	HMODULE;
-#	define MAX_PATH (PATH_MAX)
-#	define _MAX_PATH (PATH_MAX)
-
-#	define	stricmp(s1, s2)			strcasecmp(s1, s2)
-#	define	strnicmp(s1, s2, len)	strncasecmp(s1, s2, len)
-//#	define	_strdup(s)				strdup(s)
-//#	define _getcwd(b,l)				getcwd(b,l)
-//#	define _alloca(s)				alloca(s)
-
-#endif /*  WIN32  /  __QNX__  /  __linux__  //  __sun__  // __sgi  //======================================= */
-
-//#ifndef WIN32
-//#include <string.h>
-//#include <strings.h>
-//#include <sys/stat.h>
-//#include <unistd.h>
-
-//#ifdef _strdup
-//#undef _strdup
-//#warning _strdup should not be #defined!
-//#endif
-//
-//# ifndef __QNX__
-//	static inline int stricmp(char const * s1, char const *s2) {
-//		return strcasecmp(s1,s2);
-//	}
-//	static inline int strnicmp(char const * s1, char const *s2, size_t l) {
-//		return strncasecmp(s1,s2,l);
-//	}
-//// QDT: Not possible due o libOpalCore and libOpalOhci depending on each other
-////	static inline int _stricmp(char const * s1, char const *s2) {
-////		return strcasecmp(s1,s2);
-////	}
-//#  ifndef _stricmp
-//#	define _stricmp stricmp
-//#  endif
-//	static inline int _strnicmp(char const * s1, char const *s2, size_t l) {
-//		return strncasecmp(s1,s2,l);
-//	}
-//	static inline char * _strdup(const char * s) {
-//		return strdup(s);
-//	}
-////	static inline void * _alloca(size_t size) {
-////		return alloca(size);
-////	}
-//# endif
-//	static inline pid_t _getpid() {
-//		return getpid();
-//	}
-//	static inline char * _getcwd(char * buffer, size_t size) {
-//		return getcwd(buffer, size);
-//	}
-//	static inline int _mkdir(const char *path, mode_t mode) {
-//		return mkdir(path, mode);
-//	}
-//	static inline int _access(const char *pathname, int mode) {
-//		return access(pathname, mode);
-//	}
-//	static inline int _close(int fildes) {
-//		return close(fildes);
-//	}
-//#endif
-
-typedef struct
-{
-	union
-	{
-		struct { unsigned char s_b1,s_b2,s_b3,s_b4; } S_un_b;
-		uint32_T	S_addr;
-	} S_un;
-} OP_IN_ADDR;
-
-
-typedef enum
-{
-	TR_PRIORITY_NORMAL = 0,
-	TR_PRIORITY_HIGH,
-	TR_MAX_PRIORITY
-
-}	TR_PRIORITY;
-
-#define ROUND_ST(x)	(int)((x)+0.5)
-#define FLOAT_EQU(x,y) (((((x)-(y)) >= 0) && (((x)-(y)) < 0.0000001)) || ((((y)-(x)) >= 0) && (((y)-(x)) < 0.0000001))  )
-
-#if ! defined(OP_API_H)
-typedef	unsigned short	OP_API_INSTANCE_ID;
-typedef unsigned long OP_LOAD_ID;
-#endif
-
-#if ! defined(EOK)
-#	define	EOK	0
-#else
-#	if EOK != 0
-	Generated error: EOK should be 0
-#	endif
-#endif
-
-#define NUM_MODEL_ARGS	8
-
-typedef unsigned long OP_FULL_MODEL_ID;
-
-#endif  /* __OPALTYPES__ */

thirdparty/xilinx/Makefile

@@ -0,0 +1,28 @@
+LIB = libxil.so
+
+PREFIX ?= /usr/local
+
+SRCS  = $(wildcard src/*.c)
+SRCS += $(wildcard orig/*/src/*.c)
+OBJS  = $(SRCS:c=o)
+
+CC = gcc
+CFLAGS = -O3 -fPIC -Iinclude/xilinx -Iorig/common_v1_00_a/src -Wno-int-conversion -Wno-pointer-to-int-cast -Wno-int-to-pointer-cast
+
+ifdef DEBUG
+	CFLAGS += -DDEBUG -DXDEBUG_WARNING -g
+endif
+
+all: $(LIB)
+
+$(LIB): $(OBJS)
+	$(CC) -shared -o $@ $^
+
+clean:
+	rm -f $(LIB) $(OBJS)
+
+install: $(LIB)
+	mkdir -p $(PREFIX)/include/xilinx
+	install -m 0644 $(LIB) $(PREFIX)/lib
+	install -m 0644 include/xilinx/*.h $(PREFIX)/include/xilinx
+	ldconfig

thirdparty/xilinx/README.md

@@ -0,0 +1 @@
+These drivers are taken from https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers

thirdparty/xilinx/include/xilinx/xaxidma.h

@@ -0,0 +1,741 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxidma.h
+* @addtogroup axidma_v9_0
+* @{
+* @details
+*
+* This is the driver API for the AXI DMA engine.
+*
+* For a full description of DMA features, please see the hardware spec. This
+* driver supports the following features:
+*
+*   - Scatter-Gather DMA (SGDMA)
+*   - Simple DMA
+*   - Interrupts
+*   - Programmable interrupt coalescing for SGDMA
+*   - APIs to manage Buffer Descriptors (BD) movement to and from the SGDMA
+*     engine
+*
+* <b>Simple DMA</b>
+*
+* Simple DMA allows the application to define a single transaction between DMA
+* and Device. It has two channels: one from the DMA to Device and the other
+* from Device to DMA. Application has to set the buffer address and
+* length fields to initiate the transfer in respective channel.
+*
+* <b>Transactions</b>
+*
+* The object used to describe a transaction is referred to as a Buffer
+* Descriptor (BD). Buffer descriptors are allocated in the user application.
+* The user application needs to set buffer address, transfer length, and
+* control information for this transfer. The control information includes
+* SOF and EOF. Definition of those masks are in xaxidma_hw.h
+*
+* <b>Scatter-Gather DMA</b>
+*
+* SGDMA allows the application to define a list of transactions in memory which
+* the hardware will process without further application intervention. During
+* this time, the application is free to continue adding more work to keep the
+* Hardware busy.
+*
+* User can check for the completion of transactions through polling the
+* hardware, or interrupts.
+*
+* SGDMA processes whole packets. A packet is defined as a series of
+* data bytes that represent a message. SGDMA allows a packet of data to be
+* broken up into one or more transactions. For example, take an Ethernet IP
+* packet which consists of a 14 byte header followed by a 1 or more bytes of
+* payload. With SGDMA, the application may point a BD to the header and another
+* BD to the payload, then transfer them as a single message. This strategy can
+* make a TCP/IP stack more efficient by allowing it to keep packet header and
+* data in different memory regions instead of assembling packets into
+* contiguous blocks of memory.
+*
+* <b>BD Ring Management</b>
+*
+* BD rings are shared by the software and the hardware.
+*
+* The hardware expects BDs to be setup as a linked list. The DMA hardware walks
+* through the list by following the next pointer field of a completed BD.
+* The hardware stops processing when the just completed BD is the same as the
+* BD specified in the Tail Ptr register in the hardware.
+*
+* The last BD in the ring is linked to the first BD in the ring.
+*
+* All BD management are done inside the driver. The user application should not
+* directly modify the BD fields. Modifications to the BD fields should always
+* go through the specific API functions.
+*
+* Within the ring, the driver maintains four groups of BDs. Each group consists
+* of 0 or more adjacent BDs:
+*
+*   - Free: The BDs that can be allocated by the application with
+*     XAxiDma_BdRingAlloc().
+*
+*   - Pre-process: The BDs that have been allocated with
+*     XAxiDma_BdRingAlloc(). These BDs are under application control. The
+*     application modifies these BDs through driver API to prepare them
+*     for DMA transactions.
+*
+*   - Hardware: The BDs that have been enqueued to hardware with
+*     XAxiDma_BdRingToHw(). These BDs are under hardware control and may be in a
+*     state of awaiting hardware processing, in process, or processed by
+*     hardware. It is considered an error for the application to change BDs
+*     while they are in this group. Doing so can cause data corruption and lead
+*     to system instability.
+*
+*   - Post-process: The BDs that have been processed by hardware and have
+*     been extracted from the Hardware group with XAxiDma_BdRingFromHw().
+*     These BDs are under application control. The application can check the
+*     transfer status of these BDs. The application use XAxiDma_BdRingFree()
+*     to put them into the Free group.
+*
+* BDs are expected to transition in the following way for continuous
+* DMA transfers:
+* <pre>
+*
+*         XAxiDma_BdRingAlloc()                   XAxiDma_BdRingToHw()
+*   Free ------------------------> Pre-process ----------------------> Hardware
+*                                                                      |
+*    /|\                                                               |
+*     |   XAxiDma_BdRingFree()                  XAxiDma_BdRingFromHw() |
+*     +--------------------------- Post-process <----------------------+
+*
+* </pre>
+*
+* When a DMA transfer is to be cancelled before enqueuing to hardware,
+* application can return the requested BDs to the Free group using
+* XAxiDma_BdRingUnAlloc(), as shown below:
+* <pre>
+*
+*         XAxiDma_BdRingUnAlloc()
+*   Free <----------------------- Pre-process
+*
+* </pre>
+*
+* The API provides functions for BD list traversal:
+* - XAxiDma_BdRingNext()
+* - XAxiDma_BdRingPrev()
+*
+* These functions should be used with care as they do not understand where
+* one group ends and another begins.
+*
+* <b>SGDMA Descriptor Ring Creation</b>
+*
+* BD ring is created using XAxiDma_BdRingCreate(). The memory for the BD ring
+* is allocated by the application, and it has to be contiguous. Physical
+* address is required to setup the BD ring.
+*
+* The applicaiton can use XAxiDma_BdRingMemCalc() to find out the amount of
+* memory needed for a certain number of BDs. XAxiDma_BdRingCntCalc() can be
+* used to find out how many BDs can be allocated for certain amount of memory.
+*
+* A helper function, XAxiDma_BdRingClone(), can speed up the BD ring setup if
+* the BDs have same types of controls, for example, SOF and EOF. After
+* using the XAxiDma_BdRingClone(), the application only needs to setup the
+* buffer address and transfer length. Note that certain BDs in one packet,
+* for example, the first BD and the last BD, may need to setup special
+* control information.
+*
+* <b>Descriptor Ring State Machine</b>
+*
+* There are two states of the BD ring:
+*
+*   - HALTED (H), where hardware is not running
+*
+*   - NOT HALTED (NH), where hardware is running
+*
+* The following diagram shows the state transition for the DMA engine:
+*
+* <pre>
+*   _____ XAxiDma_StartBdRingHw(), or XAxiDma_BdRingStart(),   ______
+*   |   |               or XAxiDma_Resume()                    |    |
+*   | H |----------------------------------------------------->| NH |
+*   |   |<-----------------------------------------------------|    |
+*   -----   XAxiDma_Pause() or XAxiDma_Reset()                 ------
+* </pre>
+*
+* <b>Interrupt Coalescing</b>
+*
+* SGDMA provides control over the frequency of interrupts through interrupt
+* coalescing. The DMA engine provides two ways to tune the interrupt
+* coalescing:
+*
+* - The packet threshold counter. Interrupt will fire once the
+*   programmable number of packets have been processed by the engine.
+*
+* - The packet delay timer counter. Interrupt will fire once the
+*   programmable amount of time has passed after processing the last packet,
+*   and no new packets to process. Note that the interrupt will only fire if
+*   at least one packet has been processed.
+*
+* <b> Interrupt </b>
+*
+* Interrupts are handled by the user application. Each DMA channel has its own
+* interrupt ID. The driver provides APIs to enable/disable interrupt,
+* and tune the interrupt frequency regarding to packet processing frequency.
+*
+* <b> Software Initialization </b>
+*
+*
+* To use the Simple mode DMA engine for transfers, the following setup is
+* required:
+*
+* - DMA Initialization using XAxiDma_CfgInitialize() function. This step
+*   initializes a driver instance for the given DMA engine and resets the
+*   engine.
+*
+* - Enable interrupts if chosen to use interrupt mode. The application is
+*   responsible for setting up the interrupt system, which includes providing
+*   and connecting interrupt handlers and call back functions, before
+*   enabling the interrupts.
+*
+* - Set the buffer address and length field in respective channels to start
+*   the DMA transfer
+*
+* To use the SG mode DMA engine for transfers, the following setup are
+* required:
+*
+* - DMA Initialization using XAxiDma_CfgInitialize() function. This step
+*   initializes a driver instance for the given DMA engine and resets the
+*   engine.
+*
+* - BD Ring creation. A BD ring is needed per DMA channel and can be built by
+*   calling XAxiDma_BdRingCreate().
+*
+* - Enable interrupts if chose to use interrupt mode. The application is
+*   responsible for setting up the interrupt system, which includes providing
+*   and connecting interrupt handlers and call back functions, before
+*   enabling the interrupts.
+*
+* - Start a DMA transfer: Call XAxiDma_BdRingStart() to start a transfer for
+*   the first time or after a reset, and XAxiDma_BdRingToHw() if the channel
+*   is already started. Calling XAxiDma_BdRingToHw() when a DMA channel is not
+*   running will not put the BDs to the hardware, and the BDs will be processed
+*   later when the DMA channel is started through XAxiDma_BdRingStart().
+*
+* <b> How to start DMA transactions </b>
+*
+* The user application uses XAxiDma_BdRingToHw() to submit BDs to the hardware
+* to start DMA transfers.
+*
+* For both channels, if the DMA engine is currently stopped (using
+* XAxiDma_Pause()), the newly added BDs will be accepted but not processed
+* until the DMA engine is started, using XAxiDma_BdRingStart(), or resumed,
+* using XAxiDma_Resume().
+*
+* <b> Software Post-Processing on completed DMA transactions </b>
+*
+* If the interrupt system has been set up and the interrupts are enabled,
+* a DMA channels notifies the software about the completion of a transfer
+* through interrupts. Otherwise, the user application can poll for
+* completions of the BDs, using XAxiDma_BdRingFromHw() or
+* XAxiDma_BdHwCompleted().
+*
+* - Once BDs are finished by a channel, the application first needs to fetch
+*   them from the channel using XAxiDma_BdRingFromHw().
+*
+* - On the TX side, the application now could free the data buffers attached to
+*   those BDs as the data in the buffers has been transmitted.
+*
+* - On the RX side, the application now could use the received data in the
+*	buffers attached to those BDs.
+*
+* - For both channels, completed BDs need to be put back to the Free group
+*   using XAxiDma_BdRingFree(), so they can be used for future transactions.
+*
+* - On the RX side, it is the application's responsibility to have BDs ready
+*   to receive data at any time. Otherwise, the RX channel refuses to
+*   accept any data if it has no RX BDs.
+*
+* <b> Examples </b>
+*
+* We provide five examples to show how to use the driver API:
+* - One for SG interrupt mode (xaxidma_example_sg_intr.c), multiple BD/packets transfer
+* - One for SG polling mode (xaxidma_example_sg_poll.c), single BD transfer.
+* - One for SG polling mode (xaxidma_poll_multi_pkts.c), multiple BD/packets transfer
+* - One for simple polling mode (xaxidma_example_simple_poll.c)
+* - One for simple Interrupt mode (xaxidma_example_simple_intr.c)
+*
+* <b> Address Translation </b>
+*
+* All buffer addresses and BD addresses for the hardware are physical
+* addresses. The user application is responsible to provide physical buffer
+* address for the BD upon BD ring creation. The user application accesses BD
+* through its virtual addess. The driver maintains the address translation
+* between the physical and virtual address for BDs.
+*
+* <b> Cache Coherency </b>
+*
+* This driver expects all application buffers attached to BDs to be in cache
+* coherent memory. If cache is used in the system, buffers for transmit MUST
+* be flushed from the cache before passing the associated BD to this driver.
+* Buffers for receive MUST be invalidated before accessing the data.
+*
+* <b> Alignment </b>
+*
+* For BDs:
+*
+* Minimum alignment is defined by the constant XAXIDMA_BD_MINIMUM_ALIGNMENT.
+* This is the smallest alignment allowed by both hardware and software for them
+* to properly work.
+*
+* If the descriptor ring is to be placed in cached memory, alignment also MUST
+* be at least the processor's cache-line size. Otherwise, system instability
+* occurs. For alignment larger than the cache line size, multiple cache line
+* size alignment is required.
+*
+* Aside from the initial creation of the descriptor ring (see
+* XAxiDma_BdRingCreate()), there are no other run-time checks for proper
+* alignment of BDs.
+*
+* For application data buffers:
+*
+* Application data buffers may reside on any alignment if DRE is built into the
+* hardware. Otherwise, application data buffer must be word-aligned. The word
+* is defined by XPAR_AXIDMA_0_M_AXIS_MM2S_TDATA_WIDTH for transmit and
+* XPAR_AXIDMA_0_S_AXIS_S2MM_TDATA_WIDTH for receive.
+*
+* For scatter gather transfers that have more than one BDs in the chain of BDs,
+* Each BD transfer length must be multiple of word too. Otherwise, internal
+* error happens in the hardware.
+*
+* <b> Error Handling </b>
+*
+* The DMA engine will halt on all error conditions. It requires the software
+* to do a reset before it can start process new transfer requests.
+*
+* <b> Restart After Stopping </b>
+*
+* After the DMA engine has been stopped (through reset or reset after an error)
+* the software keeps track of the current BD pointer when reset happens, and
+* processing of BDs can be resumed through XAxiDma_BdRingStart().
+*
+* <b> Limitations </b>
+*
+* This driver does not have any mechanisms for mutual exclusion. It is up to
+* the application to provide this protection.
+*
+* <b> Hardware Defaults & Exclusive Use </b>
+*
+* After the initialization or reset, the DMA engine is in the following
+* default mode:
+* - All interrupts are disabled.
+*
+* - Interrupt coalescing counter is 1.
+*
+* - The DMA engine is not running (halted). Each DMA channel is started
+*   separately, using XAxiDma_StartBdRingHw() if no BDs are setup for transfer
+*   yet, or XAxiDma_BdRingStart() otherwise.
+*
+* The driver has exclusive use of the registers and BDs. All accesses to the
+* registers and BDs should go through the driver interface.
+*
+* <b> Debug Print </b>
+*
+* To see the debug print for the driver, please put "-DDEBUG" as the extra
+* compiler flags in software platform settings. Also comment out the line in
+* xdebug.h: "#undef DEBUG".
+*
+* <b>Changes From v1.00a</b>
+*
+* . We have changes return type for XAxiDma_BdSetBufAddr() from void to int
+* . We added XAxiDma_LookupConfig() so that user does not need to look for the
+* hardware settings anymore.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz   05/18/10 First release
+* 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+*                     updated tcl file, added xaxidma_porting_guide.h
+* 3.00a jz   11/22/10 Support IP core parameters change
+* 4.00a rkv  02/22/11 Added support for simple DMA mode
+*		      New API added for simple DMA mode are
+*			- XAxiDma_Busy
+*			- XAxiDma_SimpleTransfer
+*		      New Macros added for simple DMA mode are
+* 			- XAxiDma_HasSg
+* 			- XAxiDma_IntrEnable
+* 			- XAxiDma_IntrGetEnabled
+* 			- XAxiDma_IntrDisable
+* 			- XAxiDma_IntrGetIrq
+* 			- XAxiDma_IntrAckIrq
+* 5.00a srt  08/25/11  Added support for memory barrier and modified
+*			Cache Macros to have a common API for Microblaze
+*			and Zynq.
+* 6.00a srt  01/24/12 Added support for Multi-Channel DMA mode.
+*		      - Changed APIs:
+*			* XAxiDma_GetRxRing(InstancePtr, RingIndex)
+*			* XAxiDma_Start(XAxiDma * InstancePtr, int RingIndex)
+*			* XAxiDma_Started(XAxiDma * InstancePtr, int RingIndex)
+*			* XAxiDma_Pause(XAxiDma * InstancePtr, int RingIndex)
+*			* XAxiDma_Resume(XAxiDma * InstancePtr, int RingIndex)
+*			* XAxiDma_SimpleTransfer(XAxiDma *InstancePtr,
+*        					u32 BuffAddr, u32 Length,
+*						int Direction, int RingIndex)
+*			* XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr,
+*					int RingIndex)
+*			* XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+*			* XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr,
+*        			int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
+*			* XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+*			* XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+*			* XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr,
+*					u32 LenBytes, u32 LengthMask)
+*       		* XAxiDma_BdGetActualLength(BdPtr, LengthMask)
+*			* XAxiDma_BdGetLength(BdPtr, LengthMask)
+*		       - New APIs
+*			* XAxiDma_SelectKeyHole(XAxiDma *InstancePtr,
+*						int Direction, int Select)
+*			* XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr,
+*						int RingIndex)
+* 7.00a srt  06/18/12  All the APIs changed in v6_00_a are reverted back for
+*		       backward compatibility.
+*			- New API:
+*			  XAxiDma_GetRxIndexRing(InstancePtr, RingIndex)
+* 7.01a srt  10/26/12  - Fixed issue with driver as it fails with IP version
+*		         < 6.00a as the parameter C_NUM_*_CHANNELS is not
+*			 applicable.
+*		       - Changed the logic of MCDMA BD fields Set APIs, to
+*			 clear the field first and then set it.
+* 7.02a srt  01/23/13  Replaced *_TDATA_WIDTH parameters to *_DATA_WIDTH
+*		       (CR 691867)
+*		       Updated DDR base address for IPI designs (CR 703656).
+* 8.0   adk  19/12/13  Updated as per the New Tcl API's
+*	srt  01/29/14  Added support for Micro DMA Mode and cyclic mode of
+*		       operations.
+*		      - New APIs:
+*			* XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr,
+*						int Direction, int Select)
+ *			* XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd*, u32)
+* 8.1   adk  20/01/15  Added support for peripheral test. Created the self
+*		       test example to include it on peripheral test's(CR#823144).
+* 8.1   adk  29/01/15  Added the sefltest api (XAxiDma_Selftest) to the driver source files
+* 		      (xaxidma_selftest.c) and called this from the selftest example
+* 9.0 	adk  27/07/15  Added support for 64-bit Addressing.
+* 9.0   adk  19/08/15  Fixed CR#873125 DMA SG Mode example tests are failing on
+*		       HW in 2015.3.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XAXIDMA_H_   /* prevent circular inclusions */
+#define XAXIDMA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xaxidma_bdring.h"
+#ifdef __MICROBLAZE__
+#include "xenv.h"
+#else
+#include <string.h>
+#include "xil_cache.h"
+#endif
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * The XAxiDma driver instance data. An instance must be allocated for each DMA
+ * engine in use.
+ */
+typedef struct XAxiDma {
+	u32 RegBase;		/* Virtual base address of DMA engine */
+
+	int HasMm2S;		/* Has transmit channel */
+	int HasS2Mm;		/* Has receive channel */
+	int Initialized;	/* Driver has been initialized */
+	int HasSg;
+
+	XAxiDma_BdRing TxBdRing;     /* BD container management for TX channel */
+	XAxiDma_BdRing RxBdRing[16]; /* BD container management for RX channel */
+	int TxNumChannels;
+	int RxNumChannels;
+	int MicroDmaMode;
+	int AddrWidth;		  /**< Address Width */
+} XAxiDma;
+
+/**
+ * The configuration structure for AXI DMA engine
+ *
+ * This structure passes the hardware building information to the driver
+ */
+typedef struct {
+	u32 DeviceId;
+	u32 BaseAddr;
+
+	int HasStsCntrlStrm;
+	int HasMm2S;
+	int HasMm2SDRE;
+	int Mm2SDataWidth;
+	int HasS2Mm;
+	int HasS2MmDRE;
+	int S2MmDataWidth;
+	int HasSg;
+	int Mm2sNumChannels;
+	int S2MmNumChannels;
+	int Mm2SBurstSize;
+	int S2MmBurstSize;
+	int MicroDmaMode;
+	int AddrWidth;		  /**< Address Width */
+} XAxiDma_Config;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/*****************************************************************************/
+/**
+* Get Transmit (Tx) Ring ptr
+*
+* Warning: This has a different API than the LLDMA driver. It now returns
+* the pointer to the BD ring.
+*
+* @param	InstancePtr is a pointer to the DMA engine instance to be
+*		worked on.
+*
+* @return	Pointer to the Tx Ring
+*
+* @note		C-style signature:
+* 		XAxiDma_BdRing * XAxiDma_GetTxRing(XAxiDma * InstancePtr)
+* 		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_GetTxRing(InstancePtr) \
+			(&((InstancePtr)->TxBdRing))
+
+/*****************************************************************************/
+/**
+* Get Receive (Rx) Ring ptr
+*
+* Warning: This has a different API than the LLDMA driver. It now returns
+* the pointer to the BD ring.
+*
+* @param	InstancePtr is a pointer to the DMA engine instance to be
+*		worked on.
+*
+* @return	Pointer to the Rx Ring
+*
+* @note
+* 		C-style signature:
+* 		XAxiDma_BdRing * XAxiDma_GetRxRing(XAxiDma * InstancePtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_GetRxRing(InstancePtr) \
+			(&((InstancePtr)->RxBdRing[0]))
+
+/*****************************************************************************/
+/**
+* Get Receive (Rx) Ring ptr of a Index
+*
+* Warning: This has a different API than the LLDMA driver. It now returns
+* the pointer to the BD ring.
+*
+* @param	InstancePtr is a pointer to the DMA engine instance to be
+*		worked on.
+* @param	RingIndex is the channel Index.
+*
+* @return	Pointer to the Rx Ring
+*
+* @note
+* 		C-style signature:
+* 		XAxiDma_BdRing * XAxiDma_GetRxIndexRing(XAxiDma * InstancePtr,
+						int RingIndex)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_GetRxIndexRing(InstancePtr, RingIndex) \
+			(&((InstancePtr)->RxBdRing[RingIndex]))
+
+/*****************************************************************************/
+/**
+* This function checks whether system is configured as Simple or
+* Scatter Gather mode
+*
+* @param	InstancePtr is a pointer to the DMA engine instance to be
+*		worked on.
+*
+* @return
+*		- TRUE if configured as SG mode
+*		- FALSE if configured as simple mode
+*
+* @note		None
+*
+*****************************************************************************/
+#define XAxiDma_HasSg(InstancePtr)	((InstancePtr)->HasSg) ? TRUE : FALSE
+
+/*****************************************************************************/
+/**
+ * This function enables interrupts specified by the Mask in specified
+ * direction, Interrupts that are not in the mask are not affected.
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ * @param	Mask is the mask for the interrupts to be enabled
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+ * @return	None
+ *
+ * @note	None
+ *
+ *****************************************************************************/
+#define  XAxiDma_IntrEnable(InstancePtr, Mask, Direction) 	\
+	XAxiDma_WriteReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET, \
+			(XAxiDma_ReadReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET)) \
+			| (Mask & XAXIDMA_IRQ_ALL_MASK))
+
+
+/*****************************************************************************/
+/**
+ * This function gets the mask for the interrupts that are currently enabled
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+ *
+ * @return	The bit mask for the interrupts that are currently enabled
+ *
+ * @note	None
+ *
+ *****************************************************************************/
+#define   XAxiDma_IntrGetEnabled(InstancePtr, Direction)	\
+			XAxiDma_ReadReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET) &\
+							XAXIDMA_IRQ_ALL_MASK)
+
+
+
+/*****************************************************************************/
+/**
+ * This function disables interrupts specified by the Mask. Interrupts that
+ * are not in the mask are not affected.
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ * @param	Mask is the mask for the interrupts to be disabled
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+ * @return	None
+ *
+ * @note	None
+ *
+ *****************************************************************************/
+ #define XAxiDma_IntrDisable(InstancePtr, Mask, Direction)	\
+		XAxiDma_WriteReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET, \
+			(XAxiDma_ReadReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET)) \
+			& ~(Mask & XAXIDMA_IRQ_ALL_MASK))
+
+
+/*****************************************************************************/
+/**
+ * This function gets the interrupts that are asserted.
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+ *
+ * @return	The bit mask for the interrupts asserted.
+ *
+ * @note	None
+ *
+ *****************************************************************************/
+#define  XAxiDma_IntrGetIrq(InstancePtr, Direction)	\
+			(XAxiDma_ReadReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_SR_OFFSET) &\
+							XAXIDMA_IRQ_ALL_MASK)
+
+/*****************************************************************************/
+/**
+ * This function acknowledges the interrupts that are specified in Mask
+ *
+ * @param	InstancePtr is the driver instance we are working on
+ * @param	Mask is the mask for the interrupts to be acknowledge
+ * @param	Direction is DMA transfer direction, valid values are
+ *			- XAXIDMA_DMA_TO_DEVICE.
+ *			- XAXIDMA_DEVICE_TO_DMA.
+ *
+ * @return	None
+ *
+ * @note	None.
+ *
+ *****************************************************************************/
+#define  XAxiDma_IntrAckIrq(InstancePtr, Mask, Direction)	\
+			XAxiDma_WriteReg((InstancePtr)->RegBase + \
+			(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_SR_OFFSET, \
+			(Mask) & XAXIDMA_IRQ_ALL_MASK)
+
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization and control functions in xaxidma.c
+ */
+XAxiDma_Config *XAxiDma_LookupConfig(u32 DeviceId);
+int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config);
+void XAxiDma_Reset(XAxiDma * InstancePtr);
+int XAxiDma_ResetIsDone(XAxiDma * InstancePtr);
+int XAxiDma_Pause(XAxiDma * InstancePtr);
+int XAxiDma_Resume(XAxiDma * InstancePtr);
+u32 XAxiDma_Busy(XAxiDma *InstancePtr,int Direction);
+u32 XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, UINTPTR BuffAddr, u32 Length,
+	int Direction);
+int XAxiDma_SelectKeyHole(XAxiDma *InstancePtr, int Direction, int Select);
+int XAxiDma_SelectCyclicMode(XAxiDma *InstancePtr, int Direction, int Select);
+int XAxiDma_Selftest(XAxiDma * InstancePtr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */

thirdparty/xilinx/include/xilinx/xaxidma_bd.h

@@ -0,0 +1,679 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xaxidma_bd.h
+* @addtogroup axidma_v9_0
+* @{
+ *
+ * Buffer descriptor (BD) management API.
+ *
+ * <b> Buffer Descriptors </b>
+ *
+ * A BD defines a DMA transaction (see "Transaction" section in xaxidma.h).
+ * All accesses to a BD go through this set of API.
+ *
+ * The XAxiDma_Bd structure defines a BD. The first XAXIDMA_BD_HW_NUM_BYTES
+ * are shared between hardware and software.
+ *
+ * <b> Actual Transfer Length </b>
+ *
+ * The actual transfer length for receive could be smaller than the requested
+ * transfer length. The hardware sets the actual transfer length in the
+ * completed BD. The API to retrieve the actual transfer length is
+ * XAxiDma_GetActualLength().
+ *
+ * <b> User IP words </b>
+ *
+ * There are 5 user IP words in each BD.
+ *
+ * If hardware does not have the StsCntrl stream built in, then these words
+ * are not usable. Retrieving these words get a NULL pointer and setting
+ * these words results an error.
+ *
+ * <b> Performance </b>
+ *
+ * BDs are typically in a non-cached memory space. Reducing the number of
+ * I/O operations to BDs can improve overall performance of the DMA channel.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ------------------------------------------------------
+ * 1.00a jz   05/18/10 First release
+ * 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+ *                     updated tcl file, added xaxidma_porting_guide.h
+ * 3.00a jz   11/22/10 Support IP core parameters change
+ * 5.00a srt  08/25/11 Changed Cache Macros to have a common API for Zynq
+ *		           and Microblaze.
+ * 6.00a srt  01/24/12 Added APIs to support Multi-Channel DMA:
+ *			XAxiDma_BdSetTId()
+ *			XAxiDma_BdGetTId()
+ *			XAxiDma_BdSetTDest()
+ *			XAxiDma_BdGetTDest()
+ *			XAxiDma_BdSetTUser()
+ *			XAxiDma_BdGetTUser()
+ *			XAxiDma_BdSetARCache()
+ *			XAxiDma_BdGetARCache()
+ *			XAxiDma_BdSetARUser()
+ *			XAxiDma_BdGetARUser()
+ *			XAxiDma_BdSetStride()
+ *			XAxiDma_BdGetStride()
+ *			XAxiDma_BdSetVSize()
+ *			XAxiDma_BdGetVSize()
+ *			- Changed APIs
+ *			XAxiDma_BdGetActualLength(BdPtr, LengthMask)
+ *			XAxiDma_BdGetLength(BdPtr, LengthMask)
+ *			XAxiDma_BdSetLength(XAxiDma_Bd* BdPtr,
+ *					u32 LenBytes, u32 LengthMask)
+ * 7.01a srt  10/26/12  Changed the logic of MCDMA BD fields Set APIs, to
+ *			clear the field first and set it.
+ * 8.0   srt  01/29/14 Added support for Micro DMA Mode.
+ *
+ * </pre>
+ *****************************************************************************/
+
+#ifndef XAXIDMA_BD_H_    /* To prevent circular inclusions */
+#define XAXIDMA_BD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xaxidma_hw.h"
+#include "xstatus.h"
+#include "xdebug.h"
+#include "xil_cache.h"
+
+#ifdef __MICROBLAZE__
+#include "xenv.h"
+#else
+#include <string.h>
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * The XAxiDma_Bd is the type for a buffer descriptor (BD).
+ */
+
+typedef UINTPTR XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS];
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/******************************************************************************
+ * Define methods to flush and invalidate cache for BDs should they be
+ * located in cached memory.
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XAXIDMA_CACHE_FLUSH(BdPtr)
+#define XAXIDMA_CACHE_INVALIDATE(BdPtr)
+#else
+#define XAXIDMA_CACHE_FLUSH(BdPtr) \
+	Xil_DCacheFlushRange((UINTPTR)(BdPtr), XAXIDMA_BD_HW_NUM_BYTES)
+
+#define XAXIDMA_CACHE_INVALIDATE(BdPtr) \
+	Xil_DCacheInvalidateRange((UINTPTR)(BdPtr), XAXIDMA_BD_HW_NUM_BYTES)
+#endif
+
+/*****************************************************************************/
+/**
+*
+* Read the given Buffer Descriptor word.
+*
+* @param	BaseAddress is the base address of the BD to read
+* @param	Offset is the word offset to be read
+*
+* @return	The 32-bit value of the field
+*
+* @note
+*		C-style signature:
+*		u32 XAxiDma_BdRead(u32 BaseAddress, u32 Offset)
+*
+******************************************************************************/
+#define XAxiDma_BdRead(BaseAddress, Offset)				\
+	(*(u32 *)((UINTPTR)((void *)(BaseAddress)) + (u32)(Offset)))
+
+/*****************************************************************************/
+/**
+*
+* Write the given Buffer Descriptor word.
+*
+* @param	BaseAddress is the base address of the BD to write
+* @param	Offset is the word offset to be written
+* @param	Data is the 32-bit value to write to the field
+*
+* @return	None.
+*
+* @note
+* 		C-style signature:
+*		void XAxiDma_BdWrite(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+******************************************************************************/
+#define XAxiDma_BdWrite(BaseAddress, Offset, Data)			\
+	(*(u32 *)((UINTPTR)(void *)(BaseAddress) + (u32)(Offset))) = (u32)(Data)
+
+/*****************************************************************************/
+/**
+ * Zero out BD specific fields. BD fields that are for the BD ring or for the
+ * system hardware build information are not touched.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdClear(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdClear(BdPtr)                    \
+  memset((void *)(((UINTPTR)(BdPtr)) + XAXIDMA_BD_START_CLEAR), 0, \
+    XAXIDMA_BD_BYTES_TO_CLEAR)
+
+/*****************************************************************************/
+/**
+ * Get the control bits for the BD
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	The bit mask for the control of the BD
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetCtrl(BdPtr)				\
+		(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET)	\
+		& XAXIDMA_BD_CTRL_ALL_MASK)
+/*****************************************************************************/
+/**
+ * Retrieve the status of a BD
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	Word at offset XAXIDMA_BD_DMASR_OFFSET. Use XAXIDMA_BD_STS_***
+ *		values defined in xaxidma_hw.h to interpret the returned value
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetSts(BdPtr)              \
+	(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \
+		XAXIDMA_BD_STS_ALL_MASK)
+/*****************************************************************************/
+/**
+ * Retrieve the length field value from the given BD.  The returned value is
+ * the same as what was written with XAxiDma_BdSetLength(). Note that in the
+ * this value does not reflect the real length of received data.
+ * See the comments of XAxiDma_BdSetLength() for more details. To obtain the
+ * actual transfer length, use XAxiDma_BdGetActualLength().
+ *
+ * @param	BdPtr is the BD to operate on.
+ * @param	LengthMask is the Maximum Transfer Length.
+ *
+ * @return	The length value set in the BD.
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetLength(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetLength(BdPtr, LengthMask)                \
+	(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET) & \
+		LengthMask)
+
+
+/*****************************************************************************/
+/**
+ * Set the ID field of the given BD. The ID is an arbitrary piece of data the
+ * application can associate with a specific BD.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	Id is a 32 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetId(XAxiDma_Bd* BdPtr, void Id)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetId(BdPtr, Id)                                      \
+	(XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_ID_OFFSET, (u32)(Id)))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the ID field of the given BD previously set with XAxiDma_BdSetId.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetId(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetId(BdPtr) (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_ID_OFFSET))
+
+/*****************************************************************************/
+/**
+ * Get the BD's buffer address
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetBufAddr(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetBufAddr(BdPtr)                     \
+	(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_BUFA_OFFSET))
+
+/*****************************************************************************/
+/**
+ * Check whether a BD has completed in hardware. This BD has been submitted
+ * to hardware. The application can use this function to poll for the
+ * completion of the BD.
+ *
+ * This function may not work if the BD is in cached memory.
+ *
+ * @param	BdPtr is the BD to check on
+ *
+ * @return
+ *		- 0 if not complete
+ *		- XAXIDMA_BD_STS_COMPLETE_MASK if completed, may contain
+ * 		XAXIDMA_BD_STS_*_ERR_MASK bits.
+ *
+ * @note
+ * 		C-style signature:
+ *		int XAxiDma_BdHwCompleted(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdHwCompleted(BdPtr)                     \
+	(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \
+		XAXIDMA_BD_STS_COMPLETE_MASK)
+
+/*****************************************************************************/
+/**
+ * Get the actual transfer length of a BD. The BD has completed in hw.
+ *
+ * This function may not work if the BD is in cached memory.
+ *
+ * @param	BdPtr is the BD to check on
+ * @param	LengthMask is the Maximum Transfer Length.
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		int XAxiDma_BdGetActualLength(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetActualLength(BdPtr, LengthMask)      \
+	(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \
+		LengthMask)
+
+/*****************************************************************************/
+/**
+ * Set the TID field of the TX BD.
+ * Provides a stream identifier and can be used to differentiate between
+ * multiple streams of data that are being transferred across the same
+ * interface.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	TId is a 8 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetTId(XAxiDma_Bd* BdPtr, void TId)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetTId(BdPtr, TId) \
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
+		~XAXIDMA_BD_TID_FIELD_MASK); \
+	val |= ((u32)(TId) << XAXIDMA_BD_TID_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
+}
+
+/*****************************************************************************/
+/**
+ * Retrieve the TID field of the RX BD previously set with XAxiDma_BdSetTId.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetTId(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetTId(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) &  \
+		XAXIDMA_BD_TID_FIELD_MASK)
+
+/*****************************************************************************/
+/**
+ * Set the TDEST field of the TX BD.
+ * Provides coarse routing information for the data stream.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	TDest is a 8 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetTDest(XAxiDma_Bd* BdPtr, void TDest)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetTDest(BdPtr, TDest) \
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
+		~XAXIDMA_BD_TDEST_FIELD_MASK); \
+	val |= ((u32)(TDest) << XAXIDMA_BD_TDEST_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
+}
+
+/*****************************************************************************/
+/**
+ * Retrieve the TDest field of the RX BD previously set with i
+ * XAxiDma_BdSetTDest.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetTDest(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetTDest(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) &  \
+		XAXIDMA_BD_TDEST_FIELD_MASK)
+
+/*****************************************************************************/
+/**
+ * Set the TUSER field of the TX BD.
+ * User defined sideband signaling.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	TUser is a 8 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetTUser(XAxiDma_Bd* BdPtr, void TUser)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetTUser(BdPtr, TUser)	\
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
+		~XAXIDMA_BD_TUSER_FIELD_MASK); \
+	val |= ((u32)(TUser) << XAXIDMA_BD_TUSER_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
+}
+
+/*****************************************************************************/
+/**
+ * Retrieve the TUSER field of the RX BD previously set with
+ * XAxiDma_BdSetTUser.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetTUser(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetTUser(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) &  \
+		XAXIDMA_BD_TUSER_FIELD_MASK)
+
+/*****************************************************************************/
+/**
+ * Set the ARCACHE field of the given BD.
+ * This signal provides additional information about the cacheable
+ * characteristics of the transfer.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	ARCache is a 8 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetARCache(XAxiDma_Bd* BdPtr, void ARCache)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetARCache(BdPtr, ARCache) \
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
+		~XAXIDMA_BD_ARCACHE_FIELD_MASK); \
+	val |= ((u32)(ARCache) << XAXIDMA_BD_ARCACHE_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
+}
+
+/*****************************************************************************/
+/**
+ * Retrieve the ARCACHE field of the given BD previously set with
+ * XAxiDma_BdSetARCache.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetARCache(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetARCache(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET)) &  \
+		XAXIDMA_BD_ARCACHE_FIELD_MASK)
+
+
+/*****************************************************************************/
+/**
+ * Set the ARUSER field of the given BD.
+ * Sideband signals used for user defined information.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	ARUser is a 8 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetARUser(XAxiDma_Bd* BdPtr, void ARUser)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetARUser(BdPtr, ARUser) \
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
+		~XAXIDMA_BD_ARUSER_FIELD_MASK); \
+	val |= ((u32)(ARUser) << XAXIDMA_BD_ARUSER_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
+}
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the ARUSER field of the given BD previously set with
+ * XAxiDma_BdSetARUser.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetARUser(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetARUser(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET)) &  \
+		XAXIDMA_BD_ARUSER_FIELD_MASK)
+
+/*****************************************************************************/
+/**
+ * Set the STRIDE field of the given BD.
+ * It is the address distance between the first address of successive
+ * horizontal reads.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	Stride is a 32 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetStride(XAxiDma_Bd* BdPtr, void Stride)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetStride(BdPtr, Stride) \
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET) & \
+		~XAXIDMA_BD_STRIDE_FIELD_MASK); \
+	val |= ((u32)(Stride) << XAXIDMA_BD_STRIDE_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET, val); \
+}
+
+/*****************************************************************************/
+/**
+ * Retrieve the STRIDE field of the given BD previously set with
+ * XAxiDma_BdSetStride.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetStride(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetStride(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET)) &  \
+		XAXIDMA_BD_STRIDE_FIELD_MASK)
+
+/*****************************************************************************/
+/**
+ * Set the VSIZE field of the given BD.
+ * Number of horizontal lines for strided access.
+ *
+ * @param	BdPtr is the BD to operate on
+ * @param	VSize is a 32 bit quantity to set in the BD
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		void XAxiDma_BdSetVSize(XAxiDma_Bd* BdPtr, void VSize)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdSetVSize(BdPtr, VSize) \
+{ \
+	u32 val; \
+	val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET) & \
+		~XAXIDMA_BD_VSIZE_FIELD_MASK); \
+	val |= ((u32)(VSize) << XAXIDMA_BD_VSIZE_FIELD_SHIFT); \
+	XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET, val); \
+}
+
+/*****************************************************************************/
+/**
+ * Retrieve the STRIDE field of the given BD previously set with
+ * XAxiDma_BdSetVSize.
+ *
+ * @param	BdPtr is the BD to operate on
+ *
+ * @return	None
+ *
+ * @note
+ *		C-style signature:
+ *		u32 XAxiDma_BdGetVSize(XAxiDma_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XAxiDma_BdGetVSize(BdPtr) \
+	((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET)) &  \
+		XAXIDMA_BD_VSIZE_FIELD_MASK)
+
+/*****************************************************************************/
+
+/************************** Function Prototypes ******************************/
+
+int XAxiDma_BdSetLength(XAxiDma_Bd* BdPtr, u32 LenBytes, u32 LengthMask);
+u32 XAxiDma_BdSetBufAddr(XAxiDma_Bd* BdPtr, UINTPTR Addr);
+u32 XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd* BdPtr, UINTPTR Addr);
+int XAxiDma_BdSetAppWord(XAxiDma_Bd * BdPtr, int Offset, u32 Word);
+u32 XAxiDma_BdGetAppWord(XAxiDma_Bd * BdPtr, int Offset, int *Valid);
+void XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data);
+
+/* Debug utility
+ */
+void XAxiDma_DumpBd(XAxiDma_Bd* BdPtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */

thirdparty/xilinx/include/xilinx/xaxidma_bdring.h

@@ -0,0 +1,526 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxidma_bdring.h
+* @addtogroup axidma_v9_0
+* @{
+*
+* This file contains DMA channel related structure and constant definition
+* as well as function prototypes. Each DMA channel is managed by a Buffer
+* Descriptor ring, and XAxiDma_BdRing is chosen as the symbol prefix used in
+* this file. See xaxidma.h for more information on how a BD ring is managed.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz   05/18/10 First release
+* 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+*                     updated tcl file, added xaxidma_porting_guide.h
+* 3.00a jz   11/22/10 Support IP core parameters change
+* 6.00a srt  01/24/12 Added support for Multi-Channel DMA.
+*		      - New API
+*			* XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr,
+*						int RingIndex)
+*		      - Changed APIs
+*			* XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr,
+*					int RingIndex)
+*			* XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+*			* XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr,
+*        			int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
+*			* XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+*			* XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr,
+*						 int RingIndex)
+* 7.00a srt  06/18/12  All the APIs changed in v6_00_a are reverted back for
+*		       backward compatibility.
+*
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XAXIDMA_BDRING_H_	/* prevent circular inclusions */
+#define XAXIDMA_BDRING_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xaxidma_bd.h"
+
+
+
+/************************** Constant Definitions *****************************/
+/* State of a DMA channel
+ */
+#define AXIDMA_CHANNEL_NOT_HALTED	1
+#define AXIDMA_CHANNEL_HALTED		2
+
+/* Argument constant to simplify argument setting
+ */
+#define XAXIDMA_NO_CHANGE		0xFFFFFFFF
+#define XAXIDMA_ALL_BDS			0x0FFFFFFF /* 268 Million */
+
+/**************************** Type Definitions *******************************/
+
+/** Container structure for descriptor storage control. If address translation
+ * is enabled, then all addresses and pointers excluding FirstBdPhysAddr are
+ * expressed in terms of the virtual address.
+ */
+typedef struct {
+	u32 ChanBase;		/**< physical base address*/
+
+	int IsRxChannel;	/**< Is this a receive channel */
+	volatile int RunState;	/**< Whether channel is running */
+	int HasStsCntrlStrm; 	/**< Whether has stscntrl stream */
+	int HasDRE;
+	int DataWidth;
+	int Addr_ext;
+	u32 MaxTransferLen;
+
+	UINTPTR FirstBdPhysAddr;	/**< Physical address of 1st BD in list */
+	UINTPTR FirstBdAddr;	/**< Virtual address of 1st BD in list */
+	UINTPTR LastBdAddr;		/**< Virtual address of last BD in the list */
+	u32 Length;		/**< Total size of ring in bytes */
+	UINTPTR Separation;		/**< Number of bytes between the starting
+				     address of adjacent BDs */
+	XAxiDma_Bd *FreeHead;	/**< First BD in the free group */
+	XAxiDma_Bd *PreHead;	/**< First BD in the pre-work group */
+	XAxiDma_Bd *HwHead;	/**< First BD in the work group */
+	XAxiDma_Bd *HwTail;	/**< Last BD in the work group */
+	XAxiDma_Bd *PostHead;	/**< First BD in the post-work group */
+	XAxiDma_Bd *BdaRestart;	/**< BD to load when channel is started */
+	int FreeCnt;		/**< Number of allocatable BDs in free group */
+	int PreCnt;		/**< Number of BDs in pre-work group */
+	int HwCnt;		/**< Number of BDs in work group */
+	int PostCnt;		/**< Number of BDs in post-work group */
+	int AllCnt;		/**< Total Number of BDs for channel */
+	int RingIndex;		/**< Ring Index */
+} XAxiDma_BdRing;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* within the given memory constraints.
+*
+* The results of this macro can be provided to XAxiDma_BdRingCreate().
+*
+* @param	Alignment specifies what byte alignment the BDs must fall
+*		on and must be a power of 2 to get an accurate calculation
+*		(32, 64, 126,...)
+* @param	Bytes is the number of bytes to be used to store BDs.
+*
+* @return	Number of BDs that can fit in the given memory area
+*
+* @note
+*		C-style signature:
+*		int XAxiDma_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*		This function is used only when system is configured as SG mode
+*
+******************************************************************************/
+#define XAxiDma_BdRingCntCalc(Alignment, Bytes)                           \
+	(uint32_t)((Bytes)/((sizeof(XAxiDma_Bd)+((Alignment)-1))&~((Alignment)-1)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* are required to contain a given number of BDs at a given alignment.
+*
+* @param	Alignment specifies what byte alignment the BDs must fall on.
+*		This parameter must be a power of 2 to get an accurate
+*		calculation (32, 64,128,...)
+* @param	NumBd is the number of BDs to calculate memory size
+*		requirements
+*
+* @return	The number of bytes of memory required to create a BD list
+*		with the given memory constraints.
+*
+* @note
+*		C-style signature:
+*		int XAxiDma_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*		This function is used only when system is configured as SG mode
+*
+******************************************************************************/
+#define XAxiDma_BdRingMemCalc(Alignment, NumBd)			\
+	(int)((sizeof(XAxiDma_Bd)+((Alignment)-1)) & ~((Alignment)-1))*(NumBd)
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XAxiDma_BdRingCreate().
+*
+* @param	RingPtr is the BD ring to operate on.
+*
+* @return	The total number of BDs allocated for this channel.
+*
+* @note
+* 		C-style signature:
+*		int XAxiDma_BdRingGetCnt(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XAxiDma_BdRingAlloc() for pre-
+* processing.
+*
+* @param	RingPtr is the BD ring to operate on.
+*
+* @return	The number of BDs currently allocatable.
+*
+* @note
+* 		C-style signature:
+*		int XAxiDma_BdRingGetFreeCnt(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingGetFreeCnt(RingPtr)  ((RingPtr)->FreeCnt)
+
+
+/****************************************************************************/
+/**
+* Snap shot the latest BD a BD ring is processing.
+*
+* @param	RingPtr is the BD ring to operate on.
+*
+* @return	None
+*
+* @note
+*		C-style signature:
+*		void XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingSnapShotCurrBd(RingPtr)				  \
+	{								  \
+		if (!RingPtr->IsRxChannel) {				  \
+			(RingPtr)->BdaRestart = (XAxiDma_Bd *)		  \
+				XAxiDma_ReadReg((RingPtr)->ChanBase,	  \
+					XAXIDMA_CDESC_OFFSET);		  \
+		} else {						  \
+			if (!RingPtr->RingIndex) {			  \
+				(RingPtr)->BdaRestart =	(XAxiDma_Bd *)	  \
+				XAxiDma_ReadReg(			  \
+					(RingPtr)->ChanBase,		  \
+					XAXIDMA_CDESC_OFFSET);		  \
+			} else {					  \
+				(RingPtr)->BdaRestart =	(XAxiDma_Bd *)	  \
+				XAxiDma_ReadReg(			  \
+				(RingPtr)->ChanBase,			  \
+				(XAXIDMA_RX_CDESC0_OFFSET +		  \
+				(RingPtr->RingIndex - 1) * 		  \
+					XAXIDMA_RX_NDESC_OFFSET));	  \
+			}						  \
+		}							  \
+	}
+
+/****************************************************************************/
+/**
+* Get the BD a BD ring is processing.
+*
+* @param	RingPtr is the BD ring to operate on.
+*
+* @return	The current BD that the BD ring is working on
+*
+* @note
+*		C-style signature:
+*		XAxiDma_Bd * XAxiDma_BdRingGetCurrBd(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingGetCurrBd(RingPtr)               \
+	(XAxiDma_Bd *)XAxiDma_ReadReg((RingPtr)->ChanBase, \
+					XAXIDMA_CDESC_OFFSET)              \
+
+/****************************************************************************/
+/**
+* Return the next BD in the ring.
+*
+* @param	RingPtr is the BD ring to operate on.
+* @param	BdPtr is the current BD.
+*
+* @return	The next BD in the ring relative to the BdPtr parameter.
+*
+* @note
+*		C-style signature:
+*		XAxiDma_Bd *XAxiDma_BdRingNext(XAxiDma_BdRing* RingPtr,
+*							XAxiDma_Bd *BdPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingNext(RingPtr, BdPtr)			\
+		(((UINTPTR)(BdPtr) >= (RingPtr)->LastBdAddr) ?	\
+			(UINTPTR)(RingPtr)->FirstBdAddr :	\
+			(UINTPTR)((UINTPTR)(BdPtr) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD in the ring.
+*
+* @param	RingPtr is the DMA channel to operate on.
+* @param	BdPtr is the current BD.
+*
+* @return	The previous BD in the ring relative to the BdPtr parameter.
+*
+* @note
+*		C-style signature:
+*		XAxiDma_Bd *XAxiDma_BdRingPrev(XAxiDma_BdRing* RingPtr,
+*		XAxiDma_Bd *BdPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingPrev(RingPtr, BdPtr)				\
+		(((u32)(BdPtr) <= (RingPtr)->FirstBdAddr) ?		\
+			(XAxiDma_Bd*)(RingPtr)->LastBdAddr :		\
+			(XAxiDma_Bd*)((u32)(BdPtr) - (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Retrieve the contents of the channel status register
+*
+* @param	RingPtr is the channel instance to operate on.
+*
+* @return	Current contents of status register
+*
+* @note
+*		C-style signature:
+*		u32 XAxiDma_BdRingGetSr(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingGetSr(RingPtr)				\
+		XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET)
+
+/****************************************************************************/
+/**
+* Get error bits of a DMA channel
+*
+* @param	RingPtr is the channel instance to operate on.
+*
+* @return	Rrror bits in the status register, they should be interpreted
+*		with XAXIDMA_ERR_*_MASK defined in xaxidma_hw.h
+*
+* @note
+*		C-style signature:
+*		u32 XAxiDma_BdRingGetError(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingGetError(RingPtr)				\
+		(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
+			& XAXIDMA_ERR_ALL_MASK)
+
+/****************************************************************************/
+/**
+* Check whether a DMA channel is started, meaning the channel is not halted.
+*
+* @param	RingPtr is the channel instance to operate on.
+*
+* @return
+*		- 1 if channel is started
+*		- 0 otherwise
+*
+* @note
+*		C-style signature:
+*		int XAxiDma_BdRingHwIsStarted(XAxiDma_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XAxiDma_BdRingHwIsStarted(RingPtr)				\
+		((XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
+			& XAXIDMA_HALTED_MASK) ? FALSE : TRUE)
+
+/****************************************************************************/
+/**
+* Check if the current DMA channel is busy with a DMA operation.
+*
+* @param	RingPtr is the channel instance to operate on.
+*
+* @return
+*		- 1 if the DMA is busy.
+*		- 0 otherwise
+*
+* @note
+*		C-style signature:
+*		int XAxiDma_BdRingBusy(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingBusy(RingPtr)					 \
+		(XAxiDma_BdRingHwIsStarted(RingPtr) &&		\
+		((XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
+			& XAXIDMA_IDLE_MASK) ? FALSE : TRUE))
+
+/****************************************************************************/
+/**
+* Set interrupt enable bits for a channel. This operation will modify the
+* XAXIDMA_CR_OFFSET register.
+*
+* @param	RingPtr is the channel instance to operate on.
+* @param	Mask consists of the interrupt signals to enable.Bits not
+*		specified in the mask are not affected.
+*
+* @note
+*		C-style signature:
+*		void XAxiDma_BdRingIntEnable(XAxiDma_BdRing* RingPtr, u32 Mask)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingIntEnable(RingPtr, Mask)			\
+		(XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET, \
+		XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) \
+			| ((Mask) & XAXIDMA_IRQ_ALL_MASK)))
+
+/****************************************************************************/
+/**
+* Get enabled interrupts of a channel. It is in XAXIDMA_CR_OFFSET register.
+*
+* @param	RingPtr is the channel instance to operate on.
+* @return	Enabled interrupts of a channel. Use XAXIDMA_IRQ_* defined in
+*		xaxidma_hw.h to interpret this returned value.
+*
+* @note
+*		C-style signature:
+*		u32 XAxiDma_BdRingIntGetEnabled(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingIntGetEnabled(RingPtr)				\
+	(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) \
+		& XAXIDMA_IRQ_ALL_MASK)
+
+/****************************************************************************/
+/**
+* Clear interrupt enable bits for a channel. It modifies the
+* XAXIDMA_CR_OFFSET register.
+*
+* @param	RingPtr is the channel instance to operate on.
+* @param	Mask consists of the interrupt signals to disable.Bits not
+*		specified in the Mask are not affected.
+*
+* @note
+*		C-style signature:
+*		void XAxiDma_BdRingIntDisable(XAxiDma_BdRing* RingPtr,
+*								u32 Mask)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingIntDisable(RingPtr, Mask)				\
+		(XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET, \
+		XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) & \
+			~((Mask) & XAXIDMA_IRQ_ALL_MASK)))
+
+/****************************************************************************/
+/**
+* Retrieve the contents of the channel's IRQ register XAXIDMA_SR_OFFSET. This
+* operation can be used to see which interrupts are pending.
+*
+* @param	RingPtr is the channel instance to operate on.
+*
+* @return	Current contents of the IRQ_OFFSET register. Use
+*		XAXIDMA_IRQ_*** values defined in xaxidma_hw.h to interpret
+*		the returned value.
+*
+* @note
+*		C-style signature:
+*		u32 XAxiDma_BdRingGetIrq(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingGetIrq(RingPtr)				\
+		(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
+			& XAXIDMA_IRQ_ALL_MASK)
+
+/****************************************************************************/
+/**
+* Acknowledge asserted interrupts. It modifies XAXIDMA_SR_OFFSET register.
+* A mask bit set for an unasserted interrupt has no effect.
+*
+* @param 	RingPtr is the channel instance to operate on.
+* @param	Mask are the interrupt signals to acknowledge
+*
+* @note
+*		C-style signature:
+*		void XAxiDma_BdRingAckIrq(XAxiDma_BdRing* RingPtr)
+*		This function is used only when system is configured as SG mode
+*
+*****************************************************************************/
+#define XAxiDma_BdRingAckIrq(RingPtr, Mask)				\
+		XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET,\
+			(Mask) & XAXIDMA_IRQ_ALL_MASK)
+
+/************************* Function Prototypes ******************************/
+
+/*
+ * Descriptor ring functions xaxidma_bdring.c
+ */
+int XAxiDma_StartBdRingHw(XAxiDma_BdRing* RingPtr);
+int XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing* RingPtr);
+u32 XAxiDma_BdRingCreate(XAxiDma_BdRing * RingPtr, UINTPTR PhysAddr,
+		UINTPTR VirtAddr, u32 Alignment, int BdCount);
+int XAxiDma_BdRingClone(XAxiDma_BdRing * RingPtr, XAxiDma_Bd * SrcBdPtr);
+int XAxiDma_BdRingAlloc(XAxiDma_BdRing * RingPtr, int NumBd,
+		XAxiDma_Bd ** BdSetPtr);
+int XAxiDma_BdRingUnAlloc(XAxiDma_BdRing * RingPtr, int NumBd,
+		XAxiDma_Bd * BdSetPtr);
+int XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr, int NumBd,
+		XAxiDma_Bd * BdSetPtr);
+int XAxiDma_BdRingFromHw(XAxiDma_BdRing * RingPtr, int BdLimit,
+		XAxiDma_Bd ** BdSetPtr);
+int XAxiDma_BdRingFree(XAxiDma_BdRing * RingPtr, int NumBd,
+		XAxiDma_Bd * BdSetPtr);
+int XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr);
+int XAxiDma_BdRingSetCoalesce(XAxiDma_BdRing * RingPtr, u32 Counter, u32 Timer);
+void XAxiDma_BdRingGetCoalesce(XAxiDma_BdRing * RingPtr,
+		u32 *CounterPtr, u32 *TimerPtr);
+
+/* The following functions are for debug only
+ */
+int XAxiDma_BdRingCheck(XAxiDma_BdRing * RingPtr);
+void XAxiDma_BdRingDumpRegs(XAxiDma_BdRing *RingPtr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */

thirdparty/xilinx/include/xilinx/xaxidma_hw.h

@@ -0,0 +1,344 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *  @file xaxidma_hw.h
+* @addtogroup axidma_v9_0
+* @{
+ *
+ * Hardware definition file. It defines the register interface and Buffer
+ * Descriptor (BD) definitions.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a jz   05/18/10 First release
+ * 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+ *                     updated tcl file, added xaxidma_porting_guide.h
+ * 3.00a jz   11/22/10 Support IP core parameters change
+ * 4.00a rkv  02/22/11 Added support for simple DMA mode
+ * 6.00a srt  01/24/12 Added support for Multi-Channel DMA mode
+ * 8.0   srt  01/29/14 Added support for Micro DMA Mode and Cyclic mode of
+ *		       operations.
+ *
+ * </pre>
+ *
+ *****************************************************************************/
+
+#ifndef XAXIDMA_HW_H_    /* prevent circular inclusions */
+#define XAXIDMA_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name DMA Transfer Direction
+ *  @{
+ */
+#define XAXIDMA_DMA_TO_DEVICE		0x00
+#define XAXIDMA_DEVICE_TO_DMA		0x01
+
+
+/** @name Buffer Descriptor Alignment
+ *  @{
+ */
+#define XAXIDMA_BD_MINIMUM_ALIGNMENT	0x40	/**< Minimum byte alignment
+						requirement for descriptors to
+						satisfy both hardware/software
+						needs */
+/*@}*/
+
+/** @name Micro DMA Buffer Address Alignment
+ *  @{
+ */
+#define XAXIDMA_MICROMODE_MIN_BUF_ALIGN	0xFFF	/**< Minimum byte alignment
+						requirement for buffer address
+						in Micro DMA mode */
+/*@}*/
+
+/** @name Maximum transfer length
+ *	This is determined by hardware
+ * @{
+ */
+#define XAXIDMA_MAX_TRANSFER_LEN	0x7FFFFF  /* Max length hw supports */
+#define XAXIDMA_MCHAN_MAX_TRANSFER_LEN	0x00FFFF  /* Max length MCDMA
+						     hw supports */
+/*@}*/
+
+/* Register offset definitions. Register accesses are 32-bit.
+ */
+/** @name Device registers
+ *  Register sets on TX and RX channels are identical
+ *  @{
+ */
+#define XAXIDMA_TX_OFFSET	0x00000000 /**< TX channel registers base
+					     *  offset */
+#define XAXIDMA_RX_OFFSET	0x00000030 /**< RX channel registers base
+					     * offset */
+
+/* This set of registers are applicable for both channels. Add
+ * XAXIDMA_TX_OFFSET to get to TX channel, and XAXIDMA_RX_OFFSET to get to RX
+ * channel
+ */
+#define XAXIDMA_CR_OFFSET	 0x00000000   /**< Channel control */
+#define XAXIDMA_SR_OFFSET	 0x00000004   /**< Status */
+#define XAXIDMA_CDESC_OFFSET	 0x00000008   /**< Current descriptor pointer */
+#define XAXIDMA_CDESC_MSB_OFFSET 0x0000000C   /**< Current descriptor pointer */
+#define XAXIDMA_TDESC_OFFSET	 0x00000010   /**< Tail descriptor pointer */
+#define XAXIDMA_TDESC_MSB_OFFSET 0x00000014   /**< Tail descriptor pointer */
+#define XAXIDMA_SRCADDR_OFFSET	 0x00000018   /**< Simple mode source address
+						pointer */
+#define XAXIDMA_SRCADDR_MSB_OFFSET	0x0000001C  /**< Simple mode source address
+						pointer */
+#define XAXIDMA_DESTADDR_OFFSET		0x00000018   /**< Simple mode destination address pointer */
+#define XAXIDMA_DESTADDR_MSB_OFFSET	0x0000001C   /**< Simple mode destination address pointer */
+#define XAXIDMA_BUFFLEN_OFFSET		0x00000028   /**< Tail descriptor pointer */
+#define XAXIDMA_SGCTL_OFFSET		0x0000002c   /**< SG Control Register */
+
+/** Multi-Channel DMA Descriptor Offsets **/
+#define XAXIDMA_RX_CDESC0_OFFSET	0x00000040   /**< Rx Current Descriptor 0 */
+#define XAXIDMA_RX_CDESC0_MSB_OFFSET	0x00000044   /**< Rx Current Descriptor 0 */
+#define XAXIDMA_RX_TDESC0_OFFSET	0x00000048   /**< Rx Tail Descriptor 0 */
+#define XAXIDMA_RX_TDESC0_MSB_OFFSET	0x0000004C   /**< Rx Tail Descriptor 0 */
+#define XAXIDMA_RX_NDESC_OFFSET		0x00000020   /**< Rx Next Descriptor Offset */
+/*@}*/
+
+/** @name Bitmasks of XAXIDMA_CR_OFFSET register
+ * @{
+ */
+#define XAXIDMA_CR_RUNSTOP_MASK	0x00000001 /**< Start/stop DMA channel */
+#define XAXIDMA_CR_RESET_MASK	0x00000004 /**< Reset DMA engine */
+#define XAXIDMA_CR_KEYHOLE_MASK	0x00000008 /**< Keyhole feature */
+#define XAXIDMA_CR_CYCLIC_MASK	0x00000010 /**< Cyclic Mode */
+/*@}*/
+
+/** @name Bitmasks of XAXIDMA_SR_OFFSET register
+ *
+ * This register reports status of a DMA channel, including
+ * run/stop/idle state, errors, and interrupts (note that interrupt
+ * masks are shared with XAXIDMA_CR_OFFSET register, and are defined
+ * in the _IRQ_ section.
+ *
+ * The interrupt coalescing threshold value and delay counter value are
+ * also shared with XAXIDMA_CR_OFFSET register, and are defined in a
+ * later section.
+ * @{
+ */
+#define XAXIDMA_HALTED_MASK		0x00000001  /**< DMA channel halted */
+#define XAXIDMA_IDLE_MASK		0x00000002  /**< DMA channel idle */
+#define XAXIDMA_ERR_INTERNAL_MASK	0x00000010  /**< Datamover internal
+						      *  err */
+#define XAXIDMA_ERR_SLAVE_MASK		0x00000020  /**< Datamover slave err */
+#define XAXIDMA_ERR_DECODE_MASK		0x00000040  /**< Datamover decode
+						      *  err */
+#define XAXIDMA_ERR_SG_INT_MASK		0x00000100  /**< SG internal err */
+#define XAXIDMA_ERR_SG_SLV_MASK		0x00000200  /**< SG slave err */
+#define XAXIDMA_ERR_SG_DEC_MASK		0x00000400  /**< SG decode err */
+#define XAXIDMA_ERR_ALL_MASK		0x00000770  /**< All errors */
+
+/** @name Bitmask for interrupts
+ * These masks are shared by XAXIDMA_CR_OFFSET register and
+ * XAXIDMA_SR_OFFSET register
+ * @{
+ */
+#define XAXIDMA_IRQ_IOC_MASK		0x00001000 /**< Completion intr */
+#define XAXIDMA_IRQ_DELAY_MASK		0x00002000 /**< Delay interrupt */
+#define XAXIDMA_IRQ_ERROR_MASK		0x00004000 /**< Error interrupt */
+#define XAXIDMA_IRQ_ALL_MASK		0x00007000 /**< All interrupts */
+/*@}*/
+
+/** @name Bitmask and shift for delay and coalesce
+ * These masks are shared by XAXIDMA_CR_OFFSET register and
+ * XAXIDMA_SR_OFFSET register
+ * @{
+ */
+#define XAXIDMA_DELAY_MASK		0xFF000000 /**< Delay timeout
+						     *  counter */
+#define XAXIDMA_COALESCE_MASK		0x00FF0000 /**< Coalesce counter */
+
+#define XAXIDMA_DELAY_SHIFT		24
+#define XAXIDMA_COALESCE_SHIFT		16
+/*@}*/
+
+
+/* Buffer Descriptor (BD) definitions
+ */
+
+/** @name Buffer Descriptor offsets
+ *  USR* fields are defined by higher level IP.
+ *  setup for EMAC type devices. The first 13 words are used by hardware.
+ *  All words after the 13rd word are for software use only.
+ *  @{
+ */
+#define XAXIDMA_BD_NDESC_OFFSET		0x00  /**< Next descriptor pointer */
+#define XAXIDMA_BD_NDESC_MSB_OFFSET	0x04  /**< Next descriptor pointer */
+#define XAXIDMA_BD_BUFA_OFFSET		0x08  /**< Buffer address */
+#define XAXIDMA_BD_BUFA_MSB_OFFSET	0x0C  /**< Buffer address */
+#define XAXIDMA_BD_MCCTL_OFFSET		0x10  /**< Multichannel Control Fields */
+#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET	0x14  /**< 2D Transfer Sizes */
+#define XAXIDMA_BD_CTRL_LEN_OFFSET	0x18  /**< Control/buffer length */
+#define XAXIDMA_BD_STS_OFFSET		0x1C  /**< Status */
+
+#define XAXIDMA_BD_USR0_OFFSET		0x20  /**< User IP specific word0 */
+#define XAXIDMA_BD_USR1_OFFSET		0x24  /**< User IP specific word1 */
+#define XAXIDMA_BD_USR2_OFFSET		0x28  /**< User IP specific word2 */
+#define XAXIDMA_BD_USR3_OFFSET		0x2C  /**< User IP specific word3 */
+#define XAXIDMA_BD_USR4_OFFSET		0x30  /**< User IP specific word4 */
+
+#define XAXIDMA_BD_ID_OFFSET		0x34  /**< Sw ID */
+#define XAXIDMA_BD_HAS_STSCNTRL_OFFSET	0x38  /**< Whether has stscntrl strm */
+#define XAXIDMA_BD_HAS_DRE_OFFSET	0x3C  /**< Whether has DRE */
+#define XAXIDMA_BD_ADDRLEN_OFFSET	0x40  /**< Check for BD Addr */
+
+#define XAXIDMA_BD_HAS_DRE_MASK		0xF00 /**< Whether has DRE mask */
+#define XAXIDMA_BD_WORDLEN_MASK		0xFF  /**< Whether has DRE mask */
+
+#define XAXIDMA_BD_HAS_DRE_SHIFT	8     /**< Whether has DRE shift */
+#define XAXIDMA_BD_WORDLEN_SHIFT	0     /**< Whether has DRE shift */
+
+#define XAXIDMA_BD_START_CLEAR		8   /**< Offset to start clear */
+#define XAXIDMA_BD_BYTES_TO_CLEAR	48  /**< BD specific bytes to be
+					      *  cleared */
+
+#define XAXIDMA_BD_NUM_WORDS		20U  /**< Total number of words for
+					       * one BD*/
+#define XAXIDMA_BD_HW_NUM_BYTES		52  /**< Number of bytes hw used */
+
+/* The offset of the last app word.
+ */
+#define XAXIDMA_LAST_APPWORD		4
+
+/*@}*/
+#define XAXIDMA_DESC_LSB_MASK	(0xFFFFFFC0U)	/**< LSB Address mask */
+
+/** @name Bitmasks of XAXIDMA_BD_CTRL_OFFSET register
+ *  @{
+ */
+#define XAXIDMA_BD_CTRL_TXSOF_MASK	0x08000000 /**< First tx packet */
+#define XAXIDMA_BD_CTRL_TXEOF_MASK	0x04000000 /**< Last tx packet */
+#define XAXIDMA_BD_CTRL_ALL_MASK	0x0C000000 /**< All control bits */
+/*@}*/
+
+/** @name Bitmasks of XAXIDMA_BD_STS_OFFSET register
+ *  @{
+ */
+#define XAXIDMA_BD_STS_COMPLETE_MASK	0x80000000 /**< Completed */
+#define XAXIDMA_BD_STS_DEC_ERR_MASK	0x40000000 /**< Decode error */
+#define XAXIDMA_BD_STS_SLV_ERR_MASK	0x20000000 /**< Slave error */
+#define XAXIDMA_BD_STS_INT_ERR_MASK	0x10000000 /**< Internal err */
+#define XAXIDMA_BD_STS_ALL_ERR_MASK	0x70000000 /**< All errors */
+#define XAXIDMA_BD_STS_RXSOF_MASK	0x08000000 /**< First rx pkt */
+#define XAXIDMA_BD_STS_RXEOF_MASK	0x04000000 /**< Last rx pkt */
+#define XAXIDMA_BD_STS_ALL_MASK		0xFC000000 /**< All status bits */
+/*@}*/
+
+/** @name Bitmasks and shift values for XAXIDMA_BD_MCCTL_OFFSET register
+ *  @{
+ */
+#define XAXIDMA_BD_TDEST_FIELD_MASK	0x0000000F
+#define XAXIDMA_BD_TID_FIELD_MASK	0x00000F00
+#define XAXIDMA_BD_TUSER_FIELD_MASK	0x000F0000
+#define XAXIDMA_BD_ARCACHE_FIELD_MASK	0x0F000000
+#define XAXIDMA_BD_ARUSER_FIELD_MASK	0xF0000000
+
+#define XAXIDMA_BD_TDEST_FIELD_SHIFT	0
+#define XAXIDMA_BD_TID_FIELD_SHIFT    	8
+#define XAXIDMA_BD_TUSER_FIELD_SHIFT	16
+#define XAXIDMA_BD_ARCACHE_FIELD_SHIFT	24
+#define XAXIDMA_BD_ARUSER_FIELD_SHIFT	28
+
+/** @name Bitmasks and shift values for XAXIDMA_BD_STRIDE_VSIZE_OFFSET register
+ *  @{
+ */
+#define XAXIDMA_BD_STRIDE_FIELD_MASK	0x0000FFFF
+#define XAXIDMA_BD_VSIZE_FIELD_MASK	0xFFF80000
+
+#define XAXIDMA_BD_STRIDE_FIELD_SHIFT	0
+#define XAXIDMA_BD_VSIZE_FIELD_SHIFT   	19
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XAxiDma_In32	Xil_In32
+#define XAxiDma_Out32	Xil_Out32
+
+/*****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param	BaseAddress is the base address of the device
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note
+*		C-style signature:
+*		u32 XAxiDma_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+******************************************************************************/
+#define XAxiDma_ReadReg(BaseAddress, RegOffset)             \
+    XAxiDma_In32((BaseAddress) + (RegOffset))
+
+/*****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param	BaseAddress is the base address of the device
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note
+*		C-style signature:
+*		void XAxiDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+******************************************************************************/
+#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)          \
+    XAxiDma_Out32((BaseAddress) + (RegOffset), (Data))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/** @} */

thirdparty/xilinx/include/xilinx/xaxidma_porting_guide.h

@@ -0,0 +1,254 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxidma_porting_guide.h
+* @addtogroup axidma_v9_0
+* @{
+*
+* This is a guide on how to move from using the xlldma driver to use xaxidma
+* driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz   05/18/10 First release
+* 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
+*                     updated tcl file, added xaxidma_porting_guide.h
+* 4.00a rkv  02/22/11 Added support for simple DMA mode
+* 6.00a srt  03/27/12 Added support for MCDMA mode
+* 7.00a srt  06/18/12 API calls are reverted back for backward compatibility.
+*
+* </pre>
+*
+* <b>Overview</b>
+*
+* The API for xaxidma driver is similar to xlldma driver. The prefix for the
+* API functions and structures is XAxiDma_ for the xaxidma driver.
+*
+* Due to hardware feature changes, signatures of some API functions are a
+* little bit different from the xlldma API functions.
+*
+* We present API functions:
+* - That only have prefix changes
+* - That have different return type
+* - That are new API functions
+* - That have been removed
+*
+* Note that data structures have different prefix of XAxiDma_. Those API
+* functions, that have data structures with prefix change, are considered as
+* prefix change.
+*
+* <b>API Functions That Only Have Prefix Changes</b>
+*
+* <pre>
+*         xlldma driver              |         xaxidma driver (upto v5_00_a)
+* -----------------------------------------------------------------------
+*    XLlDma_Reset(...)               |  XAxiDma_Reset(...)
+*    XLlDma_BdRingSnapShotCurrBd(...)|  XAxiDma_BdRingSnapShotCurrBd(...)
+*    XLlDma_BdRingNext(...)          |  XAxiDma_BdRingNext(...)
+*    XLlDma_BdRingPrev(...)          |  XAxiDma_BdRingPrev(...)
+*    XLlDma_BdRingGetSr(...)         |  XAxiDma_BdRingGetSr(...)
+*    XLlDma_BdRingBusy(...)          |  XAxiDma_BdRingBusy(...)
+*    XLlDma_BdRingIntEnable(...)     |  XAxiDma_BdRingIntEnable(...)
+*    XLlDma_BdRingIntDisable(...)    |  XAxiDma_BdRingIntDisable(...)
+*    XLlDma_BdRingIntGetEnabled(...) |  XAxiDma_BdRingIntGetEnabled(...)
+*    XLlDma_BdRingGetIrq(...)        |  XAxiDma_BdRingGetIrq(...)
+*    XLlDma_BdRingAckIrq(...)        |  XAxiDma_BdRingAckIrq(...)
+*    XLlDma_BdRingCreate(...)        |  XAxiDma_BdRingCreate(...)
+*    XLlDma_BdRingClone(...)         |  XAxiDma_BdRingClone(...)
+*    XLlDma_BdRingAlloc(...)         |  XAxiDma_BdRingAlloc(...)
+*    XLlDma_BdRingUnAlloc(...)       |  XAxiDma_BdRingUnAlloc(...)
+*    XLlDma_BdRingToHw(...)          |  XAxiDma_BdRingToHw(...)
+*    XLlDma_BdRingFromHw(...)        |  XAxiDma_BdRingFromHw(...)
+*    XLlDma_BdRingFree(...)          |  XAxiDma_BdRingFree(...)
+*    XLlDma_BdRingStart(...)         |  XAxiDma_BdRingStart(...)
+*    XLlDma_BdRingCheck(...)         |  XAxiDma_BdRingCheck(...)
+*    XLlDma_BdRingSetCoalesce(...)   |  XAxiDma_BdRingSetCoalesce(...)
+*    XLlDma_BdRingGetCoalesce(...)   |  XAxiDma_BdRingGetCoalesce(...)
+*    XLlDma_BdRead(...)              |  XAxiDma_BdRead(...)
+*    XLlDma_BdWrite(...)             |  XAxiDma_BdWrite(...)
+*    XLlDma_BdClear(...)             |  XAxiDma_BdClear(...)
+*    XLlDma_BdSetId(...)             |  XAxiDma_BdSetId(...)
+*    XLlDma_BdGetId(...)             |  XAxiDma_BdGetId(...)
+*    XLlDma_BdGetLength(...)         |  XAxiDma_BdGetLength(...)
+*    XLlDma_BdGetBufAddr(...)        |  XAxiDma_BdGetBufAddr(...)
+*
+*</pre>
+*
+* <b>API Functions That Have Different Return Type</b>
+*
+* Due to possible hardware failures, The caller should check the return value
+* of the following functions.
+*
+* <pre>
+*         xlldma driver              |         xaxidma driver
+* -----------------------------------------------------------------------
+* void XLlDma_Pause(...)             | int XAxiDma_Pause(...)
+* void XLlDma_Resume(...)            | int XAxiDma_Resume(...)
+* </pre>
+*
+* The following functions have return type changed:
+*
+* <pre>
+*         xlldma driver              |         xaxidma driver
+* -----------------------------------------------------------------------
+* XLlDma_BdRing XLlDma_GetRxRing(...)| XAxiDma_BdRing * XAxiDma_GetRxRing(...)
+* XLlDma_BdRing XLlDma_GetTxRing(...)| XAxiDma_BdRing * XAxiDma_GetTxRing(...)
+* u32 XLlDma_BdRingMemCalc(...)      | int XAxiDma_BdRingMemCalc(...)
+* u32 XLlDma_BdRingCntCalc(...)      | int XAxiDma_BdRingCntCalc(...)
+* u32 XLlDma_BdRingGetCnt(...)       | int XAxiDma_BdRingGetCnt(...)
+* u32 XLlDma_BdRingGetFreeCnt(...)   | int XAxiDma_BdRingGetFreeCnt(...)
+* void XLlDma_BdSetLength(...)       | int XAxiDma_BdSetLength(...)
+* void XLlDma_BdSetBufAddr(...)      | int XAxiDma_BdSetBufAddr(...)
+*</pre>
+*
+* <b>API Functions That Are New API Functions</b>
+*
+* Now that the AXI DMA core is a standalone core, some new API are intrduced.
+* Some other functions are added due to hardware interface change, so to
+* replace old API functions.
+*
+* - XAxiDma_Config *XAxiDma_LookupConfig(u32 DeviceId);
+* - int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config);
+* - int XAxiDma_ResetIsDone(XAxiDma * InstancePtr);
+* - XAxiDma_Bd * XAxiDma_BdRingGetCurrBd(XAxiDma_BdRing* RingPtr);
+* - int XAxiDma_BdRingHwIsStarted(XAxiDma_BdRing* RingPtr);
+* - void XAxiDma_BdRingDumpRegs(XAxiDma_BdRing *RingPtr);
+* - int XAxiDma_StartBdRingHw(XAxiDma_BdRing* RingPtr);
+* - void XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data);
+* - u32 XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr);
+* - u32 XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr);
+* - int XAxiDma_BdHwCompleted(XAxiDma_Bd* BdPtr);
+* - int XAxiDma_BdGetActualLength(XAxiDma_Bd* BdPtr);
+* - int XAxiDma_BdSetAppWord(XAxiDma_Bd * BdPtr, int Offset, u32 Word);
+* - u32 XAxiDma_BdGetAppWord(XAxiDma_Bd * BdPtr, int Offset, int *Valid);
+*
+* <b>API Functions That Have Been Removed</b>
+*
+* Please see individual function comments for how to replace the removed API
+* function with new API functions.
+*
+* - void XLlDma_Initialize(XLlDma * InstancePtr, u32 BaseAddress).
+*   This function is replaced by XAxiDma_LookupConfig()/XAxiDma_CfgInitialize()
+*
+* - u32 XLlDma_BdRingGetCr(XLlDma_BdRing* RingPtr).
+*   This is replaced by XAxiDma_BdRingGetError(XAxiDma_BdRing* RingPtr)
+*
+* - u32 XLlDma_BdRingSetCr(XLlDma_BdRing* RingPtr, u32 Data).
+*   This function is covered by other API functions:
+*      - void XAxiDma_BdRingIntEnable(XAxiDma_BdRing* RingPtr, u32 Mask)
+*      - void XAxiDma_BdRingIntDisable(XAxiDma_BdRing* RingPtr, u32 Mask)
+*      - int XAxiDma_BdRingSetCoalesce(XAxiDma_BdRing * RingPtr, u32 Counter,
+*            u32 Timer)
+*
+* - u32 XLlDma_BdSetStsCtrl(XLlDma_Bd* BdPtr, u32 Data).
+*   Replaced by XAxiDma_BdSetCtrl(XAxiDma_Bd *BdPtr, u32 Data);
+*
+* - u32 XLlDma_BdGetStsCtrl(XLlDma_Bd* BdPtr).
+*   Replaced by XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr) and
+*   XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr).
+*
+* <b>API Functions That Have Been Added to support simple DMA mode</b>
+*
+* - u32 XAxiDma_Busy(XAxiDma *InstancePtr,int Direction);
+* - int XAxiDma_SimpleTransfer(XAxiDma *InstancePtr, u32 BuffAddr, int Length,
+*	int Direction);
+* - XAxiDma_HasSg(InstancePtr);
+* - XAxiDma_IntrEnable(InstancePtr,Mask,Direction);
+* - XAxiDma_IntrGetEnabled(InstancePtr, Direction);
+* - XAxiDma_IntrDisable(InstancePtr, Mask, Direction);
+* - XAxiDma_IntrGetIrq(InstancePtr, Direction);
+* - XAxiDma_IntrAckIrq(InstancePtr, Mask, Direction);
+*
+* <b> For xaxidma driver v6_00_a Multiple Channel Support
+*     ---------------------------------------------------
+* This driver supports Multi-channel mode and accordingly some APIs are
+* changed to index multiple channels. Few new APIs are added.
+*  - Changed APIs
+*	* XAxiDma_GetRxRing(InstancePtr, RingIndex)
+* 	* XAxiDma_Start(XAxiDma * InstancePtr, int RingIndex)
+* 	* XAxiDma_Started(XAxiDma * InstancePtr, int RingIndex)
+* 	* XAxiDma_Pause(XAxiDma * InstancePtr, int RingIndex)
+* 	* XAxiDma_Resume(XAxiDma * InstancePtr, int RingIndex)
+* 	* XAxiDma_SimpleTransfer(XAxiDma *InstancePtr,
+*			u32 BuffAddr, u32 Length,
+*			int Direction, int RingIndex)
+*	* XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr,
+*			int RingIndex)
+*	* XAxiDma_BdRingStart(XAxiDma_BdRing * RingPtr,
+*			 int RingIndex)
+*	* XAxiDma_BdRingToHw(XAxiDma_BdRing * RingPtr,
+*      			int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
+*	* XAxiDma_BdRingDumpRegs(XAxiDma_BdRing * RingPtr,
+*			 int RingIndex)
+*	* XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing * RingPtr,
+*			 int RingIndex)
+*	* XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr,
+*			u32 LenBytes, u32 LengthMask)
+*       * XAxiDma_BdGetActualLength(BdPtr, LengthMask)
+*	* XAxiDma_BdGetLength(BdPtr, LengthMask)
+*
+*  - New APIs
+*	* XAxiDma_SelectKeyHole(XAxiDma *InstancePtr,
+*			int Direction, int Select)
+*	* XAxiDma_UpdateBdRingCDesc(XAxiDma_BdRing * RingPtr,
+*			int RingIndex)
+*	* XAxiDma_BdSetTId()
+*	* XAxiDma_BdGetTId()
+*	* XAxiDma_BdSetTDest()
+*	* XAxiDma_BdGetTDest()
+*	* XAxiDma_BdSetTUser()
+*	* XAxiDma_BdGetTUser()
+*	* XAxiDma_BdSetARCache()
+*	* XAxiDma_BdGetARCache()
+*	* XAxiDma_BdSetARUser()
+*	* XAxiDma_BdGetARUser()
+*	* XAxiDma_BdSetStride()
+*	* XAxiDma_BdGetStride()
+*	* XAxiDma_BdSetVSize()
+*	* XAxiDma_BdGetVSize()
+* <b> For xaxidma driver v7_00_a
+*     ---------------------------------------------------
+*  - New API
+*	* XAxiDma_GetRxIndexRing(InstancePtr, RingIndex)
+*
+*  - Changed APIs
+*	All the APIs changed in v6_00_a are reverted back for backward
+*	compatibility.
+*</pre>
+*
+******************************************************************************/
+/** @} */

thirdparty/xilinx/include/xilinx/xaxis_switch.h

@@ -0,0 +1,208 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxis_switch.h
+* @addtogroup axis_switch_v1_0
+* @{
+* @details
+*
+* This is the main header file for Xilinx AXI4-Stream Switch Control Router
+* core. It is used for routing streams where masters in the system do not know
+* final destination address.
+*
+* <b>Core Features </b>
+*
+* For a full description of AXI4-Stream Switch Control Router, please see the
+* hardware specification.
+*
+* <b>Software Initialization & Configuration</b>
+*
+* The application needs to do following steps in order for preparing the
+* AXI4-Stream Switch Control Router core to be ready.
+*
+* - Call XAxisScr_LookupConfig using a device ID to find the core
+*   configuration.
+* - Call XAxisScr_CfgInitialize to initialize the device and the driver
+*   instance associated with it.
+*
+* <b>Interrupts </b>
+*
+* This driver does not have interrupt mechanism.
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b> Building the driver </b>
+*
+* The XAXI4-Stream Switch driver is composed of several source files. This
+* allows the user to build and link only those parts of the driver that are
+* necessary.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- --------------------------------------------------
+* 1.00  sha 01/28/15 Initial release.
+* </pre>
+*
+******************************************************************************/
+#ifndef XAXIS_SWITCH_H_
+#define XAXIS_SWITCH_H_		/**< Prevent circular inclusions
+				  *  by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xaxis_switch_hw.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/**
+* This typedef contains configuration information for the AXI4-Stream Switch
+* core. Each AXI4-Stream Switch device should have a configuration structure
+* associated.
+*/
+typedef struct {
+	u16 DeviceId;		/**< DeviceId is the unique ID of the AXI4-
+				  *  Stream Switch core */
+	u32 BaseAddress;	/**< BaseAddress is the physical base address
+				  *  of the core's registers */
+	u8 MaxNumSI;		/**< Maximum number of Slave interfaces */
+	u8 MaxNumMI;		/**< Maximum number of Master interfaces */
+} XAxis_Switch_Config;
+
+/**
+* The AXI4-Stream Switch driver instance data. An instance must be allocated
+* for each core in use.
+*/
+typedef struct {
+	XAxis_Switch_Config Config;	/**< Hardware Configuration */
+	u32 IsReady;			/**< Core and the driver instance are
+					  *  initialized */
+} XAxis_Switch;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* This macro enables register updates.
+*
+* @param	InstancePtr is a pointer to the XAxis_Switch core instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XAxisScr_RegUpdateEnable(XAxis_Switch *InstancePtr)
+*
+******************************************************************************/
+#define XAxisScr_RegUpdateEnable(InstancePtr) \
+	XAxisScr_WriteReg((InstancePtr)->Config.BaseAddress, \
+		XAXIS_SCR_CTRL_OFFSET, \
+		XAxisScr_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XAXIS_SCR_CTRL_OFFSET) | \
+				XAXIS_SCR_CTRL_REG_UPDATE_MASK)
+
+/*****************************************************************************/
+/**
+*
+* This macro disables register updates.
+*
+* @param	InstancePtr is a pointer to the XAxis_Switch core instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XAxisScr_RegUpdateDisable(XAxis_Switch *InstancePtr)
+*
+******************************************************************************/
+#define XAxisScr_RegUpdateDisable(InstancePtr) \
+	XAxisScr_WriteReg((InstancePtr)->Config.BaseAddress, \
+		XAXIS_SCR_CTRL_OFFSET, \
+		XAxisScr_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XAXIS_SCR_CTRL_OFFSET) & \
+				(~XAXIS_SCR_CTRL_REG_UPDATE_MASK))
+
+/************************** Function Prototypes ******************************/
+
+/* Initialization function in xaxis_switch_sinit.c */
+XAxis_Switch_Config *XAxisScr_LookupConfig(u16 DeviceId);
+
+/* Initialization and control functions in xaxis_switch.c */
+s32 XAxisScr_CfgInitialize(XAxis_Switch *InstancePtr,
+			XAxis_Switch_Config *CfgPtr, u32 EffectiveAddr);
+
+void XAxisScr_MiPortEnable(XAxis_Switch *InstancePtr, u8 MiIndex,
+				u8 SiIndex);
+void XAxisScr_MiPortDisable(XAxis_Switch *InstancePtr, u8 MiIndex);
+s32 XAxisScr_IsMiPortEnabled(XAxis_Switch *InstancePtr, u8 MiIndex,
+				u8 SiIndex);
+s32 XAxisScr_IsMiPortDisabled(XAxis_Switch *InstancePtr, u8 MiIndex);
+void XAxisScr_MiPortDisableAll(XAxis_Switch *InstancePtr);
+
+/* Self test function in xaxis_switch_selftest.c */
+s32 XAxisScr_SelfTest(XAxis_Switch *InstancePtr);
+
+/************************** Variable Declarations ****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro */
+/** @} */

thirdparty/xilinx/include/xilinx/xaxis_switch_hw.h

@@ -0,0 +1,167 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xaxis_switch_hw.h
+* @addtogroup axis_switch_v1_0
+* @{
+*
+* This header file contains identifiers and register-level core functions (or
+* macros) that can be used to access the Xilinx AXI4-Stream Switch Control
+* Router core.
+*
+* For more information about the operation of this core see the hardware
+* specification and documentation in the higher level driver
+* xaxis_switch.h file.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- --------------------------------------------------
+* 1.00  sha 01/28/15 Initial release.
+* </pre>
+*
+******************************************************************************/
+#ifndef XAXIS_SWITCH_HW_H_
+#define XAXIS_SWITCH_HW_H_	/**< Prevent circular inclusions
+				  *  by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name MI MUX register offsets
+*
+* @{
+*/
+#define XAXIS_SCR_CTRL_OFFSET		0x000	/**< Control Register offset */
+#define XAXIS_SCR_MI_MUX_START_OFFSET	0x040	/**< Start of MI MUX Register
+						  *  offset */
+#define XAXIS_SCR_MI_MUX_END_OFFSET	0x07C	/**< End of MI MUX Register
+						  *  offset */
+
+/*@}*/
+
+/** @name MI MUX Control register mask
+* @{
+*/
+#define XAXIS_SCR_CTRL_REG_UPDATE_MASK	0x02	/**< Register Update
+						  *  mask */
+/*@}*/
+
+/** @name MI MUX register mask
+*
+* It is applicable for MI[0...15] registers.
+* @{
+*/
+#define XAXIS_SCR_MI_X_MUX_MASK		0x0F		/**< MI MUX mask */
+#define XAXIS_SCR_MI_X_DISABLE_MASK	0x80000000	/**< MI Disable mask */
+#define XAXIS_SCR_MI_X_DISABLE_SHIFT	31	/**< MI Disable shift */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/** @name Register access macro definition
+* @{
+*/
+#define XAxisScr_In32		Xil_In32	/**< Input Operations */
+#define XAxisScr_Out32		Xil_Out32	/**< Output Operations */
+
+/*****************************************************************************/
+/**
+*
+* This macro reads a value from a AXI4-Stream Switch register. A 32 bit read
+* is performed. If the component is implemented in a smaller width, only the
+* least significant data is read from the register. The most significant data
+* will be read as 0.
+*
+* @param	BaseAddress is the base address of the XAxis_Switch core
+*		instance.
+* @param	RegOffset is the register offset of the register (defined at
+*		the top of this file).
+*
+* @return	The 32-bit value of the register.
+*
+* @note		C-style signature:
+*		u32 XAxisScr_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+******************************************************************************/
+#define XAxisScr_ReadReg(BaseAddress, RegOffset) \
+	XAxisScr_In32((BaseAddress) + ((u32)RegOffset))
+
+/*****************************************************************************/
+/**
+*
+* This macro writes a value to a AXI4-Stream Switch register. A 32 bit write
+* is performed. If the component is implemented in a smaller width, only the
+* least significant data is written.
+*
+* @param	BaseAddress is the base address of the XAxis_Switch core
+*		instance.
+* @param	RegOffset is the register offset of the register (defined at
+*		the top of this file) to be written.
+* @param	Data is the 32-bit value to write into the register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XAxisScr_WriteReg(u32 BaseAddress, u32 RegOffset,
+*		u32 Data)
+*
+******************************************************************************/
+#define XAxisScr_WriteReg(BaseAddress, RegOffset, Data) \
+	XAxisScr_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))
+/*@}*/
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Declarations ****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */

thirdparty/xilinx/include/xilinx/xbasic_types.h

@@ -0,0 +1,315 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* This file contains basic types for Xilinx software IP.  These types do not
+* follow the standard naming convention with respect to using the component
+* name in front of each name because they are considered to be primitives.
+*
+* @note
+*
+* This file contains items which are architecture dependent.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rmm  12/14/01 First release
+*       rmm  05/09/03 Added "xassert always" macros to rid ourselves of diab
+*                     compiler warnings
+* 1.00a rpm  11/07/03 Added XNullHandler function as a stub interrupt handler
+* 1.00a rpm  07/21/04 Added XExceptionHandler typedef for processor exceptions
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a wre  01/25/07 Added Linux style data types u32, u16, u8, TRUE, FALSE
+* 1.00a rpm  04/02/07 Added ifndef KERNEL around u32, u16, u8 data types
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H	/* prevent circular inclusions */
+#define XBASIC_TYPES_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#  define TRUE		1
+#endif
+
+#ifndef FALSE
+#  define FALSE		0
+#endif
+
+#ifndef NULL
+#define NULL		0
+#endif
+
+/** Xilinx NULL, TRUE and FALSE legacy support. Deprecated. */
+#define XNULL		NULL
+#define XTRUE		TRUE
+#define XFALSE		FALSE
+
+
+#define XCOMPONENT_IS_READY     0x11111111  /**< component has been initialized */
+#define XCOMPONENT_IS_STARTED   0x22222222  /**< component has been started */
+
+/* the following constants and declarations are for unit test purposes and are
+ * designed to be used in test applications.
+ */
+#define XTEST_PASSED    0
+#define XTEST_FAILED    1
+
+#define XASSERT_NONE     0
+#define XASSERT_OCCURRED 1
+
+extern unsigned int XAssertStatus;
+extern void XAssert(char *, int);
+
+/**************************** Type Definitions *******************************/
+
+#include <stdint.h>
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef uint8_t		Xuint8;		/**< unsigned 8-bit */
+typedef int8_t		Xint8;		/**< signed 8-bit */
+typedef uint16_t	Xuint16;	/**< unsigned 16-bit */
+typedef int16_t		Xint16;		/**< signed 16-bit */
+typedef uint32_t	Xuint32;	/**< unsigned 32-bit */
+typedef int32_t		Xint32;		/**< signed 32-bit */
+typedef float		Xfloat32;	/**< 32-bit floating point */
+typedef double		Xfloat64;	/**< 64-bit double precision FP */
+typedef unsigned	Xboolean;	/**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+	Xuint32 Upper;
+	Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32         u32;
+typedef Xuint16         u16;
+typedef Xuint8          u8;
+#endif
+#else
+#include <linux/types.h>
+#endif
+
+/*@}*/
+
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Return the most significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The upper 32 bits of the 64 bit word.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* Return the least significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The lower 32 bits of the 64 bit word.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do not return anything
+* (void). This in conjunction with the XWaitInAssert boolean can be used to
+* accomodate tests so that asserts which fail allow execution to continue.
+*
+* @param    expression is the expression to evaluate. If it evaluates to
+*           false, the assert occurs.
+*
+* @return   Returns void unless the XWaitInAssert variable is true, in which
+*           case no return is made and an infinite loop is entered.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XASSERT_VOID(expression)                   \
+{                                                  \
+    if (expression)                                \
+    {                                              \
+        XAssertStatus = XASSERT_NONE;              \
+    }                                              \
+    else                                           \
+    {                                              \
+        XAssert(__FILE__, __LINE__);               \
+                XAssertStatus = XASSERT_OCCURRED;  \
+        return;                                    \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do return a value. This in
+* conjunction with the XWaitInAssert boolean can be used to accomodate tests so
+* that asserts which fail allow execution to continue.
+*
+* @param    expression is the expression to evaluate. If it evaluates to false,
+*           the assert occurs.
+*
+* @return   Returns 0 unless the XWaitInAssert variable is true, in which case
+*           no return is made and an infinite loop is entered.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XASSERT_NONVOID(expression)                \
+{                                                  \
+    if (expression)                                \
+    {                                              \
+        XAssertStatus = XASSERT_NONE;              \
+    }                                              \
+    else                                           \
+    {                                              \
+        XAssert(__FILE__, __LINE__);               \
+                XAssertStatus = XASSERT_OCCURRED;  \
+        return 0;                                  \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do not
+* return anything (void). Use for instances where an assert should always
+* occur.
+*
+* @return Returns void unless the XWaitInAssert variable is true, in which case
+*         no return is made and an infinite loop is entered.
+*
+* @note   None.
+*
+******************************************************************************/
+#define XASSERT_VOID_ALWAYS()                      \
+{                                                  \
+   XAssert(__FILE__, __LINE__);                    \
+           XAssertStatus = XASSERT_OCCURRED;       \
+   return;                                         \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do return
+* a value. Use for instances where an assert should always occur.
+*
+* @return Returns void unless the XWaitInAssert variable is true, in which case
+*         no return is made and an infinite loop is entered.
+*
+* @note   None.
+*
+******************************************************************************/
+#define XASSERT_NONVOID_ALWAYS()                   \
+{                                                  \
+   XAssert(__FILE__, __LINE__);                    \
+           XAssertStatus = XASSERT_OCCURRED;       \
+   return 0;                                       \
+}
+
+
+#else
+
+#define XASSERT_VOID(expression)
+#define XASSERT_VOID_ALWAYS()
+#define XASSERT_NONVOID(expression)
+#define XASSERT_NONVOID_ALWAYS()
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void XAssertSetCallback(XAssertCallback Routine);
+void XNullHandler(void *NullParameter);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */

thirdparty/xilinx/include/xilinx/xdebug.h

@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef _XDEBUG_H
+#define _XDEBUG_H
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#include <stdio.h>
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+#define XDBG_DEBUG_ERROR             0x00000001    /* error  condition messages */
+#define XDBG_DEBUG_GENERAL           0x00000002    /* general debug  messages */
+#define XDBG_DEBUG_ALL               0xFFFFFFFF    /* all debugging data */
+
+#define XDBG_DEBUG_FIFO_REG          0x00000100    /* display register reads/writes */
+#define XDBG_DEBUG_FIFO_RX           0x00000101    /* receive debug messages */
+#define XDBG_DEBUG_FIFO_TX           0x00000102    /* transmit debug messages */
+#define XDBG_DEBUG_FIFO_ALL          0x0000010F    /* all fifo debug messages */
+
+#define XDBG_DEBUG_TEMAC_REG         0x00000400    /* display register reads/writes */
+#define XDBG_DEBUG_TEMAC_RX          0x00000401    /* receive debug messages */
+#define XDBG_DEBUG_TEMAC_TX          0x00000402    /* transmit debug messages */
+#define XDBG_DEBUG_TEMAC_ALL         0x0000040F    /* all temac  debug messages */
+
+#define XDBG_DEBUG_TEMAC_ADPT_RX     0x00000800    /* receive debug messages */
+#define XDBG_DEBUG_TEMAC_ADPT_TX     0x00000801    /* transmit debug messages */
+#define XDBG_DEBUG_TEMAC_ADPT_IOCTL  0x00000802    /* ioctl debug messages */
+#define XDBG_DEBUG_TEMAC_ADPT_MISC   0x00000803    /* debug msg for other routines */
+#define XDBG_DEBUG_TEMAC_ADPT_ALL    0x0000080F    /* all temac adapter debug messages */
+
+#define xdbg_current_types (XDBG_DEBUG_ERROR)
+
+#define xdbg_stmnt(x)  x
+
+/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for
+ * macros that accept variable number of arguments
+ */
+#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
+#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0)
+
+#else /* ANSI Syntax */
+
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+
+#endif
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x)
+
+/* See VxWorks comments above */
+#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
+#define xdbg_printf(type, args...)
+#else /* ANSI Syntax */
+#define xdbg_printf(...)
+#endif
+
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#endif /* _XDEBUG_H */

thirdparty/xilinx/include/xilinx/xenv.h

@@ -0,0 +1,191 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch   10/24/02 Added XENV_LINUX
+* 1.00a rmm  04/17/02 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param   DestPtr is the destination address to copy data to.
+ * @param   SrcPtr is the source address to copy data from.
+ * @param   Bytes is the number of bytes to copy.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param   DestPtr is the destination address to set.
+ * @param   Data contains the value to set.
+ * @param   Bytes is the number of bytes to set.
+ *
+ * @return  None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param   delay is the number of microseconds to delay.
+ *
+ * @return  None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+
+/** @} */

thirdparty/xilinx/include/xilinx/xenv_linux.h

@@ -0,0 +1,255 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_linux.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* 	This file is not intended to be included directly by driver code.
+* 	Instead, the generic xenv.h file is intended to be included by driver
+* 	code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a ch   10/24/02 First release
+* 1.10a wgr  03/22/07 Converted to new coding style.
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XENV_LINUX_H
+#define XENV_LINUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include <asm/cache.h>
+#include <asm/cacheflush.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * Those macros are defined to catch legacy code in Xilinx drivers. The
+ * XENV_MEM_COPY and XENV_MEM_FILL macros were used in early Xilinx driver
+ * code. They are being replaced by memcpy() and memset() function calls. These
+ * macros are defined to catch any remaining occurences of those macros.
+ *
+ ******************************************************************************/
+
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	SrcPtr
+ * 		Source address to copy data from.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+		memcpy(DestPtr, SrcPtr, Bytes)
+/*		do_not_use_XENV_MEM_COPY_use_memcpy_instead */
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	Data
+ * 		Value to set.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+		memset(DestPtr, Data, Bytes)
+/*		do_not_use_XENV_MEM_FILL_use_memset_instead */
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef int XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * <br><br>
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param	delay
+ * 		Number of microseconds to delay.
+ *
+ * @return	None.
+ *
+ * @note	XENV_USLEEP is deprecated. Use udelay() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_USLEEP(delay)	udelay(delay)
+/*		do_not_use_XENV_MEM_COPY_use_memcpy_instead */
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ * The implementation of the cache handling functions can be found in
+ * arch/microblaze.
+ *
+ * These #defines are simple mappings to the Linux API.
+ *
+ * The underlying Linux implementation will take care of taking the right
+ * actions depending on the configuration of the MicroBlaze processor in the
+ * system.
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_DCACHE()		__enable_dcache()
+#define XCACHE_DISABLE_DCACHE()		__disable_dcache()
+#define XCACHE_ENABLE_ICACHE()		__enable_icache()
+#define XCACHE_DISABLE_ICACHE()		__disable_icache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) invalidate_dcache_range((u32)(Addr), ((u32)(Addr)+(Len)))
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)      flush_dcache_range((u32)(Addr), ((u32)(Addr)+(Len)))
+
+#define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) "XCACHE_INVALIDATE_ICACHE_RANGE unsupported"
+#define XCACHE_FLUSH_ICACHE_RANGE(Addr, Len)      flush_icache_range(Addr, Len)
+
+#define XCACHE_ENABLE_CACHE()	\
+		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE()	\
+		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+
+/** @} */

thirdparty/xilinx/include/xilinx/xenv_none.h

@@ -0,0 +1,55 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_none.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* This is a legacy file kept for backwards compatibility.
+*
+* Please modify your code to #include "xenv_standalone.h" instead.
+*
+*
+******************************************************************************/
+
+#warning ********************************************************************
+#warning *
+#warning * Use of xenv_none.h deprecated.
+#warning * Please include the new xenv_standalone.h file instead.
+#warning *
+#warning ********************************************************************
+
+#include "xenv_standalone.h"
+
+/** @} */

thirdparty/xilinx/include/xilinx/xenv_standalone.h

@@ -0,0 +1,370 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* 	This file is not intended to be included directly by driver code.
+* 	Instead, the generic xenv.h file is intended to be included by driver
+* 	code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+*                     used under Xilinx standalone BSP.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a rmm  03/21/02 First release
+* 1.00a wgr  03/22/07 Converted to new coding style.
+* 1.00a rpm  06/29/07 Added udelay macro for standalone
+* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
+*                     to in MICROBLAZE section
+* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include <string.h>
+
+#if defined __MICROBLAZE__
+#  include "mb_interface.h"
+#  include "xparameters.h"   /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+#  include "sleep.h"
+#  include "xcache_l.h"      /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	SrcPtr
+ * 		Source address to copy data from.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * 		This implemention MAY BREAK work if source and target memory
+ * 		area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+	memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	Data
+ * 		Value to set.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+	memset((void *) DestPtr, (int) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef int XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * <br><br>
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param	delay
+ * 		Number of microseconds to delay.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay)	usleep(delay)
+#define udelay(delay)	usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE()	\
+		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE()	\
+		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+#  define XCACHE_ENABLE_DCACHE()		microblaze_enable_dcache()
+#  define XCACHE_DISABLE_DCACHE()		microblaze_disable_dcache()
+#  define XCACHE_INVALIDATE_DCACHE()  	microblaze_invalidate_dcache()
+
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((int)(Addr), (int)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_flush_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_flush_dcache_range((int)(Addr), (int)(Len))
+#else
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_invalidate_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((int)(Addr), (int)(Len))
+#endif	/*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+#  define XCACHE_ENABLE_DCACHE()
+#  define XCACHE_DISABLE_DCACHE()
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif	/*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+#  define XCACHE_ENABLE_ICACHE()		microblaze_enable_icache()
+#  define XCACHE_DISABLE_ICACHE()		microblaze_disable_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE()  	microblaze_invalidate_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_icache_range((int)(Addr), (int)(Len))
+
+#else
+#  define XCACHE_ENABLE_ICACHE()
+#  define XCACHE_DISABLE_ICACHE()
+#endif	/*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ *   Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ *   specific memory region (0x80000001). Each bit (0-30) in the regions
+ *   bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ *   range.
+ *
+ *   regions    --> cached address range
+ *   ------------|--------------------------------------------------
+ *   0x80000000  | [0, 0x7FFFFFF]
+ *   0x00000001  | [0xF8000000, 0xFFFFFFFF]
+ *   0x80000001  | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE()		XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE()		XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE()		XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE()		XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+		XCache_InvalidateDCacheRange((unsigned int)(Addr), (unsigned)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+		XCache_FlushDCacheRange((unsigned int)(Addr), (unsigned)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE()	XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* #ifndef XENV_STANDALONE_H */
+
+/** @} */

thirdparty/xilinx/include/xilinx/xenv_vxworks.h

@@ -0,0 +1,272 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_vxworks.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* 	This file is not intended to be included directly by driver code.
+* 	Instead, the generic xenv.h file is intended to be included by driver
+* 	code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+*       rmm  09/13/03 CR 177068: Fix compiler warning in XENV_MEM_FILL
+*       rmm  10/24/02 Added XENV_USLEEP macro
+* 1.00a rmm  07/16/01 First release
+* 1.10a wgr  03/22/07 Converted to new coding style.
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XENV_VXWORKS_H
+#define XENV_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+#include <string.h>
+
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	SrcPtr
+ * 		Source address to copy data from.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note	XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+	memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	Data
+ * 		Value to set.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note	XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+	memset((void *) DestPtr, (int) Data, (size_t) Bytes)
+
+
+#if (CPU_FAMILY==PPC)
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef struct
+{
+	u32 TimeBaseUpper;
+	u32 TimeBaseLower;
+} XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)                   \
+{                                                       \
+    vxTimeBaseGet((UINT32*)&(StampPtr)->TimeBaseUpper,  \
+                  (UINT32*)&(StampPtr)->TimeBaseLower); \
+}
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note    None.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * None.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
+
+
+/* For non-PPC systems the above macros are not defined. Generate a error to
+ * make the developer aware of the problem.
+ */
+#else
+#error "XENV_TIME_STAMP_GET used in a non-PPC system. Aborting."
+#endif
+
+
+/*****************************************************************************/
+/**
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param	delay
+ * 		Number of microseconds to delay.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#define XENV_USLEEP(delay)	sysUsDelay(delay)
+
+#define udelay(delay)	sysUsDelay(delay)
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ ******************************************************************************/
+
+#if (CPU_FAMILY==PPC)
+
+#define XCACHE_ENABLE_CACHE()	\
+		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE()	\
+		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+#define XCACHE_ENABLE_DCACHE()		cacheEnable(DATA_CACHE)
+#define XCACHE_DISABLE_DCACHE()		cacheDisable(DATA_CACHE)
+#define XCACHE_ENABLE_ICACHE()		cacheEnable(INSTRUCTION_CACHE)
+#define XCACHE_DISABLE_ICACHE()		cacheDisable(INSTRUCTION_CACHE)
+
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+		cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+		cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+		cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+#define XCACHE_FLUSH_ICACHE_RANGE(Addr, Len) \
+		cacheFlush(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* #ifdef XENV_VXWORKS_H */
+
+/** @} */

thirdparty/xilinx/include/xilinx/xil_assert.h

@@ -0,0 +1,85 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* This file contains assert related functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H	/* prevent circular inclusions */
+#define XIL_ASSERT_H	/* by using protection macros */
+
+#include <assert.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define Xil_AssertVoid(expr)                                            \
+  ((expr)                                                               \
+   ? __ASSERT_VOID_CAST (0)                                             \
+   : __assert_fail (__STRING(expr), __FILE__, __LINE__, __ASSERT_FUNCTION))
+#define Xil_AssertNonvoid(expr)                                         \
+  ((expr)                                                               \
+   ? __ASSERT_VOID_CAST (0)                                             \
+   : __assert_fail (__STRING(expr), __FILE__, __LINE__, __ASSERT_FUNCTION))
+#define Xil_AssertVoidAlways()                                          \
+  __assert_fail ("always", __FILE__, __LINE__, __ASSERT_FUNCTION)
+#define Xil_AssertNonvoidAlways()                                       \
+  __assert_fail ("always", __FILE__, __LINE__, __ASSERT_FUNCTION)
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */

thirdparty/xilinx/include/xilinx/xil_cache.h

@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* Contains dummies for cache related functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  12/11/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define Xil_DCacheEnable()
+#define Xil_DCacheDisable()
+#define Xil_DCacheInvalidateRange(Addr, Len)
+#define Xil_DCacheFlushRange(Addr, Len)
+#define Xil_ICacheEnable()
+#define Xil_ICacheDisable()
+#define Xil_ICacheInvalidateRange(Addr, Len)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

thirdparty/xilinx/include/xilinx/xil_io.h

@@ -0,0 +1,246 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* This file contains the interface for the general IO component, which
+* encapsulates the Input/Output functions for processors that do not
+* require any special I/O handling.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/24/09 First release
+* 1.00a sdm      07/21/10 Added Xil_Htonl/s, Xil_Ntohl/s
+* 3.07a asa	     08/31/12 Added xil_printf.h include
+* 3.08a sgd	     11/05/12 Reverted SYNC macros definitions
+* </pre>
+******************************************************************************/
+
+#ifndef XIL_IO_H           /* prevent circular inclusions */
+#define XIL_IO_H           /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+//#include "xpseudo_asm.h"
+#include "xil_printf.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#if 0
+#  define SYNCHRONIZE_IO	dmb()
+#  define INST_SYNC		isb()
+#  define DATA_SYNC		dsb()
+#else
+#  define SYNCHRONIZE_IO
+#  define INST_SYNC
+#  define DATA_SYNC
+#endif /* __GNUC__ */
+
+/*****************************************************************************/
+/**
+*
+* Perform an big-endian input operation for a 16-bit memory location
+* by reading from the specified address and returning the Value read from
+* that address.
+*
+* @param	Addr contains the address to perform the input operation at.
+*
+* @return	The Value read from the specified input address with the
+*		proper endianness. The return Value has the same endianness
+*		as that of the processor, i.e. if the processor is
+*		little-engian, the return Value is the byte-swapped Value read
+*		from the address.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_In16LE(Addr) Xil_In16((Addr))
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian input operation for a 32-bit memory location
+* by reading from the specified address and returning the Value read from
+* that address.
+*
+* @param	Addr contains the address to perform the input operation at.
+*
+* @return	The Value read from the specified input address with the
+*		proper endianness. The return Value has the same endianness
+*		as that of the processor, i.e. if the processor is
+*		little-engian, the return Value is the byte-swapped Value read
+*		from the address.
+*
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_In32LE(Addr) Xil_In32((Addr))
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian output operation for a 16-bit memory location
+* by writing the specified Value to the specified address.
+*
+* @param	Addr contains the address to perform the output operation at.
+* @param	Value contains the Value to be output at the specified address.
+*		The Value has the same endianness as that of the processor.
+*		If the processor is little-endian, the byte-swapped Value is
+*		written to the address.
+*
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value))
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian output operation for a 32-bit memory location
+* by writing the specified Value to the specified address.
+*
+* @param	Addr contains the address to perform the output operation at.
+* @param	Value contains the Value to be output at the specified address.
+*		The Value has the same endianness as that of the processor.
+*		If the processor is little-endian, the byte-swapped Value is
+*		written to the address.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 32-bit number from host byte order to network byte order.
+*
+* @param	Data the 32-bit number to be converted.
+*
+* @return	The converted 32-bit number in network byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Htonl(Data) Xil_EndianSwap32((Data))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 16-bit number from host byte order to network byte order.
+*
+* @param	Data the 16-bit number to be converted.
+*
+* @return	The converted 16-bit number in network byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Htons(Data) Xil_EndianSwap16((Data))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 32-bit number from network byte order to host byte order.
+*
+* @param	Data the 32-bit number to be converted.
+*
+* @return	The converted 32-bit number in host byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Ntohl(Data) Xil_EndianSwap32((Data))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 16-bit number from network byte order to host byte order.
+*
+* @param	Data the 16-bit number to be converted.
+*
+* @return	The converted 16-bit number in host byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Ntohs(Data) Xil_EndianSwap16((Data))
+
+/************************** Function Prototypes ******************************/
+
+/* The following functions allow the software to be transportable across
+ * processors which may use memory mapped I/O or I/O which is mapped into a
+ * seperate address space.
+ */
+u8 Xil_In8(INTPTR Addr);
+u16 Xil_In16(INTPTR Addr);
+u32 Xil_In32(INTPTR Addr);
+
+void Xil_Out8(INTPTR Addr, u8 Value);
+void Xil_Out16(INTPTR Addr, u16 Value);
+void Xil_Out32(INTPTR Addr, u32 Value);
+
+
+u16 Xil_In16BE(INTPTR Addr);
+u32 Xil_In32BE(INTPTR Addr);
+void Xil_Out16BE(INTPTR Addr, u16 Value);
+void Xil_Out32BE(INTPTR Addr, u32 Value);
+
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */

thirdparty/xilinx/include/xilinx/xil_printf.h

@@ -0,0 +1,43 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <ctype.h>
+#include <string.h>
+#include <stdarg.h>
+#include <stdio.h>
+#include "xil_types.h"
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to   */
+/* make xil_printf re-entrant.                        */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+#define xil_printf(fmt, ...)	printf(fmt, ##__VA_ARGS__)
+#define print(ptr)		printf("%s", ptr)
+
+#define outbyte(byte)		putc(byte, stdout)
+#define inbyte();		getc(stdin)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */

thirdparty/xilinx/include/xilinx/xil_types.h

@@ -0,0 +1,200 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* This file contains basic types for Xilinx software IP.
+
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 	pkp  05/29/14 Made changes for 64 bit architecture
+*	srt  07/14/14 Use standard definitions from stdint.h and stddef.h
+*		      Define LONG and ULONG datatypes and mask values
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H	/* prevent circular inclusions */
+#define XIL_TYPES_H	/* by using protection macros */
+
+#include <stdint.h>
+#include <stddef.h>
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#define XIL_COMPONENT_IS_READY     0x11111111U  /**< component has been initialized */
+#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< component has been started */
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/**
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+
+#define __XUINT64__
+typedef struct
+{
+	u32 Upper;
+	u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* Return the most significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The upper 32 bits of the 64 bit word.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* Return the least significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The lower 32 bits of the 64 bit word.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/**
+ * xbasic_types.h does not typedef s* or u64
+ */
+
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK	0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK	~ULONG64_HI_MASK
+
+#else
+#include <linux/types.h>
+#endif
+
+
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * UPPER_32_BITS - return bits 32-63 of a number
+ * @n: the number we're accessing
+ *
+ * A basic shift-right of a 64- or 32-bit quantity.  Use this to suppress
+ * the "right shift count >= width of type" warning when that quantity is
+ * 32-bits.
+ */
+#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * LOWER_32_BITS - return bits 0-31 of a number
+ * @n: the number we're accessing
+ */
+#define LOWER_32_BITS(n) ((u32)(n))
+
+/*@}*/
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE		1U
+#endif
+
+#ifndef FALSE
+#define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#endif	/* end of protection macro */

thirdparty/xilinx/include/xilinx/xintc.h

@@ -0,0 +1,370 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xintc.h
+* @addtogroup intc_v3_4
+* @{
+* @details
+*
+* The Xilinx interrupt controller driver component. This component supports the
+* Xilinx interrupt controller.
+*
+* The interrupt controller driver uses the idea of priority for the various
+* handlers. Priority is an integer within the range of 0 and 31 inclusive with
+* 0 being the highest priority interrupt source.
+*
+* The Xilinx interrupt controller supports the following features:
+*
+*   - specific individual interrupt enabling/disabling
+*   - specific individual interrupt acknowledging
+*   - attaching specific callback function to handle interrupt source
+*   - master enable/disable
+*   - single callback per interrupt or all pending interrupts handled for
+*     each interrupt of the processor
+*
+* The acknowledgement of the interrupt within the interrupt controller is
+* selectable, either prior to the device's handler being called or after
+* the handler is called. This is necessary to support interrupt signal inputs
+* which are either edge or level signals.  Edge driven interrupt signals
+* require that the interrupt is acknowledged prior to the interrupt being
+* serviced in order to prevent the loss of interrupts which are occurring
+* extremely close together.  A level driven interrupt input signal requires
+* the interrupt to acknowledged after servicing the interrupt to ensure that
+* the interrupt only generates a single interrupt condition.
+*
+* Details about connecting the interrupt handler of the driver are contained
+* in the source file specific to interrupt processing, xintc_intr.c.
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* <b>Interrupt Vector Tables</b>
+*
+* The interrupt vector table for each interrupt controller device is declared
+* statically in xintc_g.c within the configuration data for each instance.
+* The device ID of the interrupt controller device is used by the driver as a
+* direct index into the configuration data table - to retrieve the vector table
+* for an instance of the interrupt controller. The user should populate the
+* vector table with handlers and callbacks at run-time using the XIntc_Connect()
+* and XIntc_Disconnect() functions.
+*
+* Each vector table entry corresponds to a device that can generate an
+* interrupt. Each entry contains an interrupt handler function and an argument
+* to be passed to the handler when an interrupt occurs.  The tools default this
+* argument to the base address of the interrupting device.  Note that the
+* device driver interrupt handlers given in this file do not take a base
+* address as an argument, but instead take a pointer to the driver instance.
+* This means that although the table is created statically, the user must still
+* use XIntc_Connect() when the interrupt handler takes an argument other than
+* the base address. This is only to say that the existence of the static vector
+* tables should not mislead the user into thinking they no longer need to
+* register/connect interrupt handlers with this driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm  08/16/01 First release
+* 1.00a rpm  01/09/02 Removed the AckLocation argument from XIntc_Connect().
+*                     This information is now internal in xintc_g.c.
+* 1.00b jhl  02/13/02 Repartitioned the driver for smaller files
+* 1.00b jhl  04/24/02 Made LookupConfig function global and relocated config
+*                     data type
+* 1.00c rpm  10/17/03 New release. Support the static vector table created
+*                     in the xintc_g.c configuration table. Moved vector
+*                     table and options out of instance structure and into
+*                     the configuration table.
+* 1.10c mta  03/21/07 Updated to new coding style
+* 1.11a sv   11/21/07 Updated driver to support access through a DCR bridge
+* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs and _m is removed from
+*		      all the macro names/definitions.
+* 2.01a sdm  04/27/10 Updated the tcl so that the defintions are generated in
+*		      the xparameters.h to know whether the optional registers
+*		      SIE, CIE and IVR are enabled in the HW - Refer CR 555392.
+*		      This driver doesnot make use of these definitions and does
+*		      not use the optional registers.
+* 2.03a hvm  05/24/11 Updated the tcl to generate vector Ids for external
+*		      interrupts. CR565336
+* 2.04a bss  01/13/12 Added XIntc_ConnectFastHandler API for Fast Interrupt
+*		      and XIntc_SetNormalIntrMode for setting to normal
+*		      interrupt mode.
+* 2.04a asa  03/19/12 Changed the XIntc_Config struct. The order of entries
+*		      declared in the structure now matches with the
+*		      XIntc_ConfigTable generated by the driver tcl.
+* 2.05a bss  08/16/12 Updated to support relocatable vectors in Microblaze,
+*		      added IntVectorAddr to XIntc_Config for this.
+*		      Added XIntc_RegisterFastHandler API to register fast
+*		      interrupt handlers using base address.
+* 2.06a bss  01/28/13 To support Cascade mode:
+* 		      Added XIN_INTC_NOCASCADE,XIN_INTC_PRIMARY,
+*		      XIN_INTC_SECONDARY,XIN_INTC_LAST and
+*		      XIN_CONTROLLER_MAX_INTRS  macros
+*		      Added NumberofIntrs and IntcType fields in XIntc_Config
+*		      structure.
+*		      Modified XIntc_Initialize,XIntc_Start,XIntc_Connect
+*		      XIntc_Disconnect,XIntc_Enable,XIntc_Disable,
+*		      XIntc_Acknowledge,XIntc_ConnectFastHandler and
+*		      XIntc_SetNormalIntrMode APIs.Added XIntc_InitializeSlaves
+*		      API in xintc.c
+*  		      Modified XIntc_DeviceInterruptHandler,
+*  		      XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
+*		      XIntc_RegisterFastHandler APIs.Added XIntc_CascadeHandler
+*		      API in xintc_l.c.
+*		      Modified XIntc_SetOptions API in xintc_options.c.
+*		      Modified XIntc_SimulateIntr API in xintc_selftest.c.
+*		      Modified driver tcl:
+*			to check for Cascade mode and generate XPAR_INTC_TYPE
+*			for each controller.
+*			Generate XPAR_INTC_MAX_NUM_INTR_INPUTS by adding all
+*			interrupt sources of all Controllers in Cascade mode.
+* 2.07a bss  10/18/13 To support Nested interrupts:
+*		      Modified XIntc_DeviceInterruptHandler API.
+*		      Added XIN_ILR_OFFSET macro in xintc_l.h.
+*		      Modified driver tcl to generate HAS_ILR parameter in
+*		      xparameters.h
+* 3.0   bss  01/28/13 Modified xintc.c to initialize IVAR register with
+*		      XPAR_MICROBLAZE_BASE_VECTORS + 0x10 to fix
+*		      CR#765931.
+*		      Modified driver tcl to generate XPAR_AXI_INTC_0_TYPE
+*		      correctly(CR#764865).
+*
+* @note
+*		For Cascade mode, Interrupt IDs are generated in xparameters.h
+*		as shown below:
+*
+*	    Master/Primary INTC
+*		 ______
+*		|      |-0      Secondary INTC
+*		|      |-.         ______
+*		|      |-.        |      |-32        Last INTC
+*		|      |-.        |      |-.          ______
+*		|______|<-31------|      |-.         |      |-64
+*			          |      |-.         |      |-.
+*			          |______|<-63-------|      |-.
+*                                                    |      |-.
+*                                                    |______|-95
+*
+*		All driver functions has to be called using DeviceId/
+*		InstancePtr/BaseAddress of Primary/Master Controller and
+*		Interrupts IDs generated in xparameters.h only.
+*		Driver functions takes care of Slave Controllers based on
+*		Interrupt ID passed. User must not use Interrupt source/ID
+*		31 of Primary and Secondary controllers to call driver
+*		functions.
+*
+*		For nested interrupts, XIntc_DeviceInterruptHandler saves
+*		microblaze r14 register on entry and restores on exit. This is
+*		required since compiler does not support nesting. It enables
+*		Microblaze interrupts after blocking further interrupts from
+*		the current interrupt number and interrupts below current
+*		interrupt proirity by writing to Interrupt Level Register of
+*		INTC on entry. On exit, it disables microblaze interrupts and
+*		restores ILR register default value(0xFFFFFFFF)back. It is
+*		recommended to increase STACK_SIZE in linker script for nested
+*		interrupts.
+* 3.0     adk    12/10/13  Updated as per the New Tcl API's
+* 3.0 	  adk 	 17/02/14  Fixed the CR:771287 Changes are made in the intc
+* 		           driver tcl.
+* 3.1     adk    8/4/14    Fixed the CR:783248 Changes are made in
+*			   the test-app tcl
+* 3.2     bss    4/8/14    Fixed driver tcl to handle external interrupt pins
+*			   correctly (CR#799609).
+* 3.3     adk    11/3/14   added generation of C_HAS_ILR parameter to
+*			   xparameters.h.Changes are made in the driver tcl file
+*			   (CR#828046).
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XINTC_H			/* prevent circular inclusions */
+#define XINTC_H			/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xstatus.h"
+#include "xintc_l.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * @name Configuration options
+ * These options are used in XIntc_SetOptions() to configure the device.
+ * @{
+ */
+/**
+ * <pre>
+ * XIN_SVC_SGL_ISR_OPTION	Service the highest priority pending interrupt
+ *				and then return.
+ * XIN_SVC_ALL_ISRS_OPTION	Service all of the pending interrupts and then
+ *				return.
+ * </pre>
+ */
+#define XIN_SVC_SGL_ISR_OPTION  1UL
+#define XIN_SVC_ALL_ISRS_OPTION 2UL
+/*@}*/
+
+/**
+ * @name Start modes
+ * One of these values is passed to XIntc_Start() to start the device.
+ * @{
+ */
+/** Simulation only mode, no hardware interrupts recognized */
+#define XIN_SIMULATION_MODE     0
+/** Real mode, no simulation allowed, hardware interrupts recognized */
+#define XIN_REAL_MODE           1
+/*@}*/
+
+/**
+ * @name Masks to specify Interrupt Controller Mode
+ * @{
+ */
+#define XIN_INTC_NOCASCADE     	0	/* Normal - No Cascade Mode */
+#define XIN_INTC_PRIMARY     	1	/* Master/Primary controller */
+#define XIN_INTC_SECONDARY     	2	/* Secondary Slave Controllers */
+#define XIN_INTC_LAST     	3	/* Last Slave Controller */
+
+/*@}*/
+
+/**
+ * @name Mask to specify maximum number of interrupt sources per controller
+ * @{
+ */
+#define XIN_CONTROLLER_MAX_INTRS	32  /* Each Controller has 32
+					       interrupt pins */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 BaseAddress;	/**< Register base address */
+	u32 AckBeforeService;	/**< Ack location per interrupt */
+	int FastIntr;		/**< Fast Interrupt enabled */
+	u32 IntVectorAddr;	/**< Interrupt Vector Address */
+	int NumberofIntrs;      /**< Number of Interrupt sources */
+	u32 Options;		/**< Device options */
+	int IntcType;		/**< Intc type 0 - No Cascade Mode
+				               1 - primary instance
+				               2 - secondary instance
+				               3 - last instance */
+
+/** Static vector table of interrupt handlers */
+#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
+	XIntc_VectorTableEntry HandlerTable[XIN_CONTROLLER_MAX_INTRS];
+#else
+	XIntc_VectorTableEntry HandlerTable[XPAR_INTC_MAX_NUM_INTR_INPUTS];
+#endif
+
+} XIntc_Config;
+
+/**
+ * The XIntc driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	u32 BaseAddress;	 /**< Base address of registers */
+	u32 IsReady;		 /**< Device is initialized and ready */
+	u32 IsStarted;		 /**< Device has been started */
+	u32 UnhandledInterrupts; /**< Intc Statistics */
+	XIntc_Config *CfgPtr;	 /**< Pointer to instance config entry */
+
+} XIntc;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xintc.c
+ */
+int XIntc_Initialize(XIntc * InstancePtr, u16 DeviceId);
+
+int XIntc_Start(XIntc * InstancePtr, u8 Mode);
+void XIntc_Stop(XIntc * InstancePtr);
+
+int XIntc_Connect(XIntc * InstancePtr, u8 Id,
+		  XInterruptHandler Handler, void *CallBackRef);
+void XIntc_Disconnect(XIntc * InstancePtr, u8 Id);
+
+void XIntc_Enable(XIntc * InstancePtr, u8 Id);
+void XIntc_Disable(XIntc * InstancePtr, u8 Id);
+
+void XIntc_Acknowledge(XIntc * InstancePtr, u8 Id);
+
+XIntc_Config *XIntc_LookupConfig(u16 DeviceId);
+
+int XIntc_ConnectFastHandler(XIntc *InstancePtr, u8 Id,
+				XFastInterruptHandler Handler);
+void XIntc_SetNormalIntrMode(XIntc *InstancePtr, u8 Id);
+
+/*
+ * Interrupt functions in xintr_intr.c
+ */
+void XIntc_VoidInterruptHandler(void);
+void XIntc_InterruptHandler(XIntc * InstancePtr);
+
+/*
+ * Options functions in xintc_options.c
+ */
+int XIntc_SetOptions(XIntc * InstancePtr, u32 Options);
+u32 XIntc_GetOptions(XIntc * InstancePtr);
+
+/*
+ * Self-test functions in xintc_selftest.c
+ */
+int XIntc_SelfTest(XIntc * InstancePtr);
+int XIntc_SimulateIntr(XIntc * InstancePtr, u8 Id);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */

thirdparty/xilinx/include/xilinx/xintc_l.h

@@ -0,0 +1,330 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xintc_l.h
+* @addtogroup intc_v3_4
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+*
+*
+* Note that users of the driver interface given in this file can register
+* an interrupt handler dynamically (at run-time) using the
+* XIntc_RegisterHandler() function.
+* User of the driver interface given in xintc.h should still use
+* XIntc_Connect(), as always.
+* Also see the discussion of the interrupt vector tables in xintc.h.
+*
+* There are currently two interrupt handlers specified in this interface.
+*
+* - XIntc_LowLevelInterruptHandler() is a handler without any arguments that
+*   is used in cases where there is a single interrupt controller device in
+*   the system and the handler cannot be passed an argument. This function is
+*   provided mostly for backward compatibility.
+*
+* - XIntc_DeviceInterruptHandler() is a handler that takes a device ID as an
+*   argument, indicating which interrupt controller device in the system is
+*   causing the interrupt - thereby supporting multiple interrupt controllers.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00b jhl  04/24/02 First release
+* 1.00c rpm  10/17/03 New release. Support the static vector table created
+*                     in the xintc_g.c configuration table.
+* 1.10c mta  03/21/07 Updated to new coding style
+* 1.11a sv   11/21/07 Updated driver to support access through a DCR bridge
+* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs. _m is removed from all
+*		      the macro definitions.
+* 2.04a bss  01/13/12 Updated for adding defines for IMR and IVAR for
+*                     the FAST Interrupt
+* 2.05a bss  08/18/12 Added XIntc_RegisterFastHandler API to register fast
+*		      interrupt handlers using base address.
+* 2.07a bss  10/18/13 Added XIN_ILR_OFFSET macro for nested interrupts.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XINTC_L_H		/* prevent circular inclusions */
+#define XINTC_L_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xil_io.h"
+
+/*
+ * XPAR_XINTC_USE_DCR_BRIDGE has to be set to 1 if the Intc device will be
+ * accessed through a DCR bus connected to a bridge.
+ */
+#define XPAR_XINTC_USE_DCR_BRIDGE 0
+
+#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
+#include "xio_dcr.h"
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/* define the offsets from the base address for all the registers of the
+ * interrupt controller, some registers may be optional in the hardware device
+ */
+#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
+
+#define XIN_ISR_OFFSET      0	/* Interrupt Status Register */
+#define XIN_IPR_OFFSET      1	/* Interrupt Pending Register */
+#define XIN_IER_OFFSET      2	/* Interrupt Enable Register */
+#define XIN_IAR_OFFSET      3	/* Interrupt Acknowledge Register */
+#define XIN_SIE_OFFSET      4	/* Set Interrupt Enable Register */
+#define XIN_CIE_OFFSET      5	/* Clear Interrupt Enable Register */
+#define XIN_IVR_OFFSET      6	/* Interrupt Vector Register */
+#define XIN_MER_OFFSET      7	/* Master Enable Register */
+#define XIN_IMR_OFFSET      8	/* Interrupt Mode Register , this is present
+				 *  only for Fast Interrupt */
+#define XIN_IVAR_OFFSET     64  /* Interrupt Vector Address Register
+				 * Interrupt 0 Offest, this is present
+				 * only for Fast Interrupt */
+
+#else /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */
+
+#define XIN_ISR_OFFSET      0	/* Interrupt Status Register */
+#define XIN_IPR_OFFSET      4	/* Interrupt Pending Register */
+#define XIN_IER_OFFSET      8	/* Interrupt Enable Register */
+#define XIN_IAR_OFFSET      12	/* Interrupt Acknowledge Register */
+#define XIN_SIE_OFFSET      16	/* Set Interrupt Enable Register */
+#define XIN_CIE_OFFSET      20	/* Clear Interrupt Enable Register */
+#define XIN_IVR_OFFSET      24	/* Interrupt Vector Register */
+#define XIN_MER_OFFSET      28	/* Master Enable Register */
+#define XIN_IMR_OFFSET      32	/* Interrupt Mode Register , this is present
+				 *  only for Fast Interrupt */
+#define XIN_ILR_OFFSET      36  /* Interrupt level register */
+#define XIN_IVAR_OFFSET     0x100 /* Interrupt Vector Address Register
+				   * Interrupt 0 Offest, this is present
+				   * only for Fast Interrupt */
+
+
+
+#endif /* ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0)) */
+
+/* Bit definitions for the bits of the MER register */
+
+#define XIN_INT_MASTER_ENABLE_MASK      0x1UL
+#define XIN_INT_HARDWARE_ENABLE_MASK    0x2UL	/* once set cannot be cleared */
+
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the driver interface given in this file and an instance pointer for the
+ * driver interface given in xintc.h file.
+ */
+typedef struct {
+	XInterruptHandler Handler;
+	void *CallBackRef;
+} XIntc_VectorTableEntry;
+
+typedef void (*XFastInterruptHandler) (void);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*
+ * Define the appropriate I/O access method to memory mapped I/O or DCR.
+ */
+#if ((XPAR_XINTC_USE_DCR != 0) || (XPAR_XINTC_USE_DCR_BRIDGE != 0))
+
+#define XIntc_In32  XIo_DcrIn
+#define XIntc_Out32 XIo_DcrOut
+
+#else
+
+#define XIntc_In32  Xil_In32
+#define XIntc_Out32 Xil_Out32
+
+#endif
+
+/****************************************************************************/
+/**
+*
+* Enable all interrupts in the Master Enable register of the interrupt
+* controller.  The interrupt controller defaults to all interrupts disabled
+* from reset such that this macro must be used to enable interrupts.
+*
+* @param	BaseAddress is the base address of the device.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XIntc_MasterEnable(u32 BaseAddress);
+*
+*****************************************************************************/
+#define XIntc_MasterEnable(BaseAddress) \
+	XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, \
+	XIN_INT_MASTER_ENABLE_MASK | XIN_INT_HARDWARE_ENABLE_MASK)
+
+/****************************************************************************/
+/**
+*
+* Disable all interrupts in the Master Enable register of the interrupt
+* controller.
+*
+* @param	BaseAddress is the base address of the device.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XIntc_MasterDisable(u32 BaseAddress);
+*
+*****************************************************************************/
+#define XIntc_MasterDisable(BaseAddress) \
+	XIntc_Out32((BaseAddress) + XIN_MER_OFFSET, 0)
+
+/****************************************************************************/
+/**
+*
+* Enable specific interrupt(s) in the interrupt controller.
+*
+* @param	BaseAddress is the base address of the device
+* @param	EnableMask is the 32-bit value to write to the enable register.
+*		Each bit of the mask corresponds to an interrupt input signal
+*		that is connected to the interrupt controller (INT0 = LSB).
+*		Only the bits which are set in the mask will enable interrupts.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XIntc_EnableIntr(u32 BaseAddress, u32 EnableMask);
+*
+*****************************************************************************/
+#define XIntc_EnableIntr(BaseAddress, EnableMask) \
+	XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))
+
+/****************************************************************************/
+/**
+*
+* Disable specific interrupt(s) in the interrupt controller.
+*
+* @param	BaseAddress is the base address of the device
+* @param	DisableMask is the 32-bit value to write to the enable register.
+*		Each bit of the mask corresponds to an interrupt input signal
+*		that is connected to the interrupt controller (INT0 = LSB).
+*		Only the bits which are set in the mask will disable interrupts.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XIntc_DisableIntr(u32 BaseAddress, u32 DisableMask);
+*
+*****************************************************************************/
+#define XIntc_DisableIntr(BaseAddress, DisableMask) \
+	XIntc_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))
+
+/****************************************************************************/
+/**
+*
+* Acknowledge specific interrupt(s) in the interrupt controller.
+*
+* @param	BaseAddress is the base address of the device
+* @param	AckMask is the 32-bit value to write to the acknowledge
+*		register. Each bit of the mask corresponds to an interrupt input
+*		signal that is connected to the interrupt controller (INT0 =
+*		LSB).  Only the bits which are set in the mask will acknowledge
+*		interrupts.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XIntc_AckIntr(u32 BaseAddress, u32 AckMask);
+*
+*****************************************************************************/
+#define XIntc_AckIntr(BaseAddress, AckMask) \
+	XIntc_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))
+
+/****************************************************************************/
+/**
+*
+* Get the interrupt status from the interrupt controller which indicates
+* which interrupts are active and enabled.
+*
+* @param	BaseAddress is the base address of the device
+*
+* @return	The 32-bit contents of the interrupt status register. Each bit
+*		corresponds to an interrupt input signal that is connected to
+*		the interrupt controller (INT0 = LSB). Bits which are set
+*		indicate an active interrupt which is also enabled.
+*
+* @note		C-style signature:
+*		u32 XIntc_GetIntrStatus(u32 BaseAddress);
+*
+*****************************************************************************/
+#define XIntc_GetIntrStatus(BaseAddress) \
+	(XIntc_In32((BaseAddress) + XIN_ISR_OFFSET) & \
+	XIntc_In32((BaseAddress) + XIN_IER_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Interrupt controller handlers, to be connected to processor exception
+ * handling code.
+ */
+void XIntc_LowLevelInterruptHandler(void);
+void XIntc_DeviceInterruptHandler(void *DeviceId);
+
+/* Various configuration functions */
+void XIntc_SetIntrSvcOption(u32 BaseAddress, int Option);
+
+void XIntc_RegisterHandler(u32 BaseAddress, int InterruptId,
+			   XInterruptHandler Handler, void *CallBackRef);
+
+void XIntc_RegisterFastHandler(u32 BaseAddress, u8 Id,
+					XFastInterruptHandler FastHandler);
+
+/************************** Variable Definitions *****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */

thirdparty/xilinx/include/xilinx/xllfifo.h

@@ -0,0 +1,715 @@
+/******************************************************************************
+*
+* Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xllfifo.h
+* @addtogroup llfifo_v5_0
+* @{
+* @details
+ *
+ * The Xilinx Dual Channel Fifo driver component. This driver supports the
+ * Virtex-5(TM) and Virtex-4(TM) XPS_ll_Fifo and the AxiFifo.
+ *
+ * For a full description of the bridge features, please see the HW spec. This
+ * driver supports the following features:
+ *   - Memory mapped access to host interface registers
+ *   - API for polled frame transfers
+ *   - API for interrupt driven frame transfers
+ *   - Virtual memory support
+ *   - Full duplex operation
+ *
+ * <h2>Driver Description</h2>
+ *
+ * This driver enables higher layer software to access the XPS_llFifo core
+ * using any alignment in the data buffers.
+ *
+ * This driver supports send and receive channels in the same instance
+ * structure in the same fashion as the hardware core.
+ *
+ * <h2>Initialization</h2>
+ *
+ * An instance of this driver is initialized using a call to Initialize().
+ *
+ * <h2>Usage</h2>
+ *
+ * It is fairly simple to use the API provided by this FIFO driver. The
+ * only somewhat tricky part is that the calling code must correctly call
+ * a couple routines in the right sequence for receive and transmit.
+ *
+ * This sequence is described here. Check the routine functional
+ * descriptions for information on how to use a specific API routine.
+ *
+ * <h3>Receive</h3>
+ *
+ * A frame is received by using the following sequence:<br>
+ * 1) call XLlFifo_RxOccupancy() to check the occupancy count<br>
+ * 2) call XLlFifo_RxGetLen() to get the length of the next incoming frame<br>
+ * 3) call XLlFifo_Read() one or more times to read the number of bytes
+ *    reported by XLlFifo_RxGetLen().<br>
+ *
+ * For example:
+ * <pre>
+ * 	while (XLlFifo_RxOccupancy(&RxInstance)) {
+ * 		frame_len = XLlFifo_RxGetLen(&RxInstance);
+ *		while (frame_len) {
+ * 			unsigned bytes = min(sizeof(buffer), frame_len);
+ * 			XLlFifo_Read(&RxInstance, buffer, bytes);
+ * 			// ********
+ * 			// do something with buffer here
+ * 			// ********
+ * 			frame_len -= bytes;
+ *		}
+ * 	}
+ * </pre>
+ *
+ * This FIFO hardware core does <b>not</b> support a sequence where the
+ * calling code calls RxGetLen() twice in a row and then receive the data
+ * for two frames. Each frame must be read in by calling RxGetLen() just
+ * prior to reading the data.
+ *
+ * <h3>Transmit</h3>
+ * A frame is transmittted by using the following sequence:<br>
+ * 1) call XLlFifo_Write() one or more times to write all the of bytes in
+ *    the next frame.<br>
+ * 2) call XLlFifo_TxSetLen() to begin the transmission of frame just
+ *    written.<br>
+ *
+ * For example:
+ * <pre>
+ * 	frame_left = frame_len;
+ * 	while (frame_left) {
+ * 		unsigned bytes = min(sizeof(buffer), frame_left);
+ * 		XLlFifo_Write(&TxInstance, buffer, bytes);
+ * 		// ********
+ * 		// do something here to refill buffer
+ * 		// ********
+ * 		frame_left -= bytes;
+ * 	}
+ * 	XLlFifo_TxSetLen(&RxInstance, frame_len);
+ * </pre>
+ *
+ * This FIFO hardware core does <b>not</b> support a sequence where the
+ * calling code writes the data for two frames and then calls TxSetLen()
+ * twice in a row. Each frame must be written by writting the data for one
+ * frame and then calling TxSetLen().
+ *
+ * <h2>Interrupts</h2>
+ * This driver does not handle interrupts from the FIFO hardware. The
+ * software layer above may make use of the interrupts by setting up its
+ * own handlers for the interrupts.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a jvb  10/12/06 First release
+ * 1.01a sdm  08/22/08 Removed support for static interrupt handlers from the
+ *		       MDD file
+ * 1.02a jz   12/04/09 Hal phase 1 support
+ * 2.01a asa  09/17/10 Added code for resetting Local Link/AXI Streaming
+ *		       interface for CR574868
+ * 2.02a asa  12/27/11 Changed the function XStrm_Read in xtreamer.c to reset
+ *		       HeadIndex to zero when all bytes have been read.
+ *		       Changed the macro XStrm_IsRxInternalEmpty in file
+ *		       xtreamer.h to use FrmByteCnt instead of HeadIndex.
+ *		       When FrmByteCnt is zero, this means all internal buffers
+ *		       in streamer are empty. Earlier implementation using
+ *		       HeadIndex was not very clear and could give improper
+ *		       results for some cases.
+ *		       Changed the macro XLlFifo_IsRxEmpty in file xllfifo.h
+ *		       These changes are done to fix the CR 604650.
+  * 2.03a asa  14/08/12  Added XLLF_TDR_OFFSET, XLLF_RDR_OFFSET
+ *		         defines for the new registers, and XLLF_INT_TFPF_MASK,
+ *		         XLLF_INT_TFPE_MASK, XLLF_INT_RFPF_MASK and
+ *		         XLLF_INT_RFPE_MASK for the new version of the
+ *		         AXI4-Stream FIFO core (v2.01a and later)
+ *
+ * 3.00a adk 08/10/13 Added support for AXI4 Datainterface.Changes are
+ * 		      In Xllfifo.c file XLlFifo_RxGetWord,XLlFifo_TxPutword.
+ * 		      In XLlfifo.h file updated XLlfifo structure for
+ * 		      Axi4BaseAddress and for Datainterface type provided
+ *		      polling and interrupt examples. XLlfifo_IsRxDone Macro
+ *		      Is added in the XLlfifo.h file for polledmode exmaple.
+ *		      Added Static initialzation for the driver.
+ *		      XLlFifo_Initialize is still used to make the driver
+ *		      backward compatible.
+ * 4.0   adk  19/12/13 Updated as per the New Tcl API's
+ * 5.0   adk  15/05/15 Updated the register offsets in the AXI4 data path
+ *		       as per latest IP version(v4.1)(CR:860254).
+ *
+ * </pre>
+ *
+ *****************************************************************************/
+#ifndef XLLFIFO_H		/* prevent circular inclusions */
+#define XLLFIFO_H		/* by using preprocessor symbols */
+
+/* force C linkage */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+/* This order needs to be kept this way to avoid xstatus/xil_types conflict */
+#include "xstreamer.h"
+#include "xllfifo_hw.h"
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef defines a run-time instance of an XLlFifo device.
+ */
+typedef struct XLlFifo {
+	u32 BaseAddress;  /**< BaseAddress is the physical base address of the
+	                   *   device's registers
+	                   */
+
+	u32 IsReady;           /**< IsReady is non-zero if the driver instance
+	                        *   has been initialized.
+	                        */
+
+	u32 Axi4BaseAddress;	/**< BaseAddress if the FIFO Data interface is
+				 *	AXI4 this address should use for FIFO
+				 *	access
+				 */
+	u32 Datainterface;	/**< Data interface of the FIFO. This value is zero
+				 *	if the Datainterface is AXI4-lite.
+				 */
+	XStrm_RxFifoStreamer RxStreamer; /**< RxStreamer is the byte streamer
+	                                  *   instance for the receive channel.
+	                                  */
+	XStrm_TxFifoStreamer TxStreamer; /**< TxStreamer is the byte streamer
+	                                  *   instance for the transmit channel.
+	                                  */
+} XLlFifo;
+
+typedef struct XLlFifo_Config {
+	u32 DeviceId;		/**< Deviceid of the AXI FIFO */
+	u32 BaseAddress;	/**< Base Address of the AXI FIFO */
+	u32 Axi4BaseAddress;    /**< Axi4 interface Base address */
+	u32 Datainterface;	/**< Type of Datainterface */
+}XLlFifo_Config;
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_Reset resets both the Tx and Rx channels and the local link interface
+* the FIFO specified by <i>InstancePtr</i>. XLlFifo_TxReset resets also sends a
+* reset pulse to the downstream device (e.g. TEMAC). XLlFifo_Reset drops any
+* bytes in the FIFO not yet retrieved. XLlFifo_Reset drops any bytes in the FIFO
+* not yet transmitted.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_Reset(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_Reset(InstancePtr) \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_LLR_OFFSET, \
+			XLLF_LLR_RESET_MASK)
+
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_Status returns a bit mask of the interrupt status register (ISR)
+* for the FIFO specified by <i>InstancePtr</i>. XLlFifo_Status can be used
+* to query the status of the FIFO without having to have interrupts enabled.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_IntStatus returns a bit mask of the status conditions.
+*           The mask will be a set of bitwise or'd values from the
+*           <code>XLLF_INT_*_MASK</code> preprocessor symbols.
+*
+* @note
+* C-style signature:
+*    u32 XLlFifo_IntStatus(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_Status(InstancePtr) \
+	 XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IntEnable enables the interrupts specified in <i>Mask</i> for the
+* FIFO specified by <i>InstancePtr</i>. The corresponding interrupt for each bit
+* set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    Mask contains a bit mask of the interrupts to enable. The mask
+*           can be formed using a set of bitwise or'd values from the
+*           <code>XLLF_INT_*_MASK</code> preprocessor symbols.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_IntEnable(XLlFifo *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XLlFifo_IntEnable(InstancePtr, Mask) \
+{ \
+	u32 Reg = XLlFifo_ReadReg((InstancePtr)->BaseAddress, \
+			XLLF_IER_OFFSET); \
+	Reg |= ((Mask) & XLLF_INT_ALL_MASK);                    \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET, \
+			Reg); \
+}
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IntDisable disables the interrupts specified in <i>Mask</i> for the
+* FIFO specified by <i>InstancePtr</i>. The corresponding interrupt for each bit
+* set to 1 in <i>Mask</i>, will be disabled. In other words, XLlFifo_IntDisable
+* uses the "set a bit to clear it" scheme.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    Mask contains a bit mask of the interrupts to disable. The mask
+*           can be formed using a set of bitwise or'd values from the
+*           <code>XLLF_INT_*_MASK</code> preprocessor symbols.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_IntDisable(XLlFifo *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XLlFifo_IntDisable(InstancePtr, Mask) \
+{ \
+	u32 Reg = XLlFifo_ReadReg((InstancePtr)->BaseAddress, \
+			XLLF_IER_OFFSET); \
+	Reg &= ~((Mask) & XLLF_INT_ALL_MASK);  \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET, \
+			Reg); \
+}
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IntPending returns a bit mask of the pending interrupts for the
+* FIFO specified by <i>InstancePtr</i>. Each bit set to 1 in the return value
+* represents a pending interrupt.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_IntPending returns a bit mask of the interrupts that are
+*           pending. The mask will be a set of bitwise or'd values from the
+*           <code>XLLF_INT_*_MASK</code> preprocessor symbols.
+*
+* @note
+* C-style signature:
+*    u32 XLlFifo_IntPending(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#ifdef DEBUG
+extern u32 _xllfifo_ipie_value;
+extern u32 _xllfifo_ipis_value;
+#define XLlFifo_IntPending(InstancePtr) \
+	(_xllfifo_ipie_value = XLlFifo_ReadReg( \
+		(InstancePtr)->BaseAddress, XLLF_IER_OFFSET),  \
+	_xllfifo_ipis_value = XLlFifo_ReadReg( \
+		(InstancePtr)->BaseAddress, XLLF_ISR_OFFSET),  \
+	(_xllfifo_ipie_value & _xllfifo_ipis_value))
+#else
+#define XLlFifo_IntPending(InstancePtr) \
+	(XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET) &  \
+	 XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET))
+#endif
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IntClear clears pending interrupts specified in <i>Mask</i> for the
+* FIFO specified by <i>InstancePtr</i>. The corresponding pending interrupt for
+* each bit set to 1 in <i>Mask</i>, will be cleared. In other words,
+* XLlFifo_IntClear uses the "set a bit to clear it" scheme.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    Mask contains a bit mask of the pending interrupts to clear. The
+*           mask can be formed using a set of bitwise or'd values from the
+*           <code>XLLF_INT_*_MASK</code> preprocessor symbols.
+*
+* @note
+* C-style signature:
+*    void XLlFifo_IntClear(XLlFifo *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XLlFifo_IntClear(InstancePtr, Mask) \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET, \
+			((Mask) & XLLF_INT_ALL_MASK))
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_RxReset resets the receive channel of the FIFO specified by
+* <i>InstancePtr</i>. XLlFifo_RxReset drops any bytes in the FIFO not yet
+* retrieved.
+*
+* The calling software may want to test for the completion of the reset by
+* reading the interrupt status (IS) register and testing for the Rx Reset
+* complete (RRC) bit.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_RxReset(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_RxReset(InstancePtr) \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_RDFR_OFFSET, \
+			XLLF_RDFR_RESET_MASK)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IsRxEmpty returns true if the receive channel of the FIFO, specified
+* by <i>InstancePtr</i>, is empty.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_IsRxEmpty returns TRUE when the receive channel of the
+*           FIFO is empty. Otherwise, XLlFifo_IsRxEmpty returns FALSE.
+*
+* @note
+* C-style signature:
+*    int XLlFifo_IsRxEmpty(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_IsRxEmpty(InstancePtr) \
+	((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_RDFO_OFFSET) == 0) \
+							? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_RxOccupancy returns the number of 32-bit words available (occupancy) to
+* be read from the receive channel of the FIFO, specified by <i>InstancePtr</i>.
+*
+* The xps_ll_fifo core uses the same fifo to store data values and frame length
+* values. Upon initialization, the XLlFifo_RxOccupancy will give the value of
+* 1, which means one length value (a reserved fifo location) and no data
+* values.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_RxOccupancy returns the occupancy count for the specified
+*           packet FIFO.
+*
+* @note
+*
+* C Signature: u32 XLlFifo_RxOccupancy(XLlFifo *InstancePtr)
+*
+******************************************************************************/
+#define XLlFifo_RxOccupancy(InstancePtr) \
+	XStrm_RxOccupancy(&((InstancePtr)->RxStreamer))
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_RxGetLen notifies the hardware that the program is ready to receive
+* the next frame from the receive channel of the FIFO, specified by
+* <i>InstancePtr</i>.
+*
+* Note that the program must first call XLlFifo_RxGetLen before pulling data
+* out of the receive channel of the FIFO with XLlFifo_Read.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_RxGetLen returns the number of bytes available in the next
+*           frame.
+*
+* @note
+*
+* C Signature: u32 XLlFifo_RxGetLen(XLlFifo *InstancePtr)
+*
+******************************************************************************/
+#define XLlFifo_RxGetLen(InstancePtr) \
+	XStrm_RxGetLen(&((InstancePtr)->RxStreamer))
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_Read reads <i>Bytes</i> bytes from the receive channel of the FIFO
+* referenced by <i>InstancePtr</i> to the block of memory, referenced by
+* <i>BufPtr</i>.
+*
+* Care must be taken to ensure that the number of bytes read with one or more
+* calls to XLlFifo_Read() does not exceed the number of bytes available given
+* from the last call to XLlFifo_RxGetLen().
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    BufPtr specifies the memory address to place the data read.
+*
+* @param    Bytes specifies the number of bytes to read.
+*
+* @return   N/A
+*
+* @note
+* Error handling is handled through hardware exceptions and interrupts.
+*
+* C Signature: void XLlFifo_Read(XLlFifo *InstancePtr, void *BufPtr, unsigned Bytes)
+*
+******************************************************************************/
+#define XLlFifo_Read(InstancePtr, BufPtr, Bytes) \
+	XStrm_Read(&((InstancePtr)->RxStreamer), (BufPtr), (Bytes))
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_TxReset resets the transmit channel of the FIFO specified by
+* <i>InstancePtr</i>. XLlFifo_TxReset drops any bytes in the FIFO not yet
+* transmitted.
+*
+* The calling software may want to test for the completion of the reset by
+* reading the interrupt status (IS) register and testing for the Tx Reset
+* complete (TRC) bit.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_TxReset(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_TxReset(InstancePtr) \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_TDFR_OFFSET, \
+			XLLF_TDFR_RESET_MASK)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IsTxDone returns true if the transmission in the transmit channel
+* of the FIFO, specified by <i>InstancePtr</i>, is complete. XLlFifo_IsTxDone
+* works only if the TC bit in the IS register is cleared before sending a
+* frame.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_IsTxDone returns TRUE when the transmit channel of the
+*           FIFO is complete. Otherwise, XLlFifo_IsTxDone returns FALSE.
+*
+* @note
+* C-style signature:
+*    int XLlFifo_IsTxDone(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_IsTxDone(InstancePtr) \
+	((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET) & \
+		XLLF_INT_TC_MASK) \
+		? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_IsRxDone returns true if the reception in the receive channel
+* of the FIFO, specified by <i>InstancePtr</i>, is complete. XLlFifo_IsRxDone
+* works only if the RC bit in the ISR register is cleared before receiving a
+* frame.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_IsRxDone returns TRUE when the receive channel of the
+*           FIFO is complete. Otherwise, XLlFifo_IsRxDone returns FALSE.
+*
+* @note
+* C-style signature:
+*    int XLlFifo_IsRxDone(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_IsRxDone(InstancePtr) \
+	((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET) & \
+		XLLF_INT_RC_MASK) \
+		? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_TxVacancy returns the number of unused 32 bit words available
+* (vacancy) in the send channel of the FIFO specified by <i>InstancePtr</i>.
+*
+* The xps_ll_fifo core uses tXLLF_he same fifo to store data values and frame length
+* values. Upon initialization, the XLlFifo_TxVacancy will give the value of
+* FIFO_WIDTH - 1, which means one length value used (a reserved fifo location)
+* and no data values yet present.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @return   XLlFifo_TxVacancy returns the vacancy count in 32-bit words for
+*           the specified FIFO.
+*
+* @note
+* C-style signature:
+*    u32 XLlFifo_TxVacancy(XLlFifo *InstancePtr)
+*
+*****************************************************************************/
+#define XLlFifo_TxVacancy(InstancePtr) \
+	XStrm_TxVacancy(&((InstancePtr)->TxStreamer))
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_TxSetLen begins a hardware transfer of <i>Bytes</i> bytes out of the
+* transmit channel of the FIFO specified by <i>InstancePtr</i>.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    Bytes specifies the frame length in bytes.
+*
+* @return   N/A
+*
+* @note
+*
+* C Signature: void XLlFifo_TxSetLen(XLlFifo *InstancePtr, u32 Bytes)
+*
+******************************************************************************/
+#define XLlFifo_TxSetLen(InstancePtr, Bytes) \
+	XStrm_TxSetLen(&((InstancePtr)->TxStreamer), (Bytes))
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_Write writes <i>Bytes</i> bytes of the block of memory, referenced by
+* <i>BufPtr</i>, to the transmit channel of the FIFO referenced by
+* <i>InstancePtr</i>.
+*
+* Care must be taken to ensure that the number of bytes written with one or
+* more calls to XLlFifo_Write() matches the number of bytes given in the next
+* call to XLlFifo_TxSetLen().
+*
+* @param    InstancePtr references the FIFO on which to operate.
+*
+* @param    BufPtr specifies the memory address of data to write.
+*
+* @param    Bytes specifies the number of bytes to write.
+*
+* @return   N/A
+*
+* @note
+* Error handling is handled through hardware exceptions and interrupts.
+*
+* C Signature: void XLlFifo_Write(XLlFifo *InstancePtr, void *BufPtr, unsigned Bytes)
+*
+******************************************************************************/
+#define XLlFifo_Write(InstancePtr, BufPtr, Bytes) \
+	XStrm_Write(&((InstancePtr)->TxStreamer), (BufPtr), (Bytes))
+
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_WriteTdr writes to the Transmit Destination Register (TDR)
+*
+* The TDR stores the destination address corresponding to the packet to  be
+* transmitted. When presenting a transmit packet to the AXI4-Stream FIFO core
+* the following sequence should be followed
+*  - Write the destination address into TDR first,
+*  - Write the packet data to the Transmit Data FIFO next
+*  - Write the length of the packet into the Transmit Length Register.
+*
+* @param    InstancePtr references the FIFO on which to operate.
+* @param    Tdest is the Transmit Destination address to be written to TDR.
+*
+* @return   N/A
+*
+* @note		C Signature:
+*		void XLlFifo_WriteTdr(XLlFifo *InstancePtr, u32 Tdest);
+*
+******************************************************************************/
+#define XLlFifo_WriteTdr(InstancePtr, Tdest) \
+	XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_TDR_OFFSET, \
+			  Tdest & 0xF)
+
+/*****************************************************************************/
+/**
+*
+* XLlFifo_ReadTdr returns the contents of the Receive Destination Register(RDR).
+*
+* The RDR contains destination address corresponding to the valid packet that
+* is received. The RDR should only be read when a receive packet is available
+* for processing (the receive occupancy is not zero).
+* Once the RDR is read, the receive packet data should be read from the receive
+* data FIFO before the RDR is read again. The RDR values are stored in the
+* receive data FIFO by the AXI4-Stream FIFO core with the data of each packet.
+* The RDR value for the subsequent packet to be processed is moved to the RDR
+* when the previous RDR value has been read.
+*
+* @param    	InstancePtr references the FIFO on which to operate.
+*
+* @return   	The Receive Destination address  read from the RDR.
+*
+* @note		C Signature:
+*		u32 XLlFifo_ReadRdr(XLlFifo *InstancePtr)
+*
+******************************************************************************/
+#define XLlFifo_ReadRdr(InstancePtr) 				\
+	XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_RDR_OFFSET)
+
+/************************** Function Prototypes ******************************/
+/*
+ * Initialization functions xllfifo.c
+ */
+int XLlFifo_CfgInitialize(XLlFifo *InstancePtr,
+			XLlFifo_Config *Config, u32 EffectiveAddress);
+void XLlFifo_Initialize(XLlFifo *InstancePtr, u32 BaseAddress);
+XLlFifo_Config *XLlFfio_LookupConfig(u32 DeviceId);
+u32 XLlFifo_iRxOccupancy(XLlFifo *InstancePtr);
+u32 XLlFifo_iRxGetLen(XLlFifo *InstancePtr);
+u32 XLlFifo_iTxVacancy(XLlFifo *InstancePtr);
+void XLlFifo_iTxSetLen(XLlFifo *InstancePtr, u32 Bytes);
+u32 XLlFifo_RxGetWord(XLlFifo *InstancePtr);
+void XLlFifo_TxPutWord(XLlFifo *InstancePtr, u32 Word);
+
+#ifdef __cplusplus
+}
+#endif
+#endif				/* XLLFIFO_H  end of preprocessor protection symbols */
+/** @} */

thirdparty/xilinx/include/xilinx/xllfifo_hw.h

@@ -0,0 +1,242 @@
+/******************************************************************************
+*
+* Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xllfifo_hw.h
+* @addtogroup llfifo_v5_0
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the xps_ll_fifo core.
+* High-level driver functions are defined in xpfifo.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jvb  10/16/06 First release.
+* 1.02a jz   12/04/09  Hal phase 1 support
+* 2.00a hbm  01/20/10  Hal phase 1 support, bump up major release
+* 2.03a asa  14/08/12  Added XLLF_TDR_OFFSET, XLLF_RDR_OFFSET
+*		       defines for the new registers, and XLLF_INT_TFPF_MASK,
+*		       XLLF_INT_TFPE_MASK, XLLF_INT_RFPF_MASK and
+*		       XLLF_INT_RFPE_MASK for the new version of the
+*		       AXI4-Stream FIFO core (v2.01a and later)
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XLLFIFO_HW_H		/* prevent circular inclusions */
+#define XLLFIFO_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xdebug.h"
+#include "xil_io.h"
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit.
+ */
+
+/** @name Registers
+ *  @{
+ */
+#define XLLF_ISR_OFFSET  0x00000000  /**< Interrupt Status */
+#define XLLF_IER_OFFSET  0x00000004  /**< Interrupt Enable */
+
+#define XLLF_TDFR_OFFSET 0x00000008  /**< Transmit Reset */
+#define XLLF_TDFV_OFFSET 0x0000000c  /**< Transmit Vacancy */
+#define XLLF_TDFD_OFFSET 0x00000010  /**< Transmit Data */
+#define XLLF_AXI4_TDFD_OFFSET   0x00000000  /**< Axi4 Transmit Data */
+#define XLLF_TLF_OFFSET  0x00000014  /**< Transmit Length */
+
+#define XLLF_RDFR_OFFSET 0x00000018  /**< Receive Reset */
+#define XLLF_RDFO_OFFSET 0x0000001c  /**< Receive Occupancy */
+#define XLLF_RDFD_OFFSET 0x00000020  /**< Receive Data */
+#define XLLF_AXI4_RDFD_OFFSET 	0x00001000  /**< Axi4 Receive Data */
+#define XLLF_RLF_OFFSET  0x00000024  /**< Receive Length */
+#define XLLF_LLR_OFFSET  0x00000028  /**< Local Link Reset */
+#define XLLF_TDR_OFFSET  0x0000002C  /**< Transmit Destination  */
+#define XLLF_RDR_OFFSET  0x00000030  /**< Receive Destination  */
+
+/*@}*/
+
+/* Register masks. The following constants define bit locations of various
+ * control bits in the registers. Constants are not defined for those registers
+ * that have a single bit field representing all 32 bits. For further
+ * information on the meaning of the various bit masks, refer to the HW spec.
+ */
+
+/** @name Interrupt bits
+ *  These bits are associated with the XLLF_IER_OFFSET and XLLF_ISR_OFFSET
+ *  registers.
+ * @{
+ */
+#define XLLF_INT_RPURE_MASK       0x80000000 /**< Receive under-read */
+#define XLLF_INT_RPORE_MASK       0x40000000 /**< Receive over-read */
+#define XLLF_INT_RPUE_MASK        0x20000000 /**< Receive underrun (empty) */
+#define XLLF_INT_TPOE_MASK        0x10000000 /**< Transmit overrun */
+#define XLLF_INT_TC_MASK          0x08000000 /**< Transmit complete */
+#define XLLF_INT_RC_MASK          0x04000000 /**< Receive complete */
+#define XLLF_INT_TSE_MASK         0x02000000 /**< Transmit length mismatch */
+#define XLLF_INT_TRC_MASK         0x01000000 /**< Transmit reset complete */
+#define XLLF_INT_RRC_MASK         0x00800000 /**< Receive reset complete */
+#define XLLF_INT_TFPF_MASK        0x00400000 /**< Tx FIFO Programmable Full,
+						* AXI FIFO MM2S Only */
+#define XLLF_INT_TFPE_MASK        0x00200000 /**< Tx FIFO Programmable Empty
+						* AXI FIFO MM2S Only */
+#define XLLF_INT_RFPF_MASK        0x00100000 /**< Rx FIFO Programmable Full
+						* AXI FIFO MM2S Only */
+#define XLLF_INT_RFPE_MASK        0x00080000 /**< Rx FIFO Programmable Empty
+						* AXI FIFO MM2S Only */
+#define XLLF_INT_ALL_MASK         0xfff80000 /**< All the ints */
+#define XLLF_INT_ERROR_MASK       0xf2000000 /**< Error status ints */
+#define XLLF_INT_RXERROR_MASK     0xe0000000 /**< Receive Error status ints */
+#define XLLF_INT_TXERROR_MASK     0x12000000 /**< Transmit Error status ints */
+/*@}*/
+
+/** @name Reset register values
+ *  These bits are associated with the XLLF_TDFR_OFFSET and XLLF_RDFR_OFFSET
+ *  reset registers.
+ * @{
+ */
+#define XLLF_RDFR_RESET_MASK        0x000000a5 /**< receive reset value */
+#define XLLF_TDFR_RESET_MASK        0x000000a5 /**< Transmit reset value */
+#define XLLF_LLR_RESET_MASK         0x000000a5 /**< Local Link reset value */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**** debug macros ****/
+#define XLlFifo_reg_name(RegOffset) \
+	(((RegOffset) == XLLF_ISR_OFFSET) ? "ISR": \
+	((RegOffset) == XLLF_IER_OFFSET) ? "IER": \
+	((RegOffset) == XLLF_TDFR_OFFSET) ? "TDFR {tx reset}": \
+	((RegOffset) == XLLF_TDFV_OFFSET) ? "TDFV {tx vacancy}": \
+	((RegOffset) == XLLF_TDFD_OFFSET) ? "TDFD {tx data}": \
+	((RegOffset) == XLLF_TLF_OFFSET) ? "TLF {tx length}": \
+	((RegOffset) == XLLF_RDFR_OFFSET) ? "RDFR {rx reset}": \
+	((RegOffset) == XLLF_RDFO_OFFSET) ? "RDFO {rx occupancy}": \
+	((RegOffset) == XLLF_RDFD_OFFSET) ? "RDFD {rx data}": \
+	((RegOffset) == XLLF_RLF_OFFSET) ? "RLF {rx length}": \
+	"unknown")
+
+#define XLlFifo_print_reg_o(BaseAddress, RegOffset, Value) \
+	 xdbg_printf(XDBG_DEBUG_FIFO_REG, "0x%08x -> %s(0x%08x)\n", (Value), \
+			  XLlFifo_reg_name(RegOffset), \
+			 (RegOffset) + (BaseAddress))
+
+#define XLlFifo_print_reg_i(BaseAddress, RegOffset, Value) \
+	xdbg_printf(XDBG_DEBUG_FIFO_REG, "%s(0x%08x) -> 0x%08x\n", \
+			 XLlFifo_reg_name(RegOffset), \
+			(RegOffset) + (BaseAddress), (Value))
+/**** end debug macros ****/
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_ReadReg returns the value of the register at the offet,
+* <i>RegOffset</i>, from the memory mapped base address, <i>BaseAddress</i>.
+*
+* @param    BaseAddress specifies the base address of the device.
+*
+* @param    RegOffset specifies the offset from BaseAddress.
+*
+* @return   XLlFifo_ReadReg returns the value of the specified register.
+*
+* @note
+* C-style signature:
+*    u32 XLlFifo_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#ifdef DEBUG
+extern u32 _xllfifo_rr_value;
+#define XLlFifo_ReadReg(BaseAddress, RegOffset) \
+	((((RegOffset) > 0x24) ? xdbg_printf(XDBG_DEBUG_ERROR, \
+		"XLlFifo_WriteReg: Woah! wrong reg addr: 0x%08x\n", \
+		(RegOffset)) : 0), \
+	_xllfifo_rr_value = Xil_In32((BaseAddress) + (RegOffset)), \
+	XLlFifo_print_reg_i((BaseAddress), (RegOffset), _xllfifo_rr_value), \
+	_xllfifo_rr_value)
+#else
+#define XLlFifo_ReadReg(BaseAddress, RegOffset) \
+	(Xil_In32((BaseAddress) + (RegOffset)))
+#endif
+
+/****************************************************************************/
+/**
+*
+* XLlFifo_WriteReg writes the value, <i>Value</i>, to the register at the
+* offet, <i>RegOffset</i>, from the memory mapped base address,
+* <i>BaseAddress</i>.
+*
+* @param    BaseAddress specifies the base address of the device.
+*
+* @param    RegOffset specifies the offset from BaseAddress.
+*
+* @param    Value is value to write to the register.
+*
+* @return   N/A
+*
+* @note
+* C-style signature:
+*    void XLlFifo_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Value)
+*
+*****************************************************************************/
+#ifdef DEBUG
+#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value) \
+	(((RegOffset) > 0x24) ? xdbg_printf(XDBG_DEBUG_ERROR, \
+		"XLlFifo_WriteReg: Woah! wrong reg addr: 0x%08x\n", \
+		(RegOffset)) : 0), \
+	XLlFifo_print_reg_o((BaseAddress), (RegOffset), (Value)), \
+	(Xil_Out32((BaseAddress) + (RegOffset), (Value)))
+#else
+#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value) \
+	((Xil_Out32((BaseAddress) + (RegOffset), (Value))))
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif				/* XLLFIFO_HW_H  end of protection macro */
+/** @} */

thirdparty/xilinx/include/xilinx/xparameters.h

@@ -0,0 +1,16 @@
+#ifndef _X_PARAMETERS_H_
+#define _X_PARAMETERS_H_
+
+/* We set all instance counters to zero
+ * to avoid the generation of configuration tables
+ * See: *_g.c, *_sinit.c source files
+ */
+#define XPAR_XLLFIFO_NUM_INSTANCES 0
+#define XPAR_XTMRCTR_NUM_INSTANCES 0
+#define XPAR_XAXIDMA_NUM_INSTANCES 0
+#define XPAR_XAXIS_SWITCH_NUM_INSTANCES 0
+
+#define XPAR_XINTC_NUM_INSTANCES 0
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 0
+
+#endif

thirdparty/xilinx/include/xilinx/xstatus.h

@@ -0,0 +1,432 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* This file contains Xilinx software status codes.  Status codes have their
+* own data type called int.  These codes are used throughout the Xilinx
+* device drivers.
+*
+******************************************************************************/
+
+#ifndef XSTATUS_H		/* prevent circular inclusions */
+#define XSTATUS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+
+#define XST_SUCCESS                     0L
+#define XST_FAILURE                     1L
+#define XST_DEVICE_NOT_FOUND            2L
+#define XST_DEVICE_BLOCK_NOT_FOUND      3L
+#define XST_INVALID_VERSION             4L
+#define XST_DEVICE_IS_STARTED           5L
+#define XST_DEVICE_IS_STOPPED           6L
+#define XST_FIFO_ERROR                  7L	/* an error occurred during an
+						   operation with a FIFO such as
+						   an underrun or overrun, this
+						   error requires the device to
+						   be reset */
+#define XST_RESET_ERROR                 8L	/* an error occurred which requires
+						   the device to be reset */
+#define XST_DMA_ERROR                   9L	/* a DMA error occurred, this error
+						   typically requires the device
+						   using the DMA to be reset */
+#define XST_NOT_POLLED                  10L	/* the device is not configured for
+						   polled mode operation */
+#define XST_FIFO_NO_ROOM                11L	/* a FIFO did not have room to put
+						   the specified data into */
+#define XST_BUFFER_TOO_SMALL            12L	/* the buffer is not large enough
+						   to hold the expected data */
+#define XST_NO_DATA                     13L	/* there was no data available */
+#define XST_REGISTER_ERROR              14L	/* a register did not contain the
+						   expected value */
+#define XST_INVALID_PARAM               15L	/* an invalid parameter was passed
+						   into the function */
+#define XST_NOT_SGDMA                   16L	/* the device is not configured for
+						   scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR              17L	/* a loopback test failed */
+#define XST_NO_CALLBACK                 18L	/* a callback has not yet been
+						   registered */
+#define XST_NO_FEATURE                  19L	/* device is not configured with
+						   the requested feature */
+#define XST_NOT_INTERRUPT               20L	/* device is not configured for
+						   interrupt mode operation */
+#define XST_DEVICE_BUSY                 21L	/* device is busy */
+#define XST_ERROR_COUNT_MAX             22L	/* the error counters of a device
+						   have maxed out */
+#define XST_IS_STARTED                  23L	/* used when part of device is
+						   already started i.e.
+						   sub channel */
+#define XST_IS_STOPPED                  24L	/* used when part of device is
+						   already stopped i.e.
+						   sub channel */
+#define XST_DATA_LOST                   26L	/* driver defined error */
+#define XST_RECV_ERROR                  27L	/* generic receive error */
+#define XST_SEND_ERROR                  28L	/* generic transmit error */
+#define XST_NOT_ENABLED                 29L	/* a requested service is not
+						   available because it has not
+						   been enabled */
+
+/***************** Utility Component statuses 401 - 500  *********************/
+
+#define XST_MEMTEST_FAILED              401L	/* memory test failed */
+
+
+/***************** Common Components statuses 501 - 1000 *********************/
+
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA          501L	/* not enough data in FIFO   */
+#define XST_PFIFO_NO_ROOM               502L	/* not enough room in FIFO   */
+#define XST_PFIFO_BAD_REG_VALUE         503L	/* self test, a register value
+						   was invalid after reset */
+#define XST_PFIFO_ERROR                 504L	/* generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK              505L	/* packet FIFO is reporting
+						 * empty and full simultaneously
+						 */
+
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR          511L	/* self test, DMA transfer
+						   failed */
+#define XST_DMA_RESET_REGISTER_ERROR    512L	/* self test, a register value
+						   was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY           513L	/* scatter gather list contains
+						   no buffer descriptors ready
+						   to be processed */
+#define XST_DMA_SG_IS_STARTED           514L	/* scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED           515L	/* scatter gather not running */
+#define XST_DMA_SG_LIST_FULL            517L	/* all the buffer desciptors of
+						   the scatter gather list are
+						   being used */
+#define XST_DMA_SG_BD_LOCKED            518L	/* the scatter gather buffer
+						   descriptor which is to be
+						   copied over in the scatter
+						   list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/* no buffer descriptors have been
+						   put into the scatter gather
+						   list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED       521L	/* the packet count threshold
+						   specified was larger than the
+						   total # of buffer descriptors
+						   in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS          522L	/* the scatter gather list has
+						   already been created */
+#define XST_DMA_SG_NO_LIST              523L	/* no scatter gather list has
+						   been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/* the buffer descriptor which was
+						   being started was not committed
+						   to the list */
+#define XST_DMA_SG_NO_DATA              525L	/* the buffer descriptor to start
+						   has already been used by the
+						   hardware so it can't be reused
+						 */
+#define XST_DMA_SG_LIST_ERROR           526L	/* general purpose list access
+						   error */
+#define XST_DMA_BD_ERROR                527L	/* general buffer descriptor
+						   error */
+
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR        531L	/* an invalid register width
+						   was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR   532L	/* the value of a register at
+						   reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/* a write to the device interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR       534L	/* the device interrupt status
+						   register did not reset when
+						   acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/* the device interrupt enable
+						   register was not updated when
+						   other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR        536L	/* a write to the IP interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_IP_ACK_ERROR           537L	/* the IP interrupt status register
+						   did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR        538L	/* IP interrupt enable register was
+						   not updated correctly when other
+						   registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/* The device interrupt pending
+						   register did not indicate the
+						   expected value */
+#define XST_IPIF_DEVICE_ID_ERROR        540L	/* The device interrupt ID register
+						   did not indicate the expected
+						   value */
+#define XST_IPIF_ERROR                  541L	/* generic ipif error */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/* Memory space is not big enough
+						 * to hold the minimum number of
+						 * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/* Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR     1003L	/* MII read error */
+#define XST_EMAC_MII_BUSY           1004L	/* An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS     1005L	/* Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR        1006L	/* Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR    1007L	/* Excess deferral or late
+						 * collision on polled send */
+
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR         1051L
+#define XST_UART_START_ERROR        1052L
+#define XST_UART_CONFIG_ERROR       1053L
+#define XST_UART_TEST_FAIL          1054L
+#define XST_UART_BAUD_ERROR         1055L
+#define XST_UART_BAUD_RANGE         1056L
+
+
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED         1076	/* self test failed            */
+#define XST_IIC_BUS_BUSY                1077	/* bus found busy              */
+#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/* mastersend attempted with   */
+					     /* general call address        */
+#define XST_IIC_STAND_REG_RESET_ERROR   1079	/* A non parameterizable reg   */
+					     /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/* Tx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/* Rx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR     1082	/* 10 bit addr incl in design  */
+					     /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR       1083	/* Read of the control register */
+					     /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR      1084	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR      1085	/* Read of the data Receive reg */
+					     /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR      1086	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR      1087	/* Read of the 10 bit addr reg */
+					     /* didn't return written value */
+#define XST_IIC_NOT_SLAVE               1088	/* The device isn't a slave    */
+
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX    1101L	/* the error counters in the ATM
+						   controller hit the max value
+						   which requires the statistics
+						   to be cleared */
+
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY                1126L	/* Flash is erasing or programming
+						 */
+#define XST_FLASH_READY               1127L	/* Flash is ready for commands */
+#define XST_FLASH_ERROR               1128L	/* Flash had detected an internal
+						   error. Use XFlash_DeviceControl
+						   to retrieve device specific codes
+						 */
+#define XST_FLASH_ERASE_SUSPENDED     1129L	/* Flash is in suspended erase state
+						 */
+#define XST_FLASH_WRITE_SUSPENDED     1130L	/* Flash is in suspended write state
+						 */
+#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/* Flash type not supported by
+						   driver */
+#define XST_FLASH_NOT_SUPPORTED       1132L	/* Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS    1133L	/* Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR       1134L	/* Programming or erase operation
+						   aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR       1135L	/* Accessed flash outside its
+						   addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR     1136L	/* Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/* Couldn't return immediately from
+						   write/erase function with
+						   XFL_NON_BLOCKING_WRITE/ERASE
+						   option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR     1138L	/* Failed to query the device */
+
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT          1151	/* master was selected as slave */
+#define XST_SPI_TRANSFER_DONE       1152	/* data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN   1153	/* slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN     1154	/* device overruns receive register */
+#define XST_SPI_NO_SLAVE            1155	/* no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES     1156	/* more than one slave is being
+						 * selected */
+#define XST_SPI_NOT_MASTER          1157	/* operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY          1158	/* device is configured as slave-only
+						 */
+#define XST_SPI_SLAVE_MODE_FAULT    1159	/* slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE          1160	/* device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY   1161	/* device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR       1162	/* unrecognised command - qspi only */
+
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY  1176	/* the priority registers have either
+						 * one master assigned to two or more
+						 * priorities, or one master not
+						 * assigned to any priority
+						 */
+#define XST_OPBARB_NOT_SUSPENDED     1177	/* an attempt was made to modify the
+						 * priority levels without first
+						 * suspending the use of priority
+						 * levels
+						 */
+#define XST_OPBARB_PARK_NOT_ENABLED  1178	/* bus parking by id was enabled but
+						 * bus parking was not enabled
+						 */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/* the arbiter must be in fixed
+						 * priority mode to allow the
+						 * priorities to be changed
+						 */
+
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST      1201	/* self test failed */
+#define XST_INTC_CONNECT_ERROR      1202	/* interrupt already in use */
+
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED     1226	/* self test failed */
+
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED      1251L
+
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST    1276L
+
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST   1301L
+
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST   1326L
+
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK          1351L	/* No MPU lock has been granted */
+
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS     1361L
+
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR			1400
+#define XST_FR_TX_BUSY			1401
+#define XST_FR_BUF_LOCKED		1402
+#define XST_FR_NO_BUF			1403
+
+/****************** USB constants 1410 - 1420  *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED	1410
+#define XST_USB_BUF_ALIGN_ERROR		1411
+#define XST_USB_NO_DESC_AVAILABLE	1412
+#define XST_USB_BUF_TOO_BIG		1413
+#define XST_USB_NO_BUF			1414
+
+/****************** HWICAP constants 1421 - 1429  *****************************/
+
+#define XST_HWICAP_WRITE_DONE		1421
+
+
+/****************** AXI VDMA constants 1430 - 1440  *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR 1430
+
+/*********************** NAND Flash statuses 1441 - 1459  *********************/
+
+#define XST_NAND_BUSY			1441L	/* Flash is erasing or
+						 * programming
+						 */
+#define XST_NAND_READY			1442L	/* Flash is ready for commands
+						 */
+#define XST_NAND_ERROR			1443L	/* Flash had detected an
+						 * internal error.
+						 */
+#define XST_NAND_PART_NOT_SUPPORTED	1444L	/* Flash type not supported by
+						 * driver
+						 */
+#define XST_NAND_OPT_NOT_SUPPORTED	1445L	/* Operation not supported
+						 */
+#define XST_NAND_TIMEOUT_ERROR		1446L	/* Programming or erase
+						 * operation aborted due to a
+						 * timeout
+						 */
+#define XST_NAND_ADDRESS_ERROR		1447L	/* Accessed flash outside its
+						 * addressible range
+						 */
+#define XST_NAND_ALIGNMENT_ERROR	1448L	/* Write alignment error
+						 */
+#define XST_NAND_PARAM_PAGE_ERROR	1449L	/* Failed to read parameter
+						 * page of the device
+						 */
+#define XST_NAND_CACHE_ERROR		1450L	/* Flash page buffer error
+						 */
+
+#define XST_NAND_WRITE_PROTECTED	1451L	/* Flash is write protected
+						 */
+
+/**************************** Type Definitions *******************************/
+
+typedef int XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */

thirdparty/xilinx/include/xilinx/xstreamer.h

@@ -0,0 +1,333 @@
+/******************************************************************************
+*
+* Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*
+ *
+ * @file xstreamer.h
+* @addtogroup llfifo_v5_0
+* @{
+ *
+ * The Xilinx byte streamer for packet FIFOs.
+ *
+ * <h2>Driver Description</h2>
+ *
+ * This driver enables higher layer software to access a hardware FIFO using
+ * any alignment in the data buffers while preserving alignment for the hardware
+ * FIFO access.
+ *
+ * This driver treats send and receive channels separately, using different
+ * types of instance objects for each.
+ *
+ * This driver makes use of another FIFO driver to access the specific FIFO
+ * hardware through use of the routines passed into the Tx/RxInitialize
+ * routines.
+ *
+ * <h2>Initialization</h2>
+ *
+ * Send and receive channels are intialized separately. The receive channel is
+ * initiailzed using XStrm_RxInitialize(). The send channel is initialized
+ * using XStrm_TxInitialize().
+ *
+ *
+ * <h2>Usage</h2>
+ * It is fairly simple to use the API provided by this byte streamer
+ * driver. The only somewhat tricky part is that the calling code must
+ * correctly call a couple routines in the right sequence for receive and
+ * transmit.
+ *
+ * 	This sequence is described here. Check the routine functional
+ * descriptions for information on how to use a specific API routine.
+ *
+ * <h3>Receive</h3>
+ * A frame is received by using the following sequence:<br>
+ * 1) call XStrm_RxGetLen() to get the length of the next incoming frame.<br>
+ * 2) call XStrm_Read() one or more times to read the number of bytes
+ * 	   reported by XStrm_RxGetLen().<br>
+ *
+ * For example:
+ * <pre>
+ * 	frame_len = XStrm_RxGetLen(&RxInstance);
+ * 	while (frame_len) {
+ * 		unsigned bytes = min(sizeof(buffer), frame_len);
+ * 		XStrm_Read(&RxInstance, buffer, bytes);
+ * 		// do something with buffer here
+ * 		frame_len -= bytes;
+ * 	}
+ * </pre>
+ *
+ * Other restrictions on the sequence of API calls may apply depending on
+ * the specific FIFO driver used by this byte streamer driver.
+ *
+ * <h3>Transmit</h3>
+ * A frame is transmittted by using the following sequence:<br>
+ * 1) call XStrm_Write() one or more times to write all the of bytes in
+ *    the next frame.<br>
+ * 2) call XStrm_TxSetLen() to begin the transmission of frame just
+ *    written.<br>
+ *
+ * For example:
+ * <pre>
+ * 	frame_left = frame_len;
+ * 	while (frame_left) {
+ * 		unsigned bytes = min(sizeof(buffer), frame_left);
+ * 		XStrm_Write(&TxInstance, buffer, bytes);
+ * 		// do something here to refill buffer
+ * 	}
+ * 	XStrm_TxSetLen(&RxInstance, frame_len);
+ * </pre>
+ *
+ * Other restrictions on the sequence of API calls may apply depending on
+ * the specific FIFO driver used by this byte streamer driver.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a jvb  10/12/06 First release
+ * 1.02a jz   12/04/09  Hal phase 1 support
+ * 2.00a hbm  01/20/10  Hal phase 1 support, bump up major release
+ * 2.02a asa  12/28/11  The macro XStrm_IsRxInternalEmpty is changed to use
+ *			FrmByteCnt instead of HeadIndex.
+ * </pre>
+ *
+ *****************************************************************************/
+#ifndef XSTREAMER_H		/* prevent circular inclusions */
+#define XSTREAMER_H		/* by using preprocessor symbols */
+
+/* force C linkage */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xenv.h"
+#include "xdebug.h"
+#include "xil_types.h"
+
+/*
+ * key hole size in 32 bit words
+ */
+#define LARGEST_FIFO_KEYHOLE_SIZE_WORDS 4
+
+/*
+ * This union is used simply to force a 32bit alignment on the
+ * buffer. Only the 'bytes' member is really used.
+ */
+union XStrm_AlignedBufferType {
+	u32 _words[LARGEST_FIFO_KEYHOLE_SIZE_WORDS];
+	char bytes[LARGEST_FIFO_KEYHOLE_SIZE_WORDS * 4];
+};
+
+typedef int(*XStrm_XferFnType) (void *FifoInstance, void *BufPtr,
+                                    unsigned WordCount);
+typedef u32 (*XStrm_GetLenFnType) (void *FifoInstance);
+typedef void (*XStrm_SetLenFnType) (void *FifoInstance,
+                                    u32 ByteCount);
+typedef u32 (*XStrm_GetOccupancyFnType) (void *FifoInstance);
+typedef u32 (*XStrm_GetVacancyFnType) (void *FifoInstance);
+
+/**
+ * This typedef defines a run-time instance of a receive byte-streamer.
+ */
+typedef struct XStrm_RxFifoStreamer {
+	union XStrm_AlignedBufferType AlignedBuffer;
+	unsigned HeadIndex;  /**< HeadIndex is the index to the AlignedBuffer
+	                      *   as bytes.
+                              */
+	unsigned FifoWidth;  /**< FifoWidth is the FIFO key hole width in bytes.
+	                      */
+	unsigned FrmByteCnt; /**< FrmByteCnt is the number of bytes in the next
+			      *   Frame.
+			      */
+	void *FifoInstance;  /**< FifoInstance is the FIFO driver instance to
+	                      *   pass to ReadFn, GetLenFn, and GetOccupancyFn
+	                      *   routines.
+	                      */
+	XStrm_XferFnType ReadFn;     /**< ReadFn is the routine the streamer
+	                              *   uses to receive bytes from the Fifo.
+	                              */
+	XStrm_GetLenFnType GetLenFn; /**< GetLenFn is the routine the streamer
+	                              *   uses to initiate receive operations
+	                              *   on the FIFO.
+                                      */
+	XStrm_GetOccupancyFnType GetOccupancyFn; /**< GetOccupancyFn is the
+	                                          *   routine the streamer uses
+	                                          *   to get the occupancy from
+	                                          *   the FIFO.
+	                                          */
+} XStrm_RxFifoStreamer;
+
+/**
+ * This typedef defines a run-time instance of a transmit byte-streamer.
+ */
+typedef struct XStrm_TxFifoStreamer {
+	union XStrm_AlignedBufferType AlignedBuffer;
+	unsigned TailIndex; /**< TailIndex is the index to the AlignedBuffer
+	                     *   as bytes
+                             */
+	unsigned FifoWidth; /**< FifoWidth is the FIFO key hole width in bytes.
+	                     */
+
+	void *FifoInstance; /**< FifoInstance is the FIFO driver instance to
+	                     *   pass to WriteFn, SetLenFn, and GetVacancyFn
+	                     *   routines.
+	                     */
+	XStrm_XferFnType WriteFn; /**< WriteFn is the routine the streamer
+	                           *   uses to transmit bytes to the Fifo.
+	                           */
+	XStrm_SetLenFnType SetLenFn; /**< SetLenFn is the routine the streamer
+	                              *   uses to initiate transmit operations
+	                              *   on the FIFO.
+                                      */
+	XStrm_GetVacancyFnType GetVacancyFn; /**< GetVaccancyFn is the routine
+	                                      *   the streamer uses to get the
+	                                      *   vacancy from the FIFO.
+	                                      */
+} XStrm_TxFifoStreamer;
+
+/*****************************************************************************/
+/*
+*
+* XStrm_TxVacancy returns the number of unused 32-bit words available (vacancy)
+* between the streamer, specified by <i>InstancePtr</i>, and the FIFO this
+* streamer is using.
+*
+* @param    InstancePtr references the streamer on which to operate.
+*
+* @return   XStrm_TxVacancy returns the vacancy count in number of 32 bit words.
+*
+* @note
+*
+* C Signature: u32 XStrm_TxVacancy(XStrm_TxFifoStreamer *InstancePtr)
+*
+* The amount of bytes in the holding buffer (rounded up to whole 32-bit words)
+* is subtracted from the vacancy value of FIFO this streamer is using. This is
+* to ensure the caller can write the number words given in the return value and
+* not overflow the FIFO.
+*
+******************************************************************************/
+#define XStrm_TxVacancy(InstancePtr) \
+	(((*(InstancePtr)->GetVacancyFn)((InstancePtr)->FifoInstance)) - \
+			(((InstancePtr)->TailIndex + 3) / 4))
+
+/*****************************************************************************/
+/*
+*
+* XStrm_RxOccupancy returns the number of 32-bit words available (occupancy) to
+* be read from the streamer, specified by <i>InstancePtr</i>, and FIFO this
+* steamer is using.
+*
+* @param    InstancePtr references the streamer on which to operate.
+*
+* @return   XStrm_RxOccupancy returns the occupancy count in number of 32 bit
+*           words.
+*
+* @note
+*
+* C Signature: u32 XStrm_RxOccupancy(XStrm_RxFifoStreamer *InstancePtr)
+*
+* The amount of bytes in the holding buffer (rounded up to whole 32-bit words)
+* is added to the occupancy value of FIFO this streamer is using. This is to
+* ensure the caller will get a little more accurate occupancy value.
+*
+******************************************************************************/
+#ifdef DEBUG
+extern u32 _xstrm_ro_value;
+extern u32 _xstrm_buffered;
+#define XStrm_RxOccupancy(InstancePtr) \
+        (_xstrm_ro_value = ((*(InstancePtr)->GetOccupancyFn)((InstancePtr)->FifoInstance)), \
+	xdbg_printf(XDBG_DEBUG_FIFO_RX, "reg: %d; frmbytecnt: %d\n", \
+		_xstrm_ro_value, (InstancePtr)->FrmByteCnt), \
+	(((InstancePtr)->FrmByteCnt) ? \
+		_xstrm_buffered = ((InstancePtr)->FifoWidth - (InstancePtr)->HeadIndex) : \
+		0), \
+	xdbg_printf(XDBG_DEBUG_FIFO_RX, "buffered_bytes: %d\n", _xstrm_buffered), \
+	xdbg_printf(XDBG_DEBUG_FIFO_RX, "buffered (rounded): %d\n", _xstrm_buffered), \
+	(_xstrm_ro_value + _xstrm_buffered))
+#else
+#define XStrm_RxOccupancy(InstancePtr) \
+	( \
+	  ((*(InstancePtr)->GetOccupancyFn)((InstancePtr)->FifoInstance)) + \
+	  ( \
+	    ((InstancePtr)->FrmByteCnt) ? \
+	      ((InstancePtr)->FifoWidth - (InstancePtr)->HeadIndex) : \
+	      0 \
+	  ) \
+	)
+#endif
+
+/****************************************************************************/
+/*
+*
+* XStrm_IsRxInternalEmpty returns true if the streamer, specified by
+* <i>InstancePtr</i>, is not holding any bytes in it's  internal buffers. Note
+* that this routine does not reflect information about the state of the
+* FIFO used by this streamer.
+*
+* @param    InstancePtr references the streamer on which to operate.
+*
+* @return   XStrm_IsRxInternalEmpty returns TRUE when the streamer is not
+*           holding any bytes in it's internal buffers. Otherwise,
+*           XStrm_IsRxInternalEmpty returns FALSE.
+*
+* @note
+* C-style signature:
+*    int XStrm_IsRxInternalEmpty(XStrm_RxFifoStreamer *InstancePtr)
+*
+*****************************************************************************/
+#define XStrm_IsRxInternalEmpty(InstancePtr) \
+	(((InstancePtr)->FrmByteCnt == 0) ? TRUE : FALSE)
+
+void XStrm_RxInitialize(XStrm_RxFifoStreamer *InstancePtr,
+                        unsigned FifoWidth, void *FifoInstance,
+                        XStrm_XferFnType ReadFn,
+                        XStrm_GetLenFnType GetLenFn,
+                        XStrm_GetOccupancyFnType GetOccupancyFn);
+
+void XStrm_TxInitialize(XStrm_TxFifoStreamer *InstancePtr,
+                        unsigned FifoWidth, void *FifoInstance,
+                        XStrm_XferFnType WriteFn,
+                        XStrm_SetLenFnType SetLenFn,
+                        XStrm_GetVacancyFnType GetVacancyFn);
+
+void XStrm_TxSetLen(XStrm_TxFifoStreamer *InstancePtr, u32 Bytes);
+void XStrm_Write(XStrm_TxFifoStreamer *InstancePtr, void *BufPtr,
+                    unsigned bytes);
+
+u32 XStrm_RxGetLen(XStrm_RxFifoStreamer *InstancePtr);
+void XStrm_Read(XStrm_RxFifoStreamer *InstancePtr, void *BufPtr,
+                   unsigned bytes);
+
+#ifdef __cplusplus
+}
+#endif
+#endif				/* XSTREAMER_H  end of preprocessor protection symbols */
+/** @} */

thirdparty/xilinx/include/xilinx/xtmrctr.h

@@ -0,0 +1,303 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtmrctr.h
+* @addtogroup tmrctr_v4_0
+* @{
+* @details
+*
+* The Xilinx timer/counter component. This component supports the Xilinx
+* timer/counter. More detailed description of the driver operation can
+* be found in the xtmrctr.c file.
+*
+* The Xilinx timer/counter supports the following features:
+*   - Polled mode.
+*   - Interrupt driven mode
+*   - enabling and disabling specific timers
+*   - PWM operation
+*   - Cascade Operation (This is to be used for getting a 64 bit timer and this
+*     feature is present in the latest versions of the axi_timer IP)
+*
+* The driver does not currently support the PWM operation of the device.
+*
+* The timer counter operates in 2 primary modes, compare and capture. In
+* either mode, the timer counter may count up or down, with up being the
+* default.
+*
+* Compare mode is typically used for creating a single time period or multiple
+* repeating time periods in the auto reload mode, such as a periodic interrupt.
+* When started, the timer counter loads an initial value, referred to as the
+* compare value, into the timer counter and starts counting down or up. The
+* timer counter expires when it rolls over/under depending upon the mode of
+* counting. An external compare output signal may be configured such that a
+* pulse is generated with this signal when it hits the compare value.
+*
+* Capture mode is typically used for measuring the time period between
+* external events. This mode uses an external capture input signal to cause
+* the value of the timer counter to be captured. When started, the timer
+* counter loads an initial value, referred to as the compare value,
+
+* The timer can be configured to either cause an interrupt when the count
+* reaches the compare value in compare mode or latch the current count
+* value in the capture register when an external input is asserted
+* in capture mode. The external capture input can be enabled/disabled using the
+* XTmrCtr_SetOptions function. While in compare mode, it is also possible to
+* drive an external output when the compare value is reached in the count
+* register The external compare output can be enabled/disabled using the
+* XTmrCtr_SetOptions function.
+*
+* <b>Interrupts</b>
+*
+* It is the responsibility of the application to connect the interrupt
+* handler of the timer/counter to the interrupt source. The interrupt
+* handler function, XTmrCtr_InterruptHandler, is visible such that the user
+* can connect it to the interrupt source. Note that this interrupt handler
+* does not provide interrupt context save and restore processing, the user
+* must perform this processing.
+*
+* The driver services interrupts and passes timeouts to the upper layer
+* software through callback functions. The upper layer software must register
+* its callback functions during initialization. The driver requires callback
+* functions for timers.
+*
+* @note
+* The default settings for the timers are:
+*   - Interrupt generation disabled
+*   - Count up mode
+*   - Compare mode
+*   - Hold counter (will not reload the timer)
+*   - External compare output disabled
+*   - External capture input disabled
+*   - Pulse width modulation disabled
+*   - Timer disabled, waits for Start function to be called
+* <br><br>
+* A timer counter device may contain multiple timer counters. The symbol
+* XTC_DEVICE_TIMER_COUNT defines the number of timer counters in the device.
+* The device currently contains 2 timer counters.
+* <br><br>
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  08/16/01 First release
+* 1.00b jhl  02/21/02 Repartitioned the driver for smaller files
+* 1.10b mta  03/21/07 Updated to new coding style.
+* 1.11a sdm  08/22/08 Removed support for static interrupt handlers from the MDD
+*		      file
+* 2.00a ktn  10/30/09 Updated to use HAL API's. _m is removed from all the macro
+*		      definitions.
+* 2.01a ktn  07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
+*		      for naming consistency (CR 559142).
+* 2.02a sdm  09/28/10 Updated the driver tcl to generate the xparameters
+*		      for the timer clock frequency (CR 572679).
+* 2.03a rvo  11/30/10 Added check to see if interrupt is enabled before further
+*		      processing for CR 584557.
+* 2.04a sdm  07/12/11 Added support for cascade mode operation.
+* 		      The cascade mode of operation is present in the latest
+*		      versions of the axi_timer IP. Please check the HW
+*		      Datasheet to see whether this feature is present in the
+*		      version of the IP that you are using.
+* 2.05a adk  15/05/13 Fixed the CR:693066
+*		      Added the IsStartedTmrCtr0/IsStartedTmrCtr1 members to the
+*		      XTmrCtr instance structure.
+*		      The IsStartedTmrCtrX will be assigned XIL_COMPONENT_IS_STARTED in
+*		      the XTmrCtr_Start function.
+*		      The IsStartedTmrCtrX will be cleared in the XTmrCtr_Stop function.
+*		      There will be no Initialization done in the
+*		      XTmrCtr_Initialize if both the timers have already started and
+*		      the XST_DEVICE_IS_STARTED Status is returned.
+*		      Removed the logic in the XTmrCtr_Initialize function
+*		      which was checking the Register Value to know whether
+*		      a timer has started or not.
+* 3.0   adk  19/12/13 Updated as per the New Tcl API's
+* 4.0   als  09/30/15 Updated initialization API.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTMRCTR_H		/* prevent circular inclusions */
+#define XTMRCTR_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xtmrctr_l.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * @name Configuration options
+ * These options are used in XTmrCtr_SetOptions() and XTmrCtr_GetOptions()
+ * @{
+ */
+/**
+ * Used to configure the timer counter device.
+ * <pre>
+ * XTC_CASCADE_MODE_OPTION	Enables the Cascade Mode only valid for TCSRO.
+ * XTC_ENABLE_ALL_OPTION	Enables all timer counters at once.
+ * XTC_DOWN_COUNT_OPTION	Configures the timer counter to count down from
+ *				start value, the default is to count up.
+ * XTC_CAPTURE_MODE_OPTION	Configures the timer to capture the timer
+ *				counter value when the external capture line is
+ *				asserted. The default mode is compare mode.
+ * XTC_INT_MODE_OPTION		Enables the timer counter interrupt output.
+ * XTC_AUTO_RELOAD_OPTION	In compare mode, configures the timer counter to
+ *				reload from the compare value. The default mode
+ *				causes the timer counter to hold when the
+ *				compare value is hit.
+ *				In capture mode, configures the timer counter to
+ *				not hold the previous capture value if a new
+ *				event occurs. The default mode cause the timer
+ *				counter to hold the capture value until
+ *				recognized.
+ * XTC_EXT_COMPARE_OPTION	Enables the external compare output signal.
+ * </pre>
+ */
+#define XTC_CASCADE_MODE_OPTION		0x00000080UL
+#define XTC_ENABLE_ALL_OPTION		0x00000040UL
+#define XTC_DOWN_COUNT_OPTION		0x00000020UL
+#define XTC_CAPTURE_MODE_OPTION		0x00000010UL
+#define XTC_INT_MODE_OPTION		0x00000008UL
+#define XTC_AUTO_RELOAD_OPTION		0x00000004UL
+#define XTC_EXT_COMPARE_OPTION		0x00000002UL
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 BaseAddress;	/**< Register base address */
+	u32 SysClockFreqHz;	/**< The AXI bus clock frequency */
+} XTmrCtr_Config;
+
+/**
+ * Signature for the callback function.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the callback functions, and passed back to the
+ *		upper layer when the callback is invoked. Its type is
+ *		 unimportant to the driver, so it is a void pointer.
+ * @param 	TmrCtrNumber is the number of the timer/counter within the
+ *		device. The device typically contains at least two
+ *		timer/counters. The timer number is a zero based number with a
+ *		range of 0 to (XTC_DEVICE_TIMER_COUNT - 1).
+ */
+typedef void (*XTmrCtr_Handler) (void *CallBackRef, u8 TmrCtrNumber);
+
+
+/**
+ * Timer/Counter statistics
+ */
+typedef struct {
+	u32 Interrupts;	 /**< The number of interrupts that have occurred */
+} XTmrCtrStats;
+
+/**
+ * The XTmrCtr driver instance data. The user is required to allocate a
+ * variable of this type for every timer/counter device in the system. A
+ * pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+	XTmrCtr_Config Config;   /**< Core configuration. */
+	XTmrCtrStats Stats;	 /**< Component Statistics */
+	u32 BaseAddress;	 /**< Base address of registers */
+	u32 IsReady;		 /**< Device is initialized and ready */
+	u32 IsStartedTmrCtr0;	 /**< Is Timer Counter 0 started */
+	u32 IsStartedTmrCtr1;	 /**< Is Timer Counter 1 started */
+
+	XTmrCtr_Handler Handler; /**< Callback function */
+	void *CallBackRef;	 /**< Callback reference for handler */
+} XTmrCtr;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* Required functions, in file xtmrctr.c */
+void XTmrCtr_CfgInitialize(XTmrCtr *InstancePtr, XTmrCtr_Config *ConfigPtr,
+		u32 EffectiveAddr);
+int XTmrCtr_InitHw(XTmrCtr *InstancePtr);
+int XTmrCtr_Initialize(XTmrCtr * InstancePtr, u16 DeviceId);
+void XTmrCtr_Start(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+void XTmrCtr_Stop(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+u32 XTmrCtr_GetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+void XTmrCtr_SetResetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber,
+			   u32 ResetValue);
+u32 XTmrCtr_GetCaptureValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+int XTmrCtr_IsExpired(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+void XTmrCtr_Reset(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+
+/* Lookup configuration in xtmrctr_sinit.c */
+XTmrCtr_Config *XTmrCtr_LookupConfig(u16 DeviceId);
+
+/* Functions for options, in file xtmrctr_options.c */
+void XTmrCtr_SetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber, u32 Options);
+u32 XTmrCtr_GetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+
+/* Functions for statistics, in file xtmrctr_stats.c */
+void XTmrCtr_GetStats(XTmrCtr * InstancePtr, XTmrCtrStats * StatsPtr);
+void XTmrCtr_ClearStats(XTmrCtr * InstancePtr);
+
+/* Functions for self-test, in file xtmrctr_selftest.c */
+int XTmrCtr_SelfTest(XTmrCtr * InstancePtr, u8 TmrCtrNumber);
+
+/* Functions for interrupts, in file xtmrctr_intr.c */
+void XTmrCtr_SetHandler(XTmrCtr * InstancePtr, XTmrCtr_Handler FuncPtr,
+			void *CallBackRef);
+void XTmrCtr_InterruptHandler(void *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */

thirdparty/xilinx/include/xilinx/xtmrctr_i.h

@@ -0,0 +1,80 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtmrctr_i.h
+* @addtogroup tmrctr_v3_0
+* @{
+*
+* This file contains data which is shared between files internal to the
+* XTmrCtr component. It is intended for internal use only.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b jhl  02/06/02 First release
+* 1.10b mta  03/21/07 Updated to new coding style
+* 2.00a ktn  10/30/09 _m is removed from all the macro definitions.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTMRCTR_I_H		/* prevent circular inclusions */
+#define XTMRCTR_I_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+extern u8 XTmrCtr_Offsets[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/** @} */

thirdparty/xilinx/include/xilinx/xtmrctr_l.h

@@ -0,0 +1,429 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xtmrctr_l.h
+* @addtogroup tmrctr_v4_0
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+* High-level driver functions are defined in xtmrctr.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b jhl  04/24/02 First release
+* 1.10b mta  03/21/07 Updated to new coding style
+* 2.00a ktn  10/30/09 Updated to use HAL API's. _m is removed from all the macro
+*		      definitions.
+* 2.01a ktn  07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
+*		      for naming consistency (CR 559142).
+* 2.04a sdm  07/12/11 Added the CASC mode bit in the TCSRO register for the
+*		      cascade mode operation.
+*		      The cascade mode of operation is present in the latest
+*		      versions of the axi_timer IP. Please check the HW
+*		      Datasheet to see whether this feature is present in the
+*		      version of the IP that you are using.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTMRCTR_L_H		/* prevent circular inclusions */
+#define XTMRCTR_L_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * Defines the number of timer counters within a single hardware device. This
+ * number is not currently parameterized in the hardware but may be in the
+ * future.
+ */
+#define XTC_DEVICE_TIMER_COUNT		2
+
+/* Each timer counter consumes 16 bytes of address space */
+
+#define XTC_TIMER_COUNTER_OFFSET	16
+
+/** @name Register Offset Definitions
+ * Register offsets within a timer counter, there are multiple
+ * timer counters within a single device
+ * @{
+ */
+
+#define XTC_TCSR_OFFSET		0	/**< Control/Status register */
+#define XTC_TLR_OFFSET		4	/**< Load register */
+#define XTC_TCR_OFFSET		8	/**< Timer counter register */
+
+/* @} */
+
+/** @name Control Status Register Bit Definitions
+ * Control Status Register bit masks
+ * Used to configure the timer counter device.
+ * @{
+ */
+
+#define XTC_CSR_CASC_MASK		0x00000800 /**< Cascade Mode */
+#define XTC_CSR_ENABLE_ALL_MASK		0x00000400 /**< Enables all timer
+							counters */
+#define XTC_CSR_ENABLE_PWM_MASK		0x00000200 /**< Enables the Pulse Width
+							Modulation */
+#define XTC_CSR_INT_OCCURED_MASK	0x00000100 /**< If bit is set, an
+							interrupt has occured.
+							If set and '1' is
+							written to this bit
+							position, bit is
+							cleared. */
+#define XTC_CSR_ENABLE_TMR_MASK		0x00000080 /**< Enables only the
+							specific timer */
+#define XTC_CSR_ENABLE_INT_MASK		0x00000040 /**< Enables the interrupt
+							output. */
+#define XTC_CSR_LOAD_MASK		0x00000020 /**< Loads the timer using
+							the load value provided
+							earlier in the Load
+							Register,
+							XTC_TLR_OFFSET. */
+#define XTC_CSR_AUTO_RELOAD_MASK	0x00000010 /**< In compare mode,
+							configures
+							the timer counter to
+							reload  from the
+							Load Register. The
+							default  mode
+							causes the timer counter
+							to hold when the compare
+							value is hit. In capture
+							mode, configures  the
+							timer counter to not
+							hold the previous
+							capture value if a new
+							event occurs. The
+							default mode cause the
+							timer counter to hold
+							the capture value until
+							recognized. */
+#define XTC_CSR_EXT_CAPTURE_MASK	0x00000008 /**< Enables the
+							external input
+							to the timer counter. */
+#define XTC_CSR_EXT_GENERATE_MASK	0x00000004 /**< Enables the
+							external generate output
+							for the timer. */
+#define XTC_CSR_DOWN_COUNT_MASK		0x00000002 /**< Configures the timer
+							counter to count down
+							from start value, the
+							default is to count
+							up.*/
+#define XTC_CSR_CAPTURE_MODE_MASK	0x00000001 /**< Enables the timer to
+							capture the timer
+							counter value when the
+							external capture line is
+							asserted. The default
+							mode is compare mode.*/
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+extern u8 XTmrCtr_Offsets[];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Read one of the timer counter registers.
+*
+* @param	BaseAddress contains the base address of the timer counter
+*		device.
+* @param	TmrCtrNumber contains the specific timer counter within the
+*		device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+* @param	RegOffset contains the offset from the 1st register of the timer
+*		counter to select the specific register of the timer counter.
+*
+* @return	The value read from the register, a 32 bit value.
+*
+* @note		C-Style signature:
+* 		u32 XTmrCtr_ReadReg(u32 BaseAddress, u8 TimerNumber,
+					unsigned RegOffset);
+******************************************************************************/
+#define XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset)	\
+	Xil_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
+			(RegOffset))
+
+#ifndef XTimerCtr_ReadReg
+#define XTimerCtr_ReadReg XTmrCtr_ReadReg
+#endif
+
+/*****************************************************************************/
+/**
+* Write a specified value to a register of a timer counter.
+*
+* @param	BaseAddress is the base address of the timer counter device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+* @param	RegOffset contain the offset from the 1st register of the timer
+*		counter to select the specific register of the timer counter.
+* @param	ValueToWrite is the 32 bit value to be written to the register.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_WriteReg(u32 BaseAddress, u8 TimerNumber,
+*					unsigned RegOffset, u32 ValueToWrite);
+******************************************************************************/
+#define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
+	Xil_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] +	\
+			   (RegOffset)), (ValueToWrite))
+
+/****************************************************************************/
+/**
+*
+* Set the Control Status Register of a timer counter to the specified value.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+* @param	RegisterValue is the 32 bit value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_SetControlStatusReg(u32 BaseAddress,
+*					u8 TmrCtrNumber,u32 RegisterValue);
+*****************************************************************************/
+#define XTmrCtr_SetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,     \
+					   (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the Control Status Register of a timer counter.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device,
+*		a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	The value read from the register, a 32 bit value.
+*
+* @note		C-Style signature:
+* 		u32 XTmrCtr_GetControlStatusReg(u32 BaseAddress,
+*						u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_GetControlStatusReg(BaseAddress, TmrCtrNumber)		\
+	XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Get the Timer Counter Register of a timer counter.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device,
+*		a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	The value read from the register, a 32 bit value.
+*
+* @note		C-Style signature:
+* 		u32 XTmrCtr_GetTimerCounterReg(u32 BaseAddress,
+*						u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_GetTimerCounterReg(BaseAddress, TmrCtrNumber)		  \
+	XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCR_OFFSET) \
+
+/****************************************************************************/
+/**
+*
+* Set the Load Register of a timer counter to the specified value.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+* @param	RegisterValue is the 32 bit value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_SetLoadReg(u32 BaseAddress, u8 TmrCtrNumber,
+*						  u32 RegisterValue);
+*****************************************************************************/
+#define XTmrCtr_SetLoadReg(BaseAddress, TmrCtrNumber, RegisterValue)	 \
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET, \
+					   (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the Load Register of a timer counter.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	The value read from the register, a 32 bit value.
+*
+* @note		C-Style signature:
+* 		u32 XTmrCtr_GetLoadReg(u32 BaseAddress, u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_GetLoadReg(BaseAddress, TmrCtrNumber)	\
+XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable a timer counter such that it starts running.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_Enable(u32 BaseAddress, u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_Enable(BaseAddress, TmrCtrNumber)			    \
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,   \
+			(XTmrCtr_ReadReg((BaseAddress), ( TmrCtrNumber), \
+			XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_TMR_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable a timer counter such that it stops running.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device,
+*		a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_Disable(u32 BaseAddress, u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_Disable(BaseAddress, TmrCtrNumber)			  \
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
+			(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\
+			XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_TMR_MASK))
+
+/****************************************************************************/
+/**
+*
+* Enable the interrupt for a timer counter.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_EnableIntr(u32 BaseAddress, u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_EnableIntr(BaseAddress, TmrCtrNumber)			    \
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,   \
+			(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),  \
+			XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_INT_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable the interrupt for a timer counter.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_DisableIntr(u32 BaseAddress, u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_DisableIntr(BaseAddress, TmrCtrNumber)			   \
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,  \
+	(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),		   \
+		XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_INT_MASK))
+
+/****************************************************************************/
+/**
+*
+* Cause the timer counter to load it's Timer Counter Register with the value
+* in the Load Register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		   zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XTmrCtr_LoadTimerCounterReg(u32 BaseAddress,
+					u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_LoadTimerCounterReg(BaseAddress, TmrCtrNumber)		  \
+	XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
+			(XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\
+			XTC_TCSR_OFFSET) | XTC_CSR_LOAD_MASK))
+
+/****************************************************************************/
+/**
+*
+* Determine if a timer counter event has occurred.  Events are defined to be
+* when a capture has occurred or the counter has roller over.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	TmrCtrNumber is the specific timer counter within the device, a
+*		zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
+*
+* @note		C-Style signature:
+* 		int XTmrCtr_HasEventOccurred(u32 BaseAddress, u8 TmrCtrNumber);
+*****************************************************************************/
+#define XTmrCtr_HasEventOccurred(BaseAddress, TmrCtrNumber)		\
+		((XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),	\
+		XTC_TCSR_OFFSET) & XTC_CSR_INT_OCCURED_MASK) ==		\
+		XTC_CSR_INT_OCCURED_MASK)
+
+/************************** Function Prototypes ******************************/
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+#endif /* end of protection macro */
+/** @} */

thirdparty/xilinx/include/xilinx/xutil.h

@@ -0,0 +1,167 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xutil.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* This file contains utility functions such as memory test functions.
+*
+* <b>Memory test description</b>
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* Subtest descriptions:
+* <pre>
+* XUT_ALLMEMTESTS:
+*       Runs all of the following tests
+*
+* XUT_INCREMENT:
+*       Incrementing Value Test.
+*       This test starts at 'XUT_MEMTEST_INIT_VALUE' and uses the incrementing
+*       value as the test value for memory.
+*
+* XUT_WALKONES:
+*       Walking Ones Test.
+*       This test uses a walking '1' as the test value for memory.
+*       location 1 = 0x00000001
+*       location 2 = 0x00000002
+*       ...
+*
+* XUT_WALKZEROS:
+*       Walking Zero's Test.
+*       This test uses the inverse value of the walking ones test
+*       as the test value for memory.
+*       location 1 = 0xFFFFFFFE
+*       location 2 = 0xFFFFFFFD
+*       ...
+*
+* XUT_INVERSEADDR:
+*       Inverse Address Test.
+*       This test uses the inverse of the address of the location under test
+*       as the test value for memory.
+*
+* XUT_FIXEDPATTERN:
+*       Fixed Pattern Test.
+*       This test uses the provided patters as the test value for memory.
+*       If zero is provided as the pattern the test uses '0xDEADBEEF".
+* </pre>
+*
+* <i>WARNING</i>
+*
+* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
+* have been set up.
+*
+* The address, Addr, provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a
+* boundry of a power of two making it more difficult to detect addressing
+* errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same
+* problem. Ideally, if large blocks of memory are to be tested, break
+* them up into smaller regions of memory to allow the test patterns used
+* not to repeat over the region tested.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  11/01/01 First release
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XUTIL_H			/* prevent circular inclusions */
+#define XUTIL_H			/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xbasic_types.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XUT_MEMTEST_INIT_VALUE  1
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XUT_ALLMEMTESTS     0
+#define XUT_INCREMENT       1
+#define XUT_WALKONES        2
+#define XUT_WALKZEROS       3
+#define XUT_INVERSEADDR     4
+#define XUT_FIXEDPATTERN    5
+#define XUT_MAXTEST         XUT_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_memtest prototypes */
+
+int XUtil_MemoryTest32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+int XUtil_MemoryTest16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+int XUtil_MemoryTest8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */

thirdparty/xilinx/include/xilinx/xversion.h

@@ -0,0 +1,111 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xversion.h
+* @addtogroup common_v1_00_a
+* @{
+*
+* This file contains the interface for the XVersion component. This
+* component represents a version ID.  It is encapsulated within a component
+* so that it's type and implementation can change without affecting users of
+* it.
+*
+* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
+* X is the major revision, YY is the minor revision, and Z is the
+* compatability revision.
+*
+* Packed versions are also utilized for the configuration ROM such that
+* memory is minimized. A packed version consumes only 16 bits and is
+* formatted as follows.
+*
+* <pre>
+* Revision                  Range       Bit Positions
+*
+* Major Revision            0 - 9       Bits 15 - 12
+* Minor Revision            0 - 99      Bits 11 - 5
+* Compatability Revision    a - z       Bits 4 - 0
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XVERSION_H		/* prevent circular inclusions */
+#define XVERSION_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* the following data type is used to hold a null terminated version string
+ * consisting of the following format, "X.YYX"
+ */
+typedef char XVersion[6];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+void XVersion_UnPack(XVersion *InstancePtr, u16 PackedVersion);
+
+int XVersion_Pack(XVersion *InstancePtr, u16 *PackedVersion);
+
+int XVersion_IsEqual(XVersion *InstancePtr, XVersion *VersionPtr);
+
+void XVersion_ToString(XVersion *InstancePtr, char *StringPtr);
+
+int XVersion_FromString(XVersion *InstancePtr, char *StringPtr);
+
+void XVersion_Copy(XVersion *InstancePtr, XVersion *VersionPtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */

thirdparty/xilinx/orig/README.md

@@ -0,0 +1 @@
+Those drivers are taken from https://github.com/Xilinx/embeddedsw

thirdparty/xilinx/orig/axidma_v9_0/data/axidma.mdd

@@ -0,0 +1,43 @@
+###############################################################################
+#
+# Copyright (C) 2010 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+##############################################################################
+
+OPTION psf_version = 2.1;
+
+BEGIN driver axidma
+
+  OPTION supported_peripherals = (axi_dma_v[3-9]_[0-9][0-9]_[a-z] axi_dma_v[3-9]_[0-9]);
+  OPTION driver_state = ACTIVE;
+  OPTION copyfiles = all;
+  OPTION VERSION = 9.0;
+  OPTION NAME = axidma;
+
+END driver

thirdparty/xilinx/orig/axidma_v9_0/data/axidma.tcl

@@ -0,0 +1,208 @@
+###############################################################################
+#
+# Copyright (C) 2010 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+# MODIFICATION HISTORY:
+# Ver      Who    Date     Changes
+# -------- ------ -------- ----------------------------------------------------
+#  8.0     adk    12/10/13 Updated as per the New Tcl API's
+##############################################################################
+
+#uses "xillib.tcl"
+
+set periph_ninstances    0
+
+proc generate {drv_handle} {
+  ::hsi::utils::define_include_file $drv_handle "xparameters.h" "XAxiDma" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_SG_INCLUDE_STSCNTRL_STRM" "C_INCLUDE_MM2S_DRE" "C_INCLUDE_S2MM_DRE" "C_INCLUDE_MM2S" "C_INCLUDE_S2MM" "C_M_AXI_MM2S_DATA_WIDTH" "C_M_AXI_S2MM_DATA_WIDTH" "C_INCLUDE_SG" "C_ENABLE_MULTI_CHANNEL" "C_NUM_MM2S_CHANNELS" "C_NUM_S2MM_CHANNELS" "C_MM2S_BURST_SIZE" "C_S2MM_BURST_SIZE" "C_MICRO_DMA" "c_addr_width"
+  ::hsi::utils::define_canonical_xpars $drv_handle "xparameters.h" "AxiDma" "DEVICE_ID" "C_BASEADDR" "C_SG_INCLUDE_STSCNTRL_STRM" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_INCLUDE_SG" "C_ENABLE_MULTI_CHANNEL" "C_NUM_MM2S_CHANNELS" "C_NUM_S2MM_CHANNELS" "C_MM2S_BURST_SIZE" "C_S2MM_BURST_SIZE" "C_MICRO_DMA" "c_addr_width"
+  ::hsi::utils::define_config_file  $drv_handle "xaxidma_g.c" "XAxiDma" "DEVICE_ID" "C_BASEADDR" "C_SG_INCLUDE_STSCNTRL_STRM" "C_INCLUDE_MM2S" "C_INCLUDE_MM2S_DRE" "C_M_AXI_MM2S_DATA_WIDTH" "C_INCLUDE_S2MM" "C_INCLUDE_S2MM_DRE" "C_M_AXI_S2MM_DATA_WIDTH" "C_INCLUDE_SG" "C_NUM_MM2S_CHANNELS" "C_NUM_S2MM_CHANNELS" "C_MM2S_BURST_SIZE" "C_S2MM_BURST_SIZE" "C_MICRO_DMA" "c_addr_width"
+}
+
+#
+# Given a list of arguments, define them all in an include file.
+# Handles mpd and mld parameters, as well as the special parameters NUM_INSTANCES,
+# DEVICE_ID
+# Will not work for a processor.
+#
+
+proc xdefine_dma_include_file {drv_handle file_name drv_string args} {
+    # Open include file
+    set file_handle [xopen_include_file $file_name]
+
+    # Get all peripherals connected to this driver
+    set periphs [xget_sw_iplist_for_driver $drv_handle]
+
+    # Handle special cases
+    set arg "NUM_INSTANCES"
+    set posn [lsearch -exact $args $arg]
+    if {$posn > -1} {
+	puts $file_handle "/* Definitions for driver [string toupper [get_property NAME $drv_handle]] */"
+	# Define NUM_INSTANCES
+	puts $file_handle "#define [xget_dname $drv_string $arg] [llength $periphs]"
+	set args [lreplace $args $posn $posn]
+    }
+    # Check if it is a driver parameter
+
+    lappend newargs
+    foreach arg $args {
+	set value [get_property CONFIG.$arg $drv_handle]
+	if {[llength $value] == 0} {
+	    lappend newargs $arg
+	} else {
+	    puts $file_handle "#define [xget_dname $drv_string $arg] [get_property CONFIG.$arg $drv_handle]"
+	}
+    }
+    set args $newargs
+
+    # Print all parameters for all peripherals
+    set device_id 0
+    foreach periph $periphs {
+	puts $file_handle ""
+	puts $file_handle "/* Definitions for peripheral [string toupper [get_property NAME $periph]] */"
+	foreach arg $args {
+	    if {[string compare -nocase "DEVICE_ID" $arg] == 0} {
+		set value $device_id
+		incr device_id
+	    } else {
+		set value [xget_param_value $periph $arg]
+		if {[string compare -nocase $arg "C_INCLUDE_SG"] == 0} {
+			if {[llength $value] == 0} {
+				set value 1
+			}
+		} else {
+	                if {[llength $value] == 0} {
+	                    set value 0
+	                }
+	        }
+		if {[string compare -nocase $arg "C_MICRO_DMA"] == 0} {
+			if {[llength $value] == 0} {
+				set value 1
+			}
+		} else {
+	                if {[llength $value] == 0} {
+	                    set value 0
+	                }
+	        }
+	    }
+
+	    set value [xformat_addr_string $value $arg]
+	    if {[string compare -nocase "HW_VER" $arg] == 0} {
+                puts $file_handle "#define [xget_name $periph $arg] \"$value\""
+	    } else {
+                puts $file_handle "#define [xget_name $periph $arg] $value"
+            }
+	}
+	puts $file_handle ""
+    }
+    puts $file_handle "\n/******************************************************************/\n"
+    close $file_handle
+}
+
+#-----------------------------------------------------------------------------
+# ::hsi::utils::define_canonical_xpars - Used to print out canonical defines for a driver.
+# Given a list of arguments, define each as a canonical constant name, using
+# the driver name, in an include file.
+#-----------------------------------------------------------------------------
+proc xdefine_axidma_canonical_xpars {drv_handle file_name drv_string args} {
+    # Open include file
+    set file_handle [xopen_include_file $file_name]
+
+    # Get all the peripherals connected to this driver
+    set periphs [xget_sw_iplist_for_driver $drv_handle]
+
+    # Get the names of all the peripherals connected to this driver
+    foreach periph $periphs {
+        set peripheral_name [string toupper [get_property NAME $periph]]
+        lappend peripherals $peripheral_name
+    }
+
+    # Get possible canonical names for all the peripherals connected to this
+    # driver
+    set device_id 0
+    foreach periph $periphs {
+        set canonical_name [string toupper [format "%s_%s" $drv_string $device_id]]
+        lappend canonicals $canonical_name
+
+        # Create a list of IDs of the peripherals whose hardware instance name
+        # doesn't match the canonical name. These IDs can be used later to
+        # generate canonical definitions
+        if { [lsearch $peripherals $canonical_name] < 0 } {
+            lappend indices $device_id
+        }
+        incr device_id
+    }
+
+    set i 0
+    foreach periph $periphs {
+        set periph_name [string toupper [get_property NAME $periph]]
+
+        # Generate canonical definitions only for the peripherals whose
+        # canonical name is not the same as hardware instance name
+        if { [lsearch $canonicals $periph_name] < 0 } {
+            puts $file_handle "/* Canonical definitions for peripheral $periph_name */"
+            set canonical_name [format "%s_%s" $drv_string [lindex $indices $i]]
+
+            foreach arg $args {
+                set lvalue [xget_dname $canonical_name $arg]
+                # The commented out rvalue is the name of the instance-specific constant
+                # set rvalue [xget_name $periph $arg]
+                # The rvalue set below is the actual value of the parameter
+                set rvalue [xget_param_value $periph $arg]
+
+		if {[string compare -nocase $arg "C_INCLUDE_SG"] == 0} {
+			if {[llength $rvalue] == 0} {
+				set rvalue 1
+			}
+		} else {
+	                if {[llength $rvalue] == 0} {
+	                    set rvalue 0
+	                }
+	        }
+		if {[string compare -nocase $arg "C_MICRO_DMA"] == 0} {
+			if {[llength $rvalue] == 0} {
+				set rvalue 1
+			}
+		} else {
+	                if {[llength $rvalue] == 0} {
+	                    set rvalue 0
+	                }
+	        }
+                set rvalue [xformat_addr_string $rvalue $arg]
+
+                puts $file_handle "#define $lvalue $rvalue"
+
+            }
+            puts $file_handle ""
+            incr i
+        }
+    }
+
+    puts $file_handle "\n/******************************************************************/\n"
+    close $file_handle
+}

thirdparty/xilinx/orig/axidma_v9_0/data/axidma_header.h

@@ -0,0 +1,41 @@
+/******************************************************************************
+*
+* Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef AXIDMA_HEADER_H		/* prevent circular inclusions */
+#define AXIDMA_HEADER_H		/* by using protection macros */
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+
+int AxiDMASelfTestExample(u16 DeviceId);
+
+#endif

thirdparty/xilinx/orig/axidma_v9_0/data/axidma_tapp.tcl

@@ -0,0 +1,121 @@
+###############################################################################
+#
+# Copyright (C) 2005 - 2014 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+##############################################################################
+# Uses $XILINX_EDK/bin/lib/xillib_sw.tcl
+
+# -----------------------------------------------------------------
+# Software Project Types (swproj):
+#   0 : MemoryTest - Calls basic  memorytest routines from common driver dir
+#   1 : PeripheralTest - Calls any existing polled_example and/or selftest
+# -----------------------------------------------------------------
+
+# -----------------------------------------------------------------
+# TCL Procedures:
+# -----------------------------------------------------------------
+
+proc gen_include_files {swproj mhsinst} {
+  if {$swproj == 0} {
+    return ""
+  }
+  if {$swproj == 1} {
+    set inc_file_lines {axidma_header.h}
+    return $inc_file_lines
+  }
+}
+
+proc gen_src_files {swproj mhsinst} {
+  if {$swproj == 0} {
+    return ""
+  }
+  if {$swproj == 1} {
+    set inc_file_lines {examples/xaxidma_example_selftest.c data/axidma_header.h}
+    return $inc_file_lines
+  }
+}
+
+proc gen_testfunc_def {swproj mhsinst} {
+  return ""
+}
+
+proc gen_init_code {swproj mhsinst} {
+  return ""
+}
+
+proc gen_testfunc_call {swproj mhsinst} {
+
+  if {$swproj == 0} {
+    return ""
+  }
+
+  set ipname [get_property NAME $mhsinst]
+  set deviceid [::hsi::utils::get_ip_param_name $mhsinst "DEVICE_ID"]
+   set stdout [get_property CONFIG.STDOUT [get_os]]
+   if { $stdout == "" || $stdout == "none" } {
+       set hasStdout 0
+   } else {
+       set hasStdout 1
+   }
+
+  set testfunc_call ""
+
+  if {${hasStdout} == 0} {
+
+      append testfunc_call "
+
+   {
+      int status;
+
+      status = AxiDMASelfTestExample(${deviceid});
+
+   }"
+  } else {
+
+      append testfunc_call "
+
+   {
+      int status;
+
+
+      print(\"\\r\\n Running AxiDMASelfTestExample() for ${ipname}...\\r\\n\");
+
+      status = AxiDMASelfTestExample(${deviceid});
+
+      if (status == 0) {
+         print(\"AxiDMASelfTestExample PASSED\\r\\n\");
+      }
+      else {
+         print(\"AxiDMASelfTestExample FAILED\\r\\n\");
+      }
+   }"
+  }
+
+  return $testfunc_call
+}

thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/annotated.html

@@ -0,0 +1,66 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axidma_v9_0: Data Structures</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">Data Structures</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock">Here are the data structures with brief descriptions:</div><div class="directory">
+<table class="directory">
+<tr id="row_0_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icona"><span class="icon">C</span></span><a class="el" href="struct_x_axi_dma.html" target="_self">XAxiDma</a></td><td class="desc">The <a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> driver instance data </td></tr>
+<tr id="row_1_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icona"><span class="icon">C</span></span><a class="el" href="struct_x_axi_dma___bd_ring.html" target="_self">XAxiDma_BdRing</a></td><td class="desc">Container structure for descriptor storage control </td></tr>
+<tr id="row_2_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icona"><span class="icon">C</span></span><a class="el" href="struct_x_axi_dma___config.html" target="_self">XAxiDma_Config</a></td><td class="desc">The configuration structure for AXI DMA engine </td></tr>
+</table>
+</div><!-- directory -->
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>

thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/classes.html

@@ -0,0 +1,68 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axidma_v9_0: Data Structure Index</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">Data Structure Index</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="qindex"><a class="qindex" href="#letter_X">X</a></div>
+<table style="margin: 10px; white-space: nowrap;" align="center" width="95%" border="0" cellspacing="0" cellpadding="0">
+<tr><td rowspan="2" valign="bottom"><a name="letter_X"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">&#160;&#160;X&#160;&#160;</div></td></tr></table>
+</td><td valign="top"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a>&#160;&#160;&#160;</td><td valign="top"><a class="el" href="struct_x_axi_dma___config.html">XAxiDma_Config</a>&#160;&#160;&#160;</td><td></td></tr>
+<tr><td></td><td></td><td></td></tr>
+<tr><td valign="top"><a class="el" href="struct_x_axi_dma.html">XAxiDma</a>&#160;&#160;&#160;</td><td></td><td></td><td></td></tr>
+<tr><td></td><td></td><td></td><td></td></tr>
+</table>
+<div class="qindex"><a class="qindex" href="#letter_X">X</a></div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>

thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/dynsections.js

@@ -0,0 +1,97 @@
+function toggleVisibility(linkObj)
+{
+ var base = $(linkObj).attr('id');
+ var summary = $('#'+base+'-summary');
+ var content = $('#'+base+'-content');
+ var trigger = $('#'+base+'-trigger');
+ var src=$(trigger).attr('src');
+ if (content.is(':visible')===true) {
+   content.hide();
+   summary.show();
+   $(linkObj).addClass('closed').removeClass('opened');
+   $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png');
+ } else {
+   content.show();
+   summary.hide();
+   $(linkObj).removeClass('closed').addClass('opened');
+   $(trigger).attr('src',src.substring(0,src.length-10)+'open.png');
+ } 
+ return false;
+}
+
+function updateStripes()
+{
+  $('table.directory tr').
+       removeClass('even').filter(':visible:even').addClass('even');
+}
+
+function toggleLevel(level)
+{
+  $('table.directory tr').each(function() {
+    var l = this.id.split('_').length-1;
+    var i = $('#img'+this.id.substring(3));
+    var a = $('#arr'+this.id.substring(3));
+    if (l<level+1) {
+      i.removeClass('iconfopen iconfclosed').addClass('iconfopen');
+      a.html('&#9660;');
+      $(this).show();
+    } else if (l==level+1) {
+      i.removeClass('iconfclosed iconfopen').addClass('iconfclosed');
+      a.html('&#9658;');
+      $(this).show();
+    } else {
+      $(this).hide();
+    }
+  });
+  updateStripes();
+}
+
+function toggleFolder(id)
+{
+  // the clicked row
+  var currentRow = $('#row_'+id);
+
+  // all rows after the clicked row
+  var rows = currentRow.nextAll("tr");
+
+  var re = new RegExp('^row_'+id+'\\d+_$', "i"); //only one sub
+
+  // only match elements AFTER this one (can't hide elements before)
+  var childRows = rows.filter(function() { return this.id.match(re); });
+
+  // first row is visible we are HIDING
+  if (childRows.filter(':first').is(':visible')===true) {
+    // replace down arrow by right arrow for current row
+    var currentRowSpans = currentRow.find("span");
+    currentRowSpans.filter(".iconfopen").removeClass("iconfopen").addClass("iconfclosed");
+    currentRowSpans.filter(".arrow").html('&#9658;');
+    rows.filter("[id^=row_"+id+"]").hide(); // hide all children
+  } else { // we are SHOWING
+    // replace right arrow by down arrow for current row
+    var currentRowSpans = currentRow.find("span");
+    currentRowSpans.filter(".iconfclosed").removeClass("iconfclosed").addClass("iconfopen");
+    currentRowSpans.filter(".arrow").html('&#9660;');
+    // replace down arrows by right arrows for child rows
+    var childRowsSpans = childRows.find("span");
+    childRowsSpans.filter(".iconfopen").removeClass("iconfopen").addClass("iconfclosed");
+    childRowsSpans.filter(".arrow").html('&#9658;');
+    childRows.show(); //show all children
+  }
+  updateStripes();
+}
+
+
+function toggleInherit(id)
+{
+  var rows = $('tr.inherit.'+id);
+  var img = $('tr.inherit_header.'+id+' img');
+  var src = $(img).attr('src');
+  if (rows.filter(':first').is(':visible')===true) {
+    rows.css('display','none');
+    $(img).attr('src',src.substring(0,src.length-8)+'closed.png');
+  } else {
+    rows.css('display','table-row'); // using show() causes jump in firefox
+    $(img).attr('src',src.substring(0,src.length-10)+'open.png');
+  }
+}
+

thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/files.html

@@ -0,0 +1,68 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axidma_v9_0: File List</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li class="current"><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">File List</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock">Here is a list of all documented files with brief descriptions:</div><div class="directory">
+<table class="directory">
+<tr id="row_0_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma_8c.html" target="_self">xaxidma.c</a></td><td class="desc"></td></tr>
+<tr id="row_1_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma_8h.html" target="_self">xaxidma.h</a></td><td class="desc"></td></tr>
+<tr id="row_2_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma__bd_8c.html" target="_self">xaxidma_bd.c</a></td><td class="desc"></td></tr>
+<tr id="row_3_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma__bd_8h.html" target="_self">xaxidma_bd.h</a></td><td class="desc"></td></tr>
+<tr id="row_4_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma__bdring_8c.html" target="_self">xaxidma_bdring.c</a></td><td class="desc"></td></tr>
+<tr id="row_5_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma__bdring_8h.html" target="_self">xaxidma_bdring.h</a></td><td class="desc"></td></tr>
+<tr id="row_6_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma__g_8c.html" target="_self">xaxidma_g.c</a></td><td class="desc"></td></tr>
+<tr id="row_7_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma__hw_8h.html" target="_self">xaxidma_hw.h</a></td><td class="desc"></td></tr>
+<tr id="row_8_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma__porting__guide_8h.html" target="_self">xaxidma_porting_guide.h</a></td><td class="desc"></td></tr>
+<tr id="row_9_"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma__selftest_8c.html" target="_self">xaxidma_selftest.c</a></td><td class="desc"></td></tr>
+<tr id="row_10_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span class="icondoc"></span><a class="el" href="xaxidma__sinit_8c.html" target="_self">xaxidma_sinit.c</a></td><td class="desc"></td></tr>
+</table>
+</div><!-- directory -->
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>

thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/functions.html

@@ -0,0 +1,130 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axidma_v9_0: Data Fields</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li class="current"><a href="functions.html"><span>All</span></a></li>
+      <li><a href="functions_vars.html"><span>Variables</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div><ul>
+<li>AddrWidth
+: <a class="el" href="struct_x_axi_dma.html#a663f5757eabe6b1b8813ed5fdb0d0edb">XAxiDma</a>
+, <a class="el" href="struct_x_axi_dma___config.html#a6fc1c26fb40944182ff84e370e667eb0">XAxiDma_Config</a>
+</li>
+<li>AllCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a3c928d2f36e8daf845a70afdae2573a4">XAxiDma_BdRing</a>
+</li>
+<li>BdaRestart
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a2519fd626856e7ab0d822adc46aab7d8">XAxiDma_BdRing</a>
+</li>
+<li>ChanBase
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing</a>
+</li>
+<li>FirstBdAddr
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a6d41078607d5a8165e67d6483e40e9ab">XAxiDma_BdRing</a>
+</li>
+<li>FirstBdPhysAddr
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#add2c7d765c8d95eeb9d0f94a54775528">XAxiDma_BdRing</a>
+</li>
+<li>FreeCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a51ec0929002582a900d404502e9a1622">XAxiDma_BdRing</a>
+</li>
+<li>FreeHead
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a3e067ffdf2820a816f2d6dda6e3f9114">XAxiDma_BdRing</a>
+</li>
+<li>HasStsCntrlStrm
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a7d35cb00bb50fff2e24c15f7d7d8dae0">XAxiDma_BdRing</a>
+</li>
+<li>HwCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#ab49406dd2d9ec65e3f38d1cc3c880391">XAxiDma_BdRing</a>
+</li>
+<li>HwHead
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#af097be199cf9d1d62cf32f775309a4f3">XAxiDma_BdRing</a>
+</li>
+<li>HwTail
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a7abe8351de43377407c579cd158f2448">XAxiDma_BdRing</a>
+</li>
+<li>IsRxChannel
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a912bf38e61c8b03995ece842426b3ccf">XAxiDma_BdRing</a>
+</li>
+<li>LastBdAddr
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a3743d05f930d7c04abb0693f2ef0b271">XAxiDma_BdRing</a>
+</li>
+<li>Length
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#af0b3fe5c9b9123209b3000e0d95193ed">XAxiDma_BdRing</a>
+</li>
+<li>PostCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#afd4e1620895f91a829354e131432d2b3">XAxiDma_BdRing</a>
+</li>
+<li>PostHead
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a92668e60e10a940428e68f816c64eab6">XAxiDma_BdRing</a>
+</li>
+<li>PreCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a68e8042d227f7a40821a478deb063215">XAxiDma_BdRing</a>
+</li>
+<li>PreHead
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a8a2958fb6be370d3cc29972f57203952">XAxiDma_BdRing</a>
+</li>
+<li>RingIndex
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#ac14f09fcd00f1869c8194d790f73d791">XAxiDma_BdRing</a>
+</li>
+<li>RunState
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing</a>
+</li>
+<li>Separation
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#aafd8e01bf65c7950235d8f21cf225e12">XAxiDma_BdRing</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>

thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/functions_vars.html

@@ -0,0 +1,130 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axidma_v9_0: Data Fields - Variables</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="functions.html"><span>All</span></a></li>
+      <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;<ul>
+<li>AddrWidth
+: <a class="el" href="struct_x_axi_dma.html#a663f5757eabe6b1b8813ed5fdb0d0edb">XAxiDma</a>
+, <a class="el" href="struct_x_axi_dma___config.html#a6fc1c26fb40944182ff84e370e667eb0">XAxiDma_Config</a>
+</li>
+<li>AllCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a3c928d2f36e8daf845a70afdae2573a4">XAxiDma_BdRing</a>
+</li>
+<li>BdaRestart
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a2519fd626856e7ab0d822adc46aab7d8">XAxiDma_BdRing</a>
+</li>
+<li>ChanBase
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a138fd282802e5f6ed3cb1d2505ede08a">XAxiDma_BdRing</a>
+</li>
+<li>FirstBdAddr
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a6d41078607d5a8165e67d6483e40e9ab">XAxiDma_BdRing</a>
+</li>
+<li>FirstBdPhysAddr
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#add2c7d765c8d95eeb9d0f94a54775528">XAxiDma_BdRing</a>
+</li>
+<li>FreeCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a51ec0929002582a900d404502e9a1622">XAxiDma_BdRing</a>
+</li>
+<li>FreeHead
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a3e067ffdf2820a816f2d6dda6e3f9114">XAxiDma_BdRing</a>
+</li>
+<li>HasStsCntrlStrm
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a7d35cb00bb50fff2e24c15f7d7d8dae0">XAxiDma_BdRing</a>
+</li>
+<li>HwCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#ab49406dd2d9ec65e3f38d1cc3c880391">XAxiDma_BdRing</a>
+</li>
+<li>HwHead
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#af097be199cf9d1d62cf32f775309a4f3">XAxiDma_BdRing</a>
+</li>
+<li>HwTail
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a7abe8351de43377407c579cd158f2448">XAxiDma_BdRing</a>
+</li>
+<li>IsRxChannel
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a912bf38e61c8b03995ece842426b3ccf">XAxiDma_BdRing</a>
+</li>
+<li>LastBdAddr
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a3743d05f930d7c04abb0693f2ef0b271">XAxiDma_BdRing</a>
+</li>
+<li>Length
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#af0b3fe5c9b9123209b3000e0d95193ed">XAxiDma_BdRing</a>
+</li>
+<li>PostCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#afd4e1620895f91a829354e131432d2b3">XAxiDma_BdRing</a>
+</li>
+<li>PostHead
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a92668e60e10a940428e68f816c64eab6">XAxiDma_BdRing</a>
+</li>
+<li>PreCnt
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a68e8042d227f7a40821a478deb063215">XAxiDma_BdRing</a>
+</li>
+<li>PreHead
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a8a2958fb6be370d3cc29972f57203952">XAxiDma_BdRing</a>
+</li>
+<li>RingIndex
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#ac14f09fcd00f1869c8194d790f73d791">XAxiDma_BdRing</a>
+</li>
+<li>RunState
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#a443e5c48e677e9a1a4e85a383eefc2be">XAxiDma_BdRing</a>
+</li>
+<li>Separation
+: <a class="el" href="struct_x_axi_dma___bd_ring.html#aafd8e01bf65c7950235d8f21cf225e12">XAxiDma_BdRing</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>

thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/globals.html

@@ -0,0 +1,558 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<meta name="generator" content="Doxygen 1.8.10"/>
+<title>axidma_v9_0: APIs</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<link href="doxygen.css" rel="stylesheet" type="text/css" />
+<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li class="current"><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow4" class="tabs3">
+    <ul class="tablist">
+      <li class="current"><a href="#index_x"><span>x</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:</div>
+
+<h3><a class="anchor" id="index_x"></a>- x -</h3><ul>
+<li>XAxiDma
+: <a class="el" href="group__axidma__v9__0.html#gac08fe7cb6508a133a7ef036bba7df5b5">xaxidma.h</a>
+</li>
+<li>XAxiDma_Bd
+: <a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">xaxidma_bd.h</a>
+</li>
+<li>XAXIDMA_BD_ADDRLEN_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga2b64a2b3eb88233498a9dd6a01068de6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_BUFA_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gaccd48ccba559728721eac77a4acc23d1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_BUFA_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga8bb69f2401305faa1d89fb8dc31e770f">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_BYTES_TO_CLEAR
+: <a class="el" href="group__axidma__v9__0.html#ga97ec6974f990aef9ea2298c1df5d72c3">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_CTRL_ALL_MASK
+: <a class="el" href="group__axidma__v9__0.html#gaa409dba5ec46ad5a31953e22c4d3333f">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_CTRL_LEN_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_CTRL_TXEOF_MASK
+: <a class="el" href="group__axidma__v9__0.html#gae9f4d328b9fb0bbdcadd6dc4c09fd4fa">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_CTRL_TXSOF_MASK
+: <a class="el" href="group__axidma__v9__0.html#gac279d381208f7f123ac07736702f8ff1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HAS_DRE_MASK
+: <a class="el" href="group__axidma__v9__0.html#gad40d36cf3371ad3d176835933dc85e4b">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HAS_DRE_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga932a4ab54f38046e6635b9b87a584c79">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HAS_DRE_SHIFT
+: <a class="el" href="group__axidma__v9__0.html#gac15dd4e956aa14d53a6f92544db468d1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HAS_STSCNTRL_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga819b1b14cd4d386e588679105a8738a6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HW_NUM_BYTES
+: <a class="el" href="group__axidma__v9__0.html#gae8ddf1d33d85b0a7508b9a072d95bf14">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_ID_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga117e266cba3edbd1fd2f1e29305dcfc8">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_MCCTL_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_MINIMUM_ALIGNMENT
+: <a class="el" href="group__axidma__v9__0.html#ga7957d90570574e9c7a7ee308b290ecab">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_NDESC_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga730aa200407e3c7e38e6fad914ad1eb0">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_NDESC_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga64e86b7df328bc7209a28152f86fd609">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_NUM_WORDS
+: <a class="el" href="group__axidma__v9__0.html#ga751f6662ab9baed908685eef30d322b8">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_START_CLEAR
+: <a class="el" href="group__axidma__v9__0.html#ga9eac2b100bcdf0aa763d1575f43c822b">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STRIDE_VSIZE_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_ALL_ERR_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga8018932d7e9b743c4c5c76ab3d373de1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_ALL_MASK
+: <a class="el" href="group__axidma__v9__0.html#gac433a776854849cbeaadcbed14132cb6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_COMPLETE_MASK
+: <a class="el" href="group__axidma__v9__0.html#gadb7c73caf5e5007dcb56ea029d7390ba">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_DEC_ERR_MASK
+: <a class="el" href="group__axidma__v9__0.html#gae79c77f87a9887510ea53480c1e9a998">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_INT_ERR_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga09e502148e375f2d695d6d5d6e1797d2">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_RXEOF_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga91b0504c621f6c06b0df4752fe65ee3a">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_RXSOF_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga29915484fd9f840a8ab727cf83bbfe81">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_SLV_ERR_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga1f7727fc139a6b3100a5a17cb110efa6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR0_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gace0f0376ed9e0aad3d3e3c80254b20b4">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR1_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga7d9d62be0e0ed11b18f185b62dc72f67">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR2_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gadc83ff22099fdf61a5237965ce082504">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR3_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gae1c5981447fe5ac113a6da3c1e19d6ed">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR4_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga1ccae584923d0b6d0851a8bbae4528c9">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_WORDLEN_MASK
+: <a class="el" href="group__axidma__v9__0.html#gafcbd1a131c650a5d6ceee6be15008a77">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_WORDLEN_SHIFT
+: <a class="el" href="group__axidma__v9__0.html#ga3db5b1d09deab9660ff65c06136acbc5">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_BdClear
+: <a class="el" href="group__axidma__v9__0.html#ga6c47900232c9a5a5ba30a2c1a3343628">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetActualLength
+: <a class="el" href="group__axidma__v9__0.html#ga135667574b201437cfbdbecd8b348ee0">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetAppWord()
+: <a class="el" href="group__axidma__v9__0.html#ga9d2814e4249884e68fe9e6f370920ca4">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdGetARCache
+: <a class="el" href="group__axidma__v9__0.html#gaa5f7ba67cbbb678662e4b5d36c63d16e">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetARUser
+: <a class="el" href="group__axidma__v9__0.html#ga72d1616af8d996f12db78473a75b54b6">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetBufAddr
+: <a class="el" href="group__axidma__v9__0.html#gaf858d9659197442c9e96856c206423c6">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetCtrl
+: <a class="el" href="group__axidma__v9__0.html#ga495e780d704ecf548d3536b3bb8961a5">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetId
+: <a class="el" href="group__axidma__v9__0.html#gaf3f333d78d115724bfcac84746d8cfa6">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetLength
+: <a class="el" href="group__axidma__v9__0.html#ga9875ecb45b47664b70d74e8810fd5cf0">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetStride
+: <a class="el" href="group__axidma__v9__0.html#ga29a75b8f1de16a347544e37b48d8129c">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetSts
+: <a class="el" href="group__axidma__v9__0.html#gaf2448f2b2ac172da0d19adeae3cc4c48">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetTDest
+: <a class="el" href="group__axidma__v9__0.html#ga8c1e3dd04821568424ffc77caf11a851">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetTId
+: <a class="el" href="group__axidma__v9__0.html#gac14fa76311fd7e5fb59b81fd9e251f62">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetTUser
+: <a class="el" href="group__axidma__v9__0.html#ga7a2f9668058b7e4cdc89dffcce6086d3">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetVSize
+: <a class="el" href="group__axidma__v9__0.html#gad9f48ceb5b30d66bab23337edc35d2fe">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdHwCompleted
+: <a class="el" href="group__axidma__v9__0.html#ga20937b96fad07f286948f1af50590421">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdRead
+: <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdRingAckIrq
+: <a class="el" href="group__axidma__v9__0.html#ga9e782e3715c1d2dd03e5d03434f47319">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingAlloc()
+: <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingBusy
+: <a class="el" href="group__axidma__v9__0.html#gaf7c291190c92ce93d72f95c5b04ef1d4">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingCheck()
+: <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingClone()
+: <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingCntCalc
+: <a class="el" href="group__axidma__v9__0.html#ga98555b607a9ec831dc6473e77515bb4b">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingCreate()
+: <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingDumpRegs()
+: <a class="el" href="group__axidma__v9__0.html#gaffa661a9a2467c1e274842c147531cea">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingFree()
+: <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingFromHw()
+: <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingGetCnt
+: <a class="el" href="group__axidma__v9__0.html#gac62389e25e6775026cf1be6c383e665b">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetCoalesce()
+: <a class="el" href="group__axidma__v9__0.html#ga0d3794bbccf028da8e94407d061dfc68">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingGetCurrBd
+: <a class="el" href="group__axidma__v9__0.html#ga21aa8dbf6eabf9146097d9b3cc91c574">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetError
+: <a class="el" href="group__axidma__v9__0.html#ga24cd47cdbfac0813e0d9caf966a1a3d2">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetFreeCnt
+: <a class="el" href="group__axidma__v9__0.html#ga415cf0c379fef0104f9f52881ead13a7">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetIrq
+: <a class="el" href="group__axidma__v9__0.html#ga7a9d2103e6d09fc3850b34a6386dc803">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetSr
+: <a class="el" href="group__axidma__v9__0.html#ga740fa349c7811de2b7bae5cf83eb445e">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingHwIsStarted
+: <a class="el" href="group__axidma__v9__0.html#ga766bed2454969636d827fb79faeeee97">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingIntDisable
+: <a class="el" href="group__axidma__v9__0.html#ga0269e07693c731cf7721c6f19f8eb69b">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingIntEnable
+: <a class="el" href="group__axidma__v9__0.html#ga2518030938ab80081f6896fc5589682c">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingIntGetEnabled
+: <a class="el" href="group__axidma__v9__0.html#gadbb17169213d8af8b50e6dee7f7b6d8b">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingMemCalc
+: <a class="el" href="group__axidma__v9__0.html#ga6899085c400b8f453381b305ac5521d9">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingNext
+: <a class="el" href="group__axidma__v9__0.html#ga4b7e75d1acf86428bd79fcd0d1c13745">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingPrev
+: <a class="el" href="group__axidma__v9__0.html#ga86c6d4b9c4f8766634d46a3078eadc8a">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingSetCoalesce()
+: <a class="el" href="group__axidma__v9__0.html#gaaebba5c661e04485582e887e74dbeb94">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingSnapShotCurrBd
+: <a class="el" href="group__axidma__v9__0.html#ga0d79253861939c76e6d440ecde2b6edd">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingStart()
+: <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingToHw()
+: <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingUnAlloc()
+: <a class="el" href="group__axidma__v9__0.html#gac58b1ab7a89890142baf67211772d3ce">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdSetAppWord()
+: <a class="el" href="group__axidma__v9__0.html#gafc6434a23594c20c2b601f010a979e48">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdSetARCache
+: <a class="el" href="group__axidma__v9__0.html#gac7d8a383cd6d5aff6ee36c3a3db20cbf">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetARUser
+: <a class="el" href="group__axidma__v9__0.html#gae89253197f1aef6582d5cda3e49f8ead">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetBufAddr()
+: <a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdSetBufAddrMicroMode()
+: <a class="el" href="group__axidma__v9__0.html#ga8947514b5acfea6298d0f969f3d2b97e">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdSetCtrl()
+: <a class="el" href="group__axidma__v9__0.html#ga4eb2615ac89054e982c3f3c37f0ddb52">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdSetId
+: <a class="el" href="group__axidma__v9__0.html#ga53eeff085fd39a91b855939f13fe76f3">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetLength()
+: <a class="el" href="group__axidma__v9__0.html#ga4056035d8e7c90a68fa954c60d021e07">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdSetStride
+: <a class="el" href="group__axidma__v9__0.html#ga58961be41e3c0bc2694444bfe37b6c27">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetTDest
+: <a class="el" href="group__axidma__v9__0.html#ga5f9b3088c4e16c7f5584610a43b17462">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetTId
+: <a class="el" href="group__axidma__v9__0.html#gaa5bc321894b77ca6194c867018d9fe12">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetTUser
+: <a class="el" href="group__axidma__v9__0.html#gacf41c0ebe00870b6cdd34e46698e081b">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetVSize
+: <a class="el" href="group__axidma__v9__0.html#ga383b2c0667bf5bafa22922168895bd5e">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdWrite
+: <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">xaxidma_bd.h</a>
+</li>
+<li>XAXIDMA_BUFFLEN_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gaa7ede468ba17bf106101d4850184dc74">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_Busy()
+: <a class="el" href="group__axidma__v9__0.html#gaff68c0ba3e9e25dfe5e39153301862f8">xaxidma.c</a>
+</li>
+<li>XAXIDMA_CDESC_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga00ee7a235750d8795961223455407051">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CDESC_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga24b47801eed2ab0ba326b8b40d24f2b1">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_CfgInitialize()
+: <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">xaxidma.c</a>
+</li>
+<li>XAXIDMA_COALESCE_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga280fd988ea7ec3fadfe7cf1293f39e36">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_CYCLIC_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga2d34bf268de2f2ef4d32351043835f68">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_KEYHOLE_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga8bdf83c8ba16d8217a2a6486a9b5b521">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_RESET_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga33fda61f0837d37da36d3b72b90b0fba">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_RUNSTOP_MASK
+: <a class="el" href="group__axidma__v9__0.html#gab0ebdf6b7776e79941efe1325aac5aa9">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_DELAY_MASK
+: <a class="el" href="group__axidma__v9__0.html#gae3ad7ae6b5814b99de67bba06ec77ed1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_DESC_LSB_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga170ce0e12eb12686a03e006610e2acd2">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_DESTADDR_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga3a54e372851dbae81c33997ef2ba8d2f">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_DESTADDR_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga4e98e82ed389c23918315d833b457ea9">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_DumpBd()
+: <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">xaxidma_bd.c</a>
+</li>
+<li>XAXIDMA_ERR_ALL_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga4102192c408420feb5b7db14d47c6d5c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_DECODE_MASK
+: <a class="el" href="group__axidma__v9__0.html#gaa19b93d226e97afd08d3869dc530b692">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_INTERNAL_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga87ac559811703a8ca33fc6b427913f2b">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_SG_DEC_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga43ecb16ea8e8d09a33364a17610d8909">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_SG_INT_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga1f9ef0d10a7456a25a4b244955659d65">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_SG_SLV_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga0f0d25fd68716e868742115c9a28c18c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_SLAVE_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga6d50743f6c9d6474561f6727eb956915">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_GetRxIndexRing
+: <a class="el" href="group__axidma__v9__0.html#gaf03e87b58cf2f9800e6260fda3745631">xaxidma.h</a>
+</li>
+<li>XAxiDma_GetRxRing
+: <a class="el" href="group__axidma__v9__0.html#ga6373ac3baa5365607f6727f4e2ece7a5">xaxidma.h</a>
+</li>
+<li>XAxiDma_GetTxRing
+: <a class="el" href="group__axidma__v9__0.html#ga9d91f29c6dc41f2106e097f1f9957a6e">xaxidma.h</a>
+</li>
+<li>XAXIDMA_HALTED_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga70671c3d8cd1e51c56723e298d268cce">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_HasSg
+: <a class="el" href="group__axidma__v9__0.html#ga18dd03026dd6c0ebd13526116c09ccae">xaxidma.h</a>
+</li>
+<li>XAXIDMA_IDLE_MASK
+: <a class="el" href="group__axidma__v9__0.html#gaa3538e8c2a6e024641259c85368667f0">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_IntrAckIrq
+: <a class="el" href="group__axidma__v9__0.html#ga9ff0d2e5b50846e4b6a2d683283c10d5">xaxidma.h</a>
+</li>
+<li>XAxiDma_IntrDisable
+: <a class="el" href="group__axidma__v9__0.html#ga1936b497c0fa61d326807e5ed8dd572b">xaxidma.h</a>
+</li>
+<li>XAxiDma_IntrEnable
+: <a class="el" href="group__axidma__v9__0.html#gadac28afa26e2cb55bdada1ee3c016c52">xaxidma.h</a>
+</li>
+<li>XAxiDma_IntrGetEnabled
+: <a class="el" href="group__axidma__v9__0.html#gadba63ad7c0a784d569736a8d1eb7c367">xaxidma.h</a>
+</li>
+<li>XAxiDma_IntrGetIrq
+: <a class="el" href="group__axidma__v9__0.html#ga6a0eb17bcfcaf3331e01855d302f5f0e">xaxidma.h</a>
+</li>
+<li>XAXIDMA_IRQ_ALL_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_IRQ_DELAY_MASK
+: <a class="el" href="group__axidma__v9__0.html#gadc4a45d09bcbf852f29b880935d607dc">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_IRQ_ERROR_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga6ceb68e74761910e4253795a9b4992cf">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_IRQ_IOC_MASK
+: <a class="el" href="group__axidma__v9__0.html#gae420f2ad87e1e00456a6ee3a80d2480d">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_LookupConfig()
+: <a class="el" href="group__axidma__v9__0.html#ga0cbcf5259635ea3c336fe5413c98f75c">xaxidma.h</a>
+</li>
+<li>XAXIDMA_MICROMODE_MIN_BUF_ALIGN
+: <a class="el" href="group__axidma__v9__0.html#gaf0f7e862f42d26800868816eea2a949b">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_Pause()
+: <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">xaxidma.c</a>
+</li>
+<li>XAxiDma_ReadReg
+: <a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_Reset()
+: <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">xaxidma.c</a>
+</li>
+<li>XAxiDma_ResetIsDone()
+: <a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">xaxidma.c</a>
+</li>
+<li>XAxiDma_Resume()
+: <a class="el" href="group__axidma__v9__0.html#ga847cd9a0255fcb444bce58b945de8574">xaxidma.c</a>
+</li>
+<li>XAXIDMA_RX_CDESC0_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gad80414a88feceb1da4b9f77096d1d590">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_CDESC0_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga79d2eca90f2554b8c893b2f9a70c795c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_NDESC_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga6fc559cbc93b62195de6ecaf25492467">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_TDESC0_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gaa9b5991af857e7bac763311fd917978d">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_TDESC0_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gadfa4d02f0dd1fd005c695e9977457722">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_SelectCyclicMode()
+: <a class="el" href="group__axidma__v9__0.html#ga2d93bfcf1c3e34cb9fc4a22da6148dc5">xaxidma.c</a>
+</li>
+<li>XAxiDma_SelectKeyHole()
+: <a class="el" href="group__axidma__v9__0.html#ga5becc8b0f9945af34e372ced2b37aebb">xaxidma.c</a>
+</li>
+<li>XAxiDma_Selftest()
+: <a class="el" href="group__axidma__v9__0.html#gad4ea3039216916336ae1c7598ff26afc">xaxidma.h</a>
+</li>
+<li>XAXIDMA_SGCTL_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gab26580f9b4a94b3ab1d373ddeab7b3b6">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_SimpleTransfer()
+: <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">xaxidma.c</a>
+</li>
+<li>XAXIDMA_SR_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_SRCADDR_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gafaafc49751e690d818d604efe368c481">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_SRCADDR_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga386fad6446792679302b362ed34022cf">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_StartBdRingHw()
+: <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">xaxidma_bdring.c</a>
+</li>
+<li>XAXIDMA_TDESC_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga6063ffb7cb46cdca589e6f31069f7758">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_TDESC_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gac8626fb2bed7230a2c82a7e1db0ddd35">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_TX_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga88232281611059fd669f0339888cd44e">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_UpdateBdRingCDesc()
+: <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_WriteReg
+: <a class="el" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">xaxidma_hw.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>

thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/globals_defs.html

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+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
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+<title>axidma_v9_0: APIs</title>
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+<script type="text/javascript" src="dynsections.js"></script>
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+<table cellspacing="0" cellpadding="0">
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+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
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+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
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+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li class="current"><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow4" class="tabs3">
+    <ul class="tablist">
+      <li class="current"><a href="#index_x"><span>x</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;
+
+<h3><a class="anchor" id="index_x"></a>- x -</h3><ul>
+<li>XAXIDMA_BD_ADDRLEN_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga2b64a2b3eb88233498a9dd6a01068de6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_BUFA_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gaccd48ccba559728721eac77a4acc23d1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_BUFA_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga8bb69f2401305faa1d89fb8dc31e770f">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_BYTES_TO_CLEAR
+: <a class="el" href="group__axidma__v9__0.html#ga97ec6974f990aef9ea2298c1df5d72c3">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_CTRL_ALL_MASK
+: <a class="el" href="group__axidma__v9__0.html#gaa409dba5ec46ad5a31953e22c4d3333f">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_CTRL_LEN_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gac3372d0a1625537d5b637f40ca20f52c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_CTRL_TXEOF_MASK
+: <a class="el" href="group__axidma__v9__0.html#gae9f4d328b9fb0bbdcadd6dc4c09fd4fa">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_CTRL_TXSOF_MASK
+: <a class="el" href="group__axidma__v9__0.html#gac279d381208f7f123ac07736702f8ff1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HAS_DRE_MASK
+: <a class="el" href="group__axidma__v9__0.html#gad40d36cf3371ad3d176835933dc85e4b">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HAS_DRE_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga932a4ab54f38046e6635b9b87a584c79">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HAS_DRE_SHIFT
+: <a class="el" href="group__axidma__v9__0.html#gac15dd4e956aa14d53a6f92544db468d1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HAS_STSCNTRL_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga819b1b14cd4d386e588679105a8738a6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_HW_NUM_BYTES
+: <a class="el" href="group__axidma__v9__0.html#gae8ddf1d33d85b0a7508b9a072d95bf14">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_ID_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga117e266cba3edbd1fd2f1e29305dcfc8">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_MCCTL_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga6daf74c6d99207a0d8ba91a049e661c6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_MINIMUM_ALIGNMENT
+: <a class="el" href="group__axidma__v9__0.html#ga7957d90570574e9c7a7ee308b290ecab">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_NDESC_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga730aa200407e3c7e38e6fad914ad1eb0">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_NDESC_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga64e86b7df328bc7209a28152f86fd609">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_NUM_WORDS
+: <a class="el" href="group__axidma__v9__0.html#ga751f6662ab9baed908685eef30d322b8">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_START_CLEAR
+: <a class="el" href="group__axidma__v9__0.html#ga9eac2b100bcdf0aa763d1575f43c822b">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STRIDE_VSIZE_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga83d7d4d6e88ab44910242b61fcd7f8fe">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_ALL_ERR_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga8018932d7e9b743c4c5c76ab3d373de1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_ALL_MASK
+: <a class="el" href="group__axidma__v9__0.html#gac433a776854849cbeaadcbed14132cb6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_COMPLETE_MASK
+: <a class="el" href="group__axidma__v9__0.html#gadb7c73caf5e5007dcb56ea029d7390ba">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_DEC_ERR_MASK
+: <a class="el" href="group__axidma__v9__0.html#gae79c77f87a9887510ea53480c1e9a998">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_INT_ERR_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga09e502148e375f2d695d6d5d6e1797d2">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gac71ad6cd79fc11e699bc10e3736fa08c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_RXEOF_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga91b0504c621f6c06b0df4752fe65ee3a">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_RXSOF_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga29915484fd9f840a8ab727cf83bbfe81">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_STS_SLV_ERR_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga1f7727fc139a6b3100a5a17cb110efa6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR0_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gace0f0376ed9e0aad3d3e3c80254b20b4">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR1_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga7d9d62be0e0ed11b18f185b62dc72f67">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR2_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gadc83ff22099fdf61a5237965ce082504">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR3_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gae1c5981447fe5ac113a6da3c1e19d6ed">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_USR4_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga1ccae584923d0b6d0851a8bbae4528c9">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_WORDLEN_MASK
+: <a class="el" href="group__axidma__v9__0.html#gafcbd1a131c650a5d6ceee6be15008a77">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_BD_WORDLEN_SHIFT
+: <a class="el" href="group__axidma__v9__0.html#ga3db5b1d09deab9660ff65c06136acbc5">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_BdClear
+: <a class="el" href="group__axidma__v9__0.html#ga6c47900232c9a5a5ba30a2c1a3343628">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetActualLength
+: <a class="el" href="group__axidma__v9__0.html#ga135667574b201437cfbdbecd8b348ee0">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetARCache
+: <a class="el" href="group__axidma__v9__0.html#gaa5f7ba67cbbb678662e4b5d36c63d16e">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetARUser
+: <a class="el" href="group__axidma__v9__0.html#ga72d1616af8d996f12db78473a75b54b6">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetBufAddr
+: <a class="el" href="group__axidma__v9__0.html#gaf858d9659197442c9e96856c206423c6">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetCtrl
+: <a class="el" href="group__axidma__v9__0.html#ga495e780d704ecf548d3536b3bb8961a5">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetId
+: <a class="el" href="group__axidma__v9__0.html#gaf3f333d78d115724bfcac84746d8cfa6">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetLength
+: <a class="el" href="group__axidma__v9__0.html#ga9875ecb45b47664b70d74e8810fd5cf0">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetStride
+: <a class="el" href="group__axidma__v9__0.html#ga29a75b8f1de16a347544e37b48d8129c">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetSts
+: <a class="el" href="group__axidma__v9__0.html#gaf2448f2b2ac172da0d19adeae3cc4c48">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetTDest
+: <a class="el" href="group__axidma__v9__0.html#ga8c1e3dd04821568424ffc77caf11a851">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetTId
+: <a class="el" href="group__axidma__v9__0.html#gac14fa76311fd7e5fb59b81fd9e251f62">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetTUser
+: <a class="el" href="group__axidma__v9__0.html#ga7a2f9668058b7e4cdc89dffcce6086d3">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdGetVSize
+: <a class="el" href="group__axidma__v9__0.html#gad9f48ceb5b30d66bab23337edc35d2fe">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdHwCompleted
+: <a class="el" href="group__axidma__v9__0.html#ga20937b96fad07f286948f1af50590421">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdRead
+: <a class="el" href="group__axidma__v9__0.html#gaa738ffd392c7ae1e844fab340ba50fee">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdRingAckIrq
+: <a class="el" href="group__axidma__v9__0.html#ga9e782e3715c1d2dd03e5d03434f47319">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingBusy
+: <a class="el" href="group__axidma__v9__0.html#gaf7c291190c92ce93d72f95c5b04ef1d4">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingCntCalc
+: <a class="el" href="group__axidma__v9__0.html#ga98555b607a9ec831dc6473e77515bb4b">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetCnt
+: <a class="el" href="group__axidma__v9__0.html#gac62389e25e6775026cf1be6c383e665b">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetCurrBd
+: <a class="el" href="group__axidma__v9__0.html#ga21aa8dbf6eabf9146097d9b3cc91c574">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetError
+: <a class="el" href="group__axidma__v9__0.html#ga24cd47cdbfac0813e0d9caf966a1a3d2">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetFreeCnt
+: <a class="el" href="group__axidma__v9__0.html#ga415cf0c379fef0104f9f52881ead13a7">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetIrq
+: <a class="el" href="group__axidma__v9__0.html#ga7a9d2103e6d09fc3850b34a6386dc803">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingGetSr
+: <a class="el" href="group__axidma__v9__0.html#ga740fa349c7811de2b7bae5cf83eb445e">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingHwIsStarted
+: <a class="el" href="group__axidma__v9__0.html#ga766bed2454969636d827fb79faeeee97">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingIntDisable
+: <a class="el" href="group__axidma__v9__0.html#ga0269e07693c731cf7721c6f19f8eb69b">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingIntEnable
+: <a class="el" href="group__axidma__v9__0.html#ga2518030938ab80081f6896fc5589682c">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingIntGetEnabled
+: <a class="el" href="group__axidma__v9__0.html#gadbb17169213d8af8b50e6dee7f7b6d8b">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingMemCalc
+: <a class="el" href="group__axidma__v9__0.html#ga6899085c400b8f453381b305ac5521d9">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingNext
+: <a class="el" href="group__axidma__v9__0.html#ga4b7e75d1acf86428bd79fcd0d1c13745">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingPrev
+: <a class="el" href="group__axidma__v9__0.html#ga86c6d4b9c4f8766634d46a3078eadc8a">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdRingSnapShotCurrBd
+: <a class="el" href="group__axidma__v9__0.html#ga0d79253861939c76e6d440ecde2b6edd">xaxidma_bdring.h</a>
+</li>
+<li>XAxiDma_BdSetARCache
+: <a class="el" href="group__axidma__v9__0.html#gac7d8a383cd6d5aff6ee36c3a3db20cbf">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetARUser
+: <a class="el" href="group__axidma__v9__0.html#gae89253197f1aef6582d5cda3e49f8ead">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetId
+: <a class="el" href="group__axidma__v9__0.html#ga53eeff085fd39a91b855939f13fe76f3">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetStride
+: <a class="el" href="group__axidma__v9__0.html#ga58961be41e3c0bc2694444bfe37b6c27">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetTDest
+: <a class="el" href="group__axidma__v9__0.html#ga5f9b3088c4e16c7f5584610a43b17462">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetTId
+: <a class="el" href="group__axidma__v9__0.html#gaa5bc321894b77ca6194c867018d9fe12">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetTUser
+: <a class="el" href="group__axidma__v9__0.html#gacf41c0ebe00870b6cdd34e46698e081b">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdSetVSize
+: <a class="el" href="group__axidma__v9__0.html#ga383b2c0667bf5bafa22922168895bd5e">xaxidma_bd.h</a>
+</li>
+<li>XAxiDma_BdWrite
+: <a class="el" href="group__axidma__v9__0.html#gab3b7d771208c01701b35bce165332a9f">xaxidma_bd.h</a>
+</li>
+<li>XAXIDMA_BUFFLEN_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gaa7ede468ba17bf106101d4850184dc74">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CDESC_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga00ee7a235750d8795961223455407051">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CDESC_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga24b47801eed2ab0ba326b8b40d24f2b1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_COALESCE_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga280fd988ea7ec3fadfe7cf1293f39e36">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_CYCLIC_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga2d34bf268de2f2ef4d32351043835f68">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_KEYHOLE_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga8bdf83c8ba16d8217a2a6486a9b5b521">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga8534b07ed878f92d2062dc1680fb0391">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_RESET_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga33fda61f0837d37da36d3b72b90b0fba">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_CR_RUNSTOP_MASK
+: <a class="el" href="group__axidma__v9__0.html#gab0ebdf6b7776e79941efe1325aac5aa9">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_DELAY_MASK
+: <a class="el" href="group__axidma__v9__0.html#gae3ad7ae6b5814b99de67bba06ec77ed1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_DESC_LSB_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga170ce0e12eb12686a03e006610e2acd2">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_DESTADDR_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga3a54e372851dbae81c33997ef2ba8d2f">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_DESTADDR_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga4e98e82ed389c23918315d833b457ea9">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_ALL_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga4102192c408420feb5b7db14d47c6d5c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_DECODE_MASK
+: <a class="el" href="group__axidma__v9__0.html#gaa19b93d226e97afd08d3869dc530b692">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_INTERNAL_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga87ac559811703a8ca33fc6b427913f2b">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_SG_DEC_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga43ecb16ea8e8d09a33364a17610d8909">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_SG_INT_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga1f9ef0d10a7456a25a4b244955659d65">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_SG_SLV_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga0f0d25fd68716e868742115c9a28c18c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_ERR_SLAVE_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga6d50743f6c9d6474561f6727eb956915">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_GetRxIndexRing
+: <a class="el" href="group__axidma__v9__0.html#gaf03e87b58cf2f9800e6260fda3745631">xaxidma.h</a>
+</li>
+<li>XAxiDma_GetRxRing
+: <a class="el" href="group__axidma__v9__0.html#ga6373ac3baa5365607f6727f4e2ece7a5">xaxidma.h</a>
+</li>
+<li>XAxiDma_GetTxRing
+: <a class="el" href="group__axidma__v9__0.html#ga9d91f29c6dc41f2106e097f1f9957a6e">xaxidma.h</a>
+</li>
+<li>XAXIDMA_HALTED_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga70671c3d8cd1e51c56723e298d268cce">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_HasSg
+: <a class="el" href="group__axidma__v9__0.html#ga18dd03026dd6c0ebd13526116c09ccae">xaxidma.h</a>
+</li>
+<li>XAXIDMA_IDLE_MASK
+: <a class="el" href="group__axidma__v9__0.html#gaa3538e8c2a6e024641259c85368667f0">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_IntrAckIrq
+: <a class="el" href="group__axidma__v9__0.html#ga9ff0d2e5b50846e4b6a2d683283c10d5">xaxidma.h</a>
+</li>
+<li>XAxiDma_IntrDisable
+: <a class="el" href="group__axidma__v9__0.html#ga1936b497c0fa61d326807e5ed8dd572b">xaxidma.h</a>
+</li>
+<li>XAxiDma_IntrEnable
+: <a class="el" href="group__axidma__v9__0.html#gadac28afa26e2cb55bdada1ee3c016c52">xaxidma.h</a>
+</li>
+<li>XAxiDma_IntrGetEnabled
+: <a class="el" href="group__axidma__v9__0.html#gadba63ad7c0a784d569736a8d1eb7c367">xaxidma.h</a>
+</li>
+<li>XAxiDma_IntrGetIrq
+: <a class="el" href="group__axidma__v9__0.html#ga6a0eb17bcfcaf3331e01855d302f5f0e">xaxidma.h</a>
+</li>
+<li>XAXIDMA_IRQ_ALL_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga8347e41a5c01bdabefce9c8484a7ced1">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_IRQ_DELAY_MASK
+: <a class="el" href="group__axidma__v9__0.html#gadc4a45d09bcbf852f29b880935d607dc">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_IRQ_ERROR_MASK
+: <a class="el" href="group__axidma__v9__0.html#ga6ceb68e74761910e4253795a9b4992cf">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_IRQ_IOC_MASK
+: <a class="el" href="group__axidma__v9__0.html#gae420f2ad87e1e00456a6ee3a80d2480d">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_MICROMODE_MIN_BUF_ALIGN
+: <a class="el" href="group__axidma__v9__0.html#gaf0f7e862f42d26800868816eea2a949b">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_ReadReg
+: <a class="el" href="group__axidma__v9__0.html#ga99f615c527035db697545614fff86bf2">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_CDESC0_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gad80414a88feceb1da4b9f77096d1d590">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_CDESC0_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga79d2eca90f2554b8c893b2f9a70c795c">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_NDESC_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga6fc559cbc93b62195de6ecaf25492467">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gadfdc083e0b249c04624a66e700d7a7c4">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_TDESC0_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gaa9b5991af857e7bac763311fd917978d">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_RX_TDESC0_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gadfa4d02f0dd1fd005c695e9977457722">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_SGCTL_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gab26580f9b4a94b3ab1d373ddeab7b3b6">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_SR_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga50d6957f8447d4eab9e444666730f692">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_SRCADDR_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gafaafc49751e690d818d604efe368c481">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_SRCADDR_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga386fad6446792679302b362ed34022cf">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_TDESC_MSB_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga6063ffb7cb46cdca589e6f31069f7758">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_TDESC_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#gac8626fb2bed7230a2c82a7e1db0ddd35">xaxidma_hw.h</a>
+</li>
+<li>XAXIDMA_TX_OFFSET
+: <a class="el" href="group__axidma__v9__0.html#ga88232281611059fd669f0339888cd44e">xaxidma_hw.h</a>
+</li>
+<li>XAxiDma_WriteReg
+: <a class="el" href="group__axidma__v9__0.html#ga96d7b2834ae100f53627ca961393e9a2">xaxidma_hw.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>

thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/globals_func.html

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+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
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+ <tr style="height: 56px;">
+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li class="current"><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow4" class="tabs3">
+    <ul class="tablist">
+      <li class="current"><a href="#index_x"><span>x</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;
+
+<h3><a class="anchor" id="index_x"></a>- x -</h3><ul>
+<li>XAxiDma_BdGetAppWord()
+: <a class="el" href="group__axidma__v9__0.html#ga9d2814e4249884e68fe9e6f370920ca4">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdRingAlloc()
+: <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingCheck()
+: <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingClone()
+: <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingCreate()
+: <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingDumpRegs()
+: <a class="el" href="group__axidma__v9__0.html#gaffa661a9a2467c1e274842c147531cea">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingFree()
+: <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingFromHw()
+: <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingGetCoalesce()
+: <a class="el" href="group__axidma__v9__0.html#ga0d3794bbccf028da8e94407d061dfc68">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingSetCoalesce()
+: <a class="el" href="group__axidma__v9__0.html#gaaebba5c661e04485582e887e74dbeb94">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingStart()
+: <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingToHw()
+: <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdRingUnAlloc()
+: <a class="el" href="group__axidma__v9__0.html#gac58b1ab7a89890142baf67211772d3ce">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_BdSetAppWord()
+: <a class="el" href="group__axidma__v9__0.html#gafc6434a23594c20c2b601f010a979e48">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdSetBufAddr()
+: <a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdSetBufAddrMicroMode()
+: <a class="el" href="group__axidma__v9__0.html#ga8947514b5acfea6298d0f969f3d2b97e">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdSetCtrl()
+: <a class="el" href="group__axidma__v9__0.html#ga4eb2615ac89054e982c3f3c37f0ddb52">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_BdSetLength()
+: <a class="el" href="group__axidma__v9__0.html#ga4056035d8e7c90a68fa954c60d021e07">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_Busy()
+: <a class="el" href="group__axidma__v9__0.html#gaff68c0ba3e9e25dfe5e39153301862f8">xaxidma.c</a>
+</li>
+<li>XAxiDma_CfgInitialize()
+: <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">xaxidma.c</a>
+</li>
+<li>XAxiDma_DumpBd()
+: <a class="el" href="group__axidma__v9__0.html#ga53983f629aba5b4ebf27f803a7a9284e">xaxidma_bd.c</a>
+</li>
+<li>XAxiDma_LookupConfig()
+: <a class="el" href="group__axidma__v9__0.html#ga0cbcf5259635ea3c336fe5413c98f75c">xaxidma.h</a>
+</li>
+<li>XAxiDma_Pause()
+: <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">xaxidma.c</a>
+</li>
+<li>XAxiDma_Reset()
+: <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">xaxidma.c</a>
+</li>
+<li>XAxiDma_ResetIsDone()
+: <a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">xaxidma.c</a>
+</li>
+<li>XAxiDma_Resume()
+: <a class="el" href="group__axidma__v9__0.html#ga847cd9a0255fcb444bce58b945de8574">xaxidma.c</a>
+</li>
+<li>XAxiDma_SelectCyclicMode()
+: <a class="el" href="group__axidma__v9__0.html#ga2d93bfcf1c3e34cb9fc4a22da6148dc5">xaxidma.c</a>
+</li>
+<li>XAxiDma_SelectKeyHole()
+: <a class="el" href="group__axidma__v9__0.html#ga5becc8b0f9945af34e372ced2b37aebb">xaxidma.c</a>
+</li>
+<li>XAxiDma_Selftest()
+: <a class="el" href="group__axidma__v9__0.html#gad4ea3039216916336ae1c7598ff26afc">xaxidma.h</a>
+</li>
+<li>XAxiDma_SimpleTransfer()
+: <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">xaxidma.c</a>
+</li>
+<li>XAxiDma_StartBdRingHw()
+: <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">xaxidma_bdring.c</a>
+</li>
+<li>XAxiDma_UpdateBdRingCDesc()
+: <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">xaxidma_bdring.c</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>

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+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li class="current"><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li><a href="globals_defs.html"><span>Macros</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="contents">
+&#160;<ul>
+<li>XAxiDma
+: <a class="el" href="group__axidma__v9__0.html#gac08fe7cb6508a133a7ef036bba7df5b5">xaxidma.h</a>
+</li>
+<li>XAxiDma_Bd
+: <a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">xaxidma_bd.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>

thirdparty/xilinx/orig/axidma_v9_0/doc/html/api/index.html

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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+  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li class="current"><a href="index.html"><span>Overview</span></a></li>
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">axidma_v9_0 Documentation</div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock"><p>This is the driver API for the AXI DMA engine.For a full description of DMA features, please see the hardware spec. This driver supports the following features:</p>
+<ul>
+<li>Scatter-Gather DMA (SGDMA)</li>
+<li>Simple DMA</li>
+<li>Interrupts</li>
+<li>Programmable interrupt coalescing for SGDMA</li>
+<li>APIs to manage Buffer Descriptors (BD) movement to and from the SGDMA engine</li>
+</ul>
+<p><b>Simple DMA</b></p>
+<p>Simple DMA allows the application to define a single transaction between DMA and Device. It has two channels: one from the DMA to Device and the other from Device to DMA. Application has to set the buffer address and length fields to initiate the transfer in respective channel.</p>
+<p><b>Transactions</b></p>
+<p>The object used to describe a transaction is referred to as a Buffer Descriptor (BD). Buffer descriptors are allocated in the user application. The user application needs to set buffer address, transfer length, and control information for this transfer. The control information includes SOF and EOF. Definition of those masks are in <a class="el" href="xaxidma__hw_8h.html">xaxidma_hw.h</a></p>
+<p><b>Scatter-Gather DMA</b></p>
+<p>SGDMA allows the application to define a list of transactions in memory which the hardware will process without further application intervention. During this time, the application is free to continue adding more work to keep the Hardware busy.</p>
+<p>User can check for the completion of transactions through polling the hardware, or interrupts.</p>
+<p>SGDMA processes whole packets. A packet is defined as a series of data bytes that represent a message. SGDMA allows a packet of data to be broken up into one or more transactions. For example, take an Ethernet IP packet which consists of a 14 byte header followed by a 1 or more bytes of payload. With SGDMA, the application may point a BD to the header and another BD to the payload, then transfer them as a single message. This strategy can make a TCP/IP stack more efficient by allowing it to keep packet header and data in different memory regions instead of assembling packets into contiguous blocks of memory.</p>
+<p><b>BD Ring Management</b></p>
+<p>BD rings are shared by the software and the hardware.</p>
+<p>The hardware expects BDs to be setup as a linked list. The DMA hardware walks through the list by following the next pointer field of a completed BD. The hardware stops processing when the just completed BD is the same as the BD specified in the Tail Ptr register in the hardware.</p>
+<p>The last BD in the ring is linked to the first BD in the ring.</p>
+<p>All BD management are done inside the driver. The user application should not directly modify the BD fields. Modifications to the BD fields should always go through the specific API functions.</p>
+<p>Within the ring, the driver maintains four groups of BDs. Each group consists of 0 or more adjacent BDs:</p>
+<ul>
+<li>Free: The BDs that can be allocated by the application with <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a>.</li>
+<li>Pre-process: The BDs that have been allocated with <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a>. These BDs are under application control. The application modifies these BDs through driver API to prepare them for DMA transactions.</li>
+<li>Hardware: The BDs that have been enqueued to hardware with <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b" title="Enqueue a set of BDs to hardware that were previously allocated by XAxiDma_BdRingAlloc(). ">XAxiDma_BdRingToHw()</a>. These BDs are under hardware control and may be in a state of awaiting hardware processing, in process, or processed by hardware. It is considered an error for the application to change BDs while they are in this group. Doing so can cause data corruption and lead to system instability.</li>
+<li>Post-process: The BDs that have been processed by hardware and have been extracted from the Hardware group with <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c" title="Returns a set of BD(s) that have been processed by hardware. ">XAxiDma_BdRingFromHw()</a>. These BDs are under application control. The application can check the transfer status of these BDs. The application use <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7" title="Frees a set of BDs that had been previously retrieved with XAxiDma_BdRingFromHw(). ">XAxiDma_BdRingFree()</a> to put them into the Free group.</li>
+</ul>
+<p>BDs are expected to transition in the following way for continuous DMA transfers: </p><pre></pre><pre>        <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a>                   <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b" title="Enqueue a set of BDs to hardware that were previously allocated by XAxiDma_BdRingAlloc(). ">XAxiDma_BdRingToHw()</a>
+  Free ------------------------&gt; Pre-process ----------------------&gt; Hardware
+                                                                     |
+   /|\                                                               |
+    |   <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7" title="Frees a set of BDs that had been previously retrieved with XAxiDma_BdRingFromHw(). ">XAxiDma_BdRingFree()</a>                  <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c" title="Returns a set of BD(s) that have been processed by hardware. ">XAxiDma_BdRingFromHw()</a> |
+    +--------------------------- Post-process &lt;----------------------+</pre><pre></pre><p>When a DMA transfer is to be cancelled before enqueuing to hardware, application can return the requested BDs to the Free group using <a class="el" href="group__axidma__v9__0.html#gac58b1ab7a89890142baf67211772d3ce" title="Fully or partially undo an XAxiDma_BdRingAlloc() operation. ">XAxiDma_BdRingUnAlloc()</a>, as shown below: </p><pre></pre><pre>        <a class="el" href="group__axidma__v9__0.html#gac58b1ab7a89890142baf67211772d3ce" title="Fully or partially undo an XAxiDma_BdRingAlloc() operation. ">XAxiDma_BdRingUnAlloc()</a>
+  Free &lt;----------------------- Pre-process</pre><pre></pre><p>The API provides functions for BD list traversal:</p><ul>
+<li><a class="el" href="group__axidma__v9__0.html#ga4b7e75d1acf86428bd79fcd0d1c13745" title="Return the next BD in the ring. ">XAxiDma_BdRingNext()</a></li>
+<li><a class="el" href="group__axidma__v9__0.html#ga86c6d4b9c4f8766634d46a3078eadc8a" title="Return the previous BD in the ring. ">XAxiDma_BdRingPrev()</a></li>
+</ul>
+<p>These functions should be used with care as they do not understand where one group ends and another begins.</p>
+<p><b>SGDMA Descriptor Ring Creation</b></p>
+<p>BD ring is created using <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b" title="Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring...">XAxiDma_BdRingCreate()</a>. The memory for the BD ring is allocated by the application, and it has to be contiguous. Physical address is required to setup the BD ring.</p>
+<p>The applicaiton can use <a class="el" href="group__axidma__v9__0.html#ga6899085c400b8f453381b305ac5521d9" title="Use this macro at initialization time to determine how many bytes of memory are required to contain a...">XAxiDma_BdRingMemCalc()</a> to find out the amount of memory needed for a certain number of BDs. <a class="el" href="group__axidma__v9__0.html#ga98555b607a9ec831dc6473e77515bb4b" title="Use this macro at initialization time to determine how many BDs will fit within the given memory cons...">XAxiDma_BdRingCntCalc()</a> can be used to find out how many BDs can be allocated for certain amount of memory.</p>
+<p>A helper function, <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b" title="Clone the given BD into every BD in the ring. ">XAxiDma_BdRingClone()</a>, can speed up the BD ring setup if the BDs have same types of controls, for example, SOF and EOF. After using the <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b" title="Clone the given BD into every BD in the ring. ">XAxiDma_BdRingClone()</a>, the application only needs to setup the buffer address and transfer length. Note that certain BDs in one packet, for example, the first BD and the last BD, may need to setup special control information.</p>
+<p><b>Descriptor Ring State Machine</b></p>
+<p>There are two states of the BD ring:</p>
+<ul>
+<li>HALTED (H), where hardware is not running</li>
+<li>NOT HALTED (NH), where hardware is running</li>
+</ul>
+<p>The following diagram shows the state transition for the DMA engine:</p>
+<pre>
+  _____ <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f" title="Start a DMA channel and Allow DMA transactions to commence on a given channel if descriptors are read...">XAxiDma_StartBdRingHw()</a>, or <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3" title="Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given ch...">XAxiDma_BdRingStart()</a>,   ______
+  |   |               or <a class="el" href="group__axidma__v9__0.html#ga847cd9a0255fcb444bce58b945de8574" title="Resume DMA transactions on both channels. ">XAxiDma_Resume()</a>                    |    |
+  | H |-----------------------------------------------------&gt;| NH |
+  |   |&lt;-----------------------------------------------------|    |
+  -----   <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c" title="Pause DMA transactions on both channels. ">XAxiDma_Pause()</a> or <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f" title="Reset both TX and RX channels of a DMA engine. ">XAxiDma_Reset()</a>                 ------
+</pre><p><b>Interrupt Coalescing</b></p>
+<p>SGDMA provides control over the frequency of interrupts through interrupt coalescing. The DMA engine provides two ways to tune the interrupt coalescing:</p>
+<ul>
+<li>The packet threshold counter. Interrupt will fire once the programmable number of packets have been processed by the engine.</li>
+<li>The packet delay timer counter. Interrupt will fire once the programmable amount of time has passed after processing the last packet, and no new packets to process. Note that the interrupt will only fire if at least one packet has been processed.</li>
+</ul>
+<p><b> Interrupt </b></p>
+<p>Interrupts are handled by the user application. Each DMA channel has its own interrupt ID. The driver provides APIs to enable/disable interrupt, and tune the interrupt frequency regarding to packet processing frequency.</p>
+<p><b> Software Initialization </b></p>
+<p>To use the Simple mode DMA engine for transfers, the following setup is required:</p>
+<ul>
+<li>DMA Initialization using <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77" title="This function initializes a DMA engine. ">XAxiDma_CfgInitialize()</a> function. This step initializes a driver instance for the given DMA engine and resets the engine.</li>
+<li>Enable interrupts if chosen to use interrupt mode. The application is responsible for setting up the interrupt system, which includes providing and connecting interrupt handlers and call back functions, before enabling the interrupts.</li>
+<li>Set the buffer address and length field in respective channels to start the DMA transfer</li>
+</ul>
+<p>To use the SG mode DMA engine for transfers, the following setup are required:</p>
+<ul>
+<li>DMA Initialization using <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77" title="This function initializes a DMA engine. ">XAxiDma_CfgInitialize()</a> function. This step initializes a driver instance for the given DMA engine and resets the engine.</li>
+<li>BD Ring creation. A BD ring is needed per DMA channel and can be built by calling <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b" title="Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring...">XAxiDma_BdRingCreate()</a>.</li>
+<li>Enable interrupts if chose to use interrupt mode. The application is responsible for setting up the interrupt system, which includes providing and connecting interrupt handlers and call back functions, before enabling the interrupts.</li>
+<li>Start a DMA transfer: Call <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3" title="Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given ch...">XAxiDma_BdRingStart()</a> to start a transfer for the first time or after a reset, and <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b" title="Enqueue a set of BDs to hardware that were previously allocated by XAxiDma_BdRingAlloc(). ">XAxiDma_BdRingToHw()</a> if the channel is already started. Calling <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b" title="Enqueue a set of BDs to hardware that were previously allocated by XAxiDma_BdRingAlloc(). ">XAxiDma_BdRingToHw()</a> when a DMA channel is not running will not put the BDs to the hardware, and the BDs will be processed later when the DMA channel is started through <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3" title="Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given ch...">XAxiDma_BdRingStart()</a>.</li>
+</ul>
+<p><b> How to start DMA transactions </b></p>
+<p>The user application uses <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b" title="Enqueue a set of BDs to hardware that were previously allocated by XAxiDma_BdRingAlloc(). ">XAxiDma_BdRingToHw()</a> to submit BDs to the hardware to start DMA transfers.</p>
+<p>For both channels, if the DMA engine is currently stopped (using <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c" title="Pause DMA transactions on both channels. ">XAxiDma_Pause()</a>), the newly added BDs will be accepted but not processed until the DMA engine is started, using <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3" title="Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given ch...">XAxiDma_BdRingStart()</a>, or resumed, using <a class="el" href="group__axidma__v9__0.html#ga847cd9a0255fcb444bce58b945de8574" title="Resume DMA transactions on both channels. ">XAxiDma_Resume()</a>.</p>
+<p><b> Software Post-Processing on completed DMA transactions </b></p>
+<p>If the interrupt system has been set up and the interrupts are enabled, a DMA channels notifies the software about the completion of a transfer through interrupts. Otherwise, the user application can poll for completions of the BDs, using <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c" title="Returns a set of BD(s) that have been processed by hardware. ">XAxiDma_BdRingFromHw()</a> or <a class="el" href="group__axidma__v9__0.html#ga20937b96fad07f286948f1af50590421" title="Check whether a BD has completed in hardware. ">XAxiDma_BdHwCompleted()</a>.</p>
+<ul>
+<li>Once BDs are finished by a channel, the application first needs to fetch them from the channel using <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c" title="Returns a set of BD(s) that have been processed by hardware. ">XAxiDma_BdRingFromHw()</a>.</li>
+<li>On the TX side, the application now could free the data buffers attached to those BDs as the data in the buffers has been transmitted.</li>
+<li>On the RX side, the application now could use the received data in the buffers attached to those BDs.</li>
+<li>For both channels, completed BDs need to be put back to the Free group using <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7" title="Frees a set of BDs that had been previously retrieved with XAxiDma_BdRingFromHw(). ">XAxiDma_BdRingFree()</a>, so they can be used for future transactions.</li>
+<li>On the RX side, it is the application's responsibility to have BDs ready to receive data at any time. Otherwise, the RX channel refuses to accept any data if it has no RX BDs.</li>
+</ul>
+<p><b> Examples </b></p>
+<p>We provide five examples to show how to use the driver API:</p><ul>
+<li>One for SG interrupt mode (xaxidma_example_sg_intr.c), multiple BD/packets transfer</li>
+<li>One for SG polling mode (xaxidma_example_sg_poll.c), single BD transfer.</li>
+<li>One for SG polling mode (xaxidma_poll_multi_pkts.c), multiple BD/packets transfer</li>
+<li>One for simple polling mode (xaxidma_example_simple_poll.c)</li>
+<li>One for simple Interrupt mode (xaxidma_example_simple_intr.c)</li>
+</ul>
+<p><b> Address Translation </b></p>
+<p>All buffer addresses and BD addresses for the hardware are physical addresses. The user application is responsible to provide physical buffer address for the BD upon BD ring creation. The user application accesses BD through its virtual addess. The driver maintains the address translation between the physical and virtual address for BDs.</p>
+<p><b> Cache Coherency </b></p>
+<p>This driver expects all application buffers attached to BDs to be in cache coherent memory. If cache is used in the system, buffers for transmit MUST be flushed from the cache before passing the associated BD to this driver. Buffers for receive MUST be invalidated before accessing the data.</p>
+<p><b> Alignment </b></p>
+<p>For BDs:</p>
+<p>Minimum alignment is defined by the constant XAXIDMA_BD_MINIMUM_ALIGNMENT. This is the smallest alignment allowed by both hardware and software for them to properly work.</p>
+<p>If the descriptor ring is to be placed in cached memory, alignment also MUST be at least the processor's cache-line size. Otherwise, system instability occurs. For alignment larger than the cache line size, multiple cache line size alignment is required.</p>
+<p>Aside from the initial creation of the descriptor ring (see <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b" title="Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring...">XAxiDma_BdRingCreate()</a>), there are no other run-time checks for proper alignment of BDs.</p>
+<p>For application data buffers:</p>
+<p>Application data buffers may reside on any alignment if DRE is built into the hardware. Otherwise, application data buffer must be word-aligned. The word is defined by XPAR_AXIDMA_0_M_AXIS_MM2S_TDATA_WIDTH for transmit and XPAR_AXIDMA_0_S_AXIS_S2MM_TDATA_WIDTH for receive.</p>
+<p>For scatter gather transfers that have more than one BDs in the chain of BDs, Each BD transfer length must be multiple of word too. Otherwise, internal error happens in the hardware.</p>
+<p><b> Error Handling </b></p>
+<p>The DMA engine will halt on all error conditions. It requires the software to do a reset before it can start process new transfer requests.</p>
+<p><b> Restart After Stopping </b></p>
+<p>After the DMA engine has been stopped (through reset or reset after an error) the software keeps track of the current BD pointer when reset happens, and processing of BDs can be resumed through <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3" title="Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given ch...">XAxiDma_BdRingStart()</a>.</p>
+<p><b> Limitations </b></p>
+<p>This driver does not have any mechanisms for mutual exclusion. It is up to the application to provide this protection.</p>
+<p><b> Hardware Defaults &amp; Exclusive Use </b></p>
+<p>After the initialization or reset, the DMA engine is in the following default mode:</p><ul>
+<li>All interrupts are disabled.</li>
+<li>Interrupt coalescing counter is 1.</li>
+<li>The DMA engine is not running (halted). Each DMA channel is started separately, using <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f" title="Start a DMA channel and Allow DMA transactions to commence on a given channel if descriptors are read...">XAxiDma_StartBdRingHw()</a> if no BDs are setup for transfer yet, or <a class="el" href="group__axidma__v9__0.html#gaafd18a1df185c30b4745c147e3295ac3" title="Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given ch...">XAxiDma_BdRingStart()</a> otherwise.</li>
+</ul>
+<p>The driver has exclusive use of the registers and BDs. All accesses to the registers and BDs should go through the driver interface.</p>
+<p><b> Debug Print </b></p>
+<p>To see the debug print for the driver, please put "-DDEBUG" as the extra compiler flags in software platform settings. Also comment out the line in xdebug.h: "#undef DEBUG".</p>
+<p><b>Changes From v1.00a</b></p>
+<p>. We have changes return type for <a class="el" href="group__axidma__v9__0.html#gac1a9cb01ba6cd686ee08245f5e08cb22" title="Set the BD&#39;s buffer address. ">XAxiDma_BdSetBufAddr()</a> from void to int . We added <a class="el" href="group__axidma__v9__0.html#ga0cbcf5259635ea3c336fe5413c98f75c" title="Look up the hardware configuration for a device instance. ">XAxiDma_LookupConfig()</a> so that user does not need to look for the hardware settings anymore.</p>
+<pre>
+MODIFICATION HISTORY:</pre><pre>Ver   Who  Date     Changes
+----- ---- -------- -------------------------------------------------------
+1.00a jz   05/18/10 First release
+2.00a jz   08/10/10 Second release, added in <a class="el" href="xaxidma__g_8c.html">xaxidma_g.c</a>, <a class="el" href="xaxidma__sinit_8c.html">xaxidma_sinit.c</a>,
+                    updated tcl file, added <a class="el" href="xaxidma__porting__guide_8h.html">xaxidma_porting_guide.h</a>
+3.00a jz   11/22/10 Support IP core parameters change
+4.00a rkv  02/22/11 Added support for simple DMA mode
+      	      New API added for simple DMA mode are</p><ul>
+<li>XAxiDma_Busy</li>
+<li>XAxiDma_SimpleTransfer
+      	      New Macros added for simple DMA mode are<ul>
+<li>XAxiDma_HasSg</li>
+<li>XAxiDma_IntrEnable</li>
+<li>XAxiDma_IntrGetEnabled</li>
+<li>XAxiDma_IntrDisable</li>
+<li>XAxiDma_IntrGetIrq</li>
+<li>XAxiDma_IntrAckIrq
+5.00a srt  08/25/11  Added support for memory barrier and modified
+      		Cache Macros to have a common API for Microblaze
+      		and Zynq.
+6.00a srt  01/24/12 Added support for Multi-Channel DMA mode.</li>
+</ul>
+</li>
+</ul>
+</pre><pre>Changed APIs:
+      		* <a class="el" href="group__axidma__v9__0.html#ga6373ac3baa5365607f6727f4e2ece7a5" title="Get Receive (Rx) Ring ptr. ">XAxiDma_GetRxRing(InstancePtr, RingIndex)</a>
+      		* XAxiDma_Start(XAxiDma * InstancePtr, int RingIndex)
+      		* XAxiDma_Started(XAxiDma * InstancePtr, int RingIndex)
+      		* XAxiDma_Pause(XAxiDma * InstancePtr, int RingIndex)
+      		* XAxiDma_Resume(XAxiDma * InstancePtr, int RingIndex)
+      		* XAxiDma_SimpleTransfer(<a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> *InstancePtr,
+       					u32 BuffAddr, u32 Length,
+      					int Direction, int RingIndex)
+      		* XAxiDma_StartBdRingHw(<a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> * RingPtr,
+      				int RingIndex)
+      		* XAxiDma_BdRingStart(<a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> * RingPtr,
+      					 int RingIndex)
+      		* XAxiDma_BdRingToHw(<a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> * RingPtr,
+       			int NumBd, XAxiDma_Bd * BdSetPtr, int RingIndex)
+      		* XAxiDma_BdRingDumpRegs(<a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> * RingPtr,
+      					 int RingIndex)
+      		* XAxiDma_BdRingSnapShotCurrBd(<a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> * RingPtr,
+      					 int RingIndex)
+      		* XAxiDma_BdSetLength(XAxiDma_Bd *BdPtr,
+      				u32 LenBytes, u32 LengthMask)
+      		* <a class="el" href="group__axidma__v9__0.html#ga135667574b201437cfbdbecd8b348ee0" title="Get the actual transfer length of a BD. ">XAxiDma_BdGetActualLength(BdPtr, LengthMask)</a>
+      		* <a class="el" href="group__axidma__v9__0.html#ga9875ecb45b47664b70d74e8810fd5cf0" title="Retrieve the length field value from the given BD. ">XAxiDma_BdGetLength(BdPtr, LengthMask)</a></p><ul>
+<li>New APIs
+      		* XAxiDma_SelectKeyHole(<a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> *InstancePtr,
+      					int Direction, int Select)
+      		* XAxiDma_UpdateBdRingCDesc(<a class="el" href="struct_x_axi_dma___bd_ring.html" title="Container structure for descriptor storage control. ">XAxiDma_BdRing</a> * RingPtr,
+      					int RingIndex)
+7.00a srt  06/18/12  All the APIs changed in v6_00_a are reverted back for
+      	       backward compatibility.<ul>
+<li>New API:
+      		  <a class="el" href="group__axidma__v9__0.html#gaf03e87b58cf2f9800e6260fda3745631" title="Get Receive (Rx) Ring ptr of a Index. ">XAxiDma_GetRxIndexRing(InstancePtr, RingIndex)</a>
+7.01a srt  10/26/12  - Fixed issue with driver as it fails with IP version
+      	         &lt; 6.00a as the parameter C_NUM_*_CHANNELS is not
+      		 applicable.</li>
+</ul>
+</li>
+<li>Changed the logic of MCDMA BD fields Set APIs, to
+      		 clear the field first and then set it.
+7.02a srt  01/23/13  Replaced *_TDATA_WIDTH parameters to *_DATA_WIDTH
+      	       (CR 691867)
+      	       Updated DDR base address for IPI designs (CR 703656).
+8.0   adk  19/12/13  Updated as per the New Tcl API's
+      srt  01/29/14  Added support for Micro DMA Mode and cyclic mode of
+      	       operations.</li>
+</ul>
+</pre><pre>New APIs:
+      		* XAxiDma_SelectCyclicMode(<a class="el" href="struct_x_axi_dma.html" title="The XAxiDma driver instance data. ">XAxiDma</a> *InstancePtr,
+      					int Direction, int Select)
+			* XAxiDma_BdSetBufAddrMicroMode(XAxiDma_Bd*, u32)
+8.1   adk  20/01/15  Added support for peripheral test. Created the self
+      	       test example to include it on peripheral test's(CR#823144).
+8.1   adk  29/01/15  Added the sefltest api (XAxiDma_Selftest) to the driver source files
+		      (<a class="el" href="xaxidma__selftest_8c.html">xaxidma_selftest.c</a>) and called this from the selftest example
+9.0 	adk  27/07/15  Added support for 64-bit Addressing.
+9.0   adk  19/08/15  Fixed CR#873125 DMA SG Mode example tests are failing on
+      	       HW in 2015.3.</pre><pre></pre> </div></div><!-- contents -->
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+<div class="title">APIs</div>  </div>
+</div><!--header-->
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+<div class="textblock">Here is a list of all modules:</div><div class="directory">
+<table class="directory">
+<tr id="row_0_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><a class="el" href="group__axidma__v9__0.html" target="_self">Axidma_v9_0</a></td><td class="desc">This file implements DMA engine-wise initialization and control functions </td></tr>
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+  <div class="headertitle">
+<div class="title">XAxiDma Struct Reference<div class="ingroups"><a class="el" href="group__axidma__v9__0.html">Axidma_v9_0</a></div></div>  </div>
+</div><!--header-->
+<div class="contents">
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>An instance must be allocated for each DMA engine in use. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a663f5757eabe6b1b8813ed5fdb0d0edb"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma::AddrWidth</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Address Width. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize()</a>, and <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>.</p>
+
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+   <div id="projectname">axidma_v9_0
+   </div>
+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
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+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.10 -->
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+    <ul class="tablist">
+      <li><a href="index.html"><span>Overview</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
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+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div class="header">
+  <div class="headertitle">
+<div class="title">XAxiDma_BdRing Struct Reference<div class="ingroups"><a class="el" href="group__axidma__v9__0.html">Axidma_v9_0</a></div></div>  </div>
+</div><!--header-->
+<div class="contents">
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>If address translation is enabled, then all addresses and pointers excluding FirstBdPhysAddr are expressed in terms of the virtual address. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a3c928d2f36e8daf845a70afdae2573a4"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRing::AllCnt</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Total Number of BDs for channel. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">XAxiDma_BdRingClone()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a2519fd626856e7ab0d822adc46aab7d8"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a>* XAxiDma_BdRing::BdaRestart</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>BD to load when channel is started. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a138fd282802e5f6ed3cb1d2505ede08a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XAxiDma_BdRing::ChanBase</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>physical base address </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaffa661a9a2467c1e274842c147531cea">XAxiDma_BdRingDumpRegs()</a>, <a class="el" href="group__axidma__v9__0.html#ga0d3794bbccf028da8e94407d061dfc68">XAxiDma_BdRingGetCoalesce()</a>, <a class="el" href="group__axidma__v9__0.html#gaaebba5c661e04485582e887e74dbeb94">XAxiDma_BdRingSetCoalesce()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize()</a>, <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">XAxiDma_Pause()</a>, <a class="el" href="group__axidma__v9__0.html#gaf73e1329e40c8ac1ae47a7d9c104af75">XAxiDma_ResetIsDone()</a>, <a class="el" href="group__axidma__v9__0.html#ga32ca6099d7926297a4c17cdb4a19511b">XAxiDma_SimpleTransfer()</a>, <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a6d41078607d5a8165e67d6483e40e9ab"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">UINTPTR XAxiDma_BdRing::FirstBdAddr</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Virtual address of 1st BD in list. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">XAxiDma_BdRingClone()</a>, and <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="add2c7d765c8d95eeb9d0f94a54775528"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">UINTPTR XAxiDma_BdRing::FirstBdPhysAddr</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Physical address of 1st BD in list. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, and <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a51ec0929002582a900d404502e9a1622"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRing::FreeCnt</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Number of allocatable BDs in free group. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f">XAxiDma_BdRingAlloc()</a>, <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">XAxiDma_BdRingClone()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7">XAxiDma_BdRingFree()</a>, and <a class="el" href="group__axidma__v9__0.html#gac58b1ab7a89890142baf67211772d3ce">XAxiDma_BdRingUnAlloc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a3e067ffdf2820a816f2d6dda6e3f9114"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a>* XAxiDma_BdRing::FreeHead</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>First BD in the free group. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f">XAxiDma_BdRingAlloc()</a>, <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, and <a class="el" href="group__axidma__v9__0.html#gac58b1ab7a89890142baf67211772d3ce">XAxiDma_BdRingUnAlloc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a7d35cb00bb50fff2e24c15f7d7d8dae0"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRing::HasStsCntrlStrm</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Whether has stscntrl stream. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, and <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ab49406dd2d9ec65e3f38d1cc3c880391"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRing::HwCnt</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Number of BDs in work group. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="af097be199cf9d1d62cf32f775309a4f3"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a>* XAxiDma_BdRing::HwHead</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>First BD in the work group. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, and <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a7abe8351de43377407c579cd158f2448"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a>* XAxiDma_BdRing::HwTail</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Last BD in the work group. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a912bf38e61c8b03995ece842426b3ccf"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRing::IsRxChannel</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Is this a receive channel. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize()</a>, <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a3743d05f930d7c04abb0693f2ef0b271"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">UINTPTR XAxiDma_BdRing::LastBdAddr</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Virtual address of last BD in the list. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, and <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="af0b3fe5c9b9123209b3000e0d95193ed"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">u32 XAxiDma_BdRing::Length</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Total size of ring in bytes. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="afd4e1620895f91a829354e131432d2b3"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRing::PostCnt</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Number of BDs in post-work group. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7">XAxiDma_BdRingFree()</a>, and <a class="el" href="group__axidma__v9__0.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a92668e60e10a940428e68f816c64eab6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a>* XAxiDma_BdRing::PostHead</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>First BD in the post-work group. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, and <a class="el" href="group__axidma__v9__0.html#gad2ac76e5a39486896cd484e51d2898c7">XAxiDma_BdRingFree()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a68e8042d227f7a40821a478deb063215"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRing::PreCnt</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Number of BDs in pre-work group. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga44003cd704b7d4868d1dc00bb433a91f">XAxiDma_BdRingAlloc()</a>, <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, and <a class="el" href="group__axidma__v9__0.html#gac58b1ab7a89890142baf67211772d3ce">XAxiDma_BdRingUnAlloc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a8a2958fb6be370d3cc29972f57203952"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__axidma__v9__0.html#ga11a02100a6c84e394caa41761ab7485c">XAxiDma_Bd</a>* XAxiDma_BdRing::PreHead</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>First BD in the pre-work group. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, and <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ac14f09fcd00f1869c8194d790f73d791"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int XAxiDma_BdRing::RingIndex</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Ring Index. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#gaffa661a9a2467c1e274842c147531cea">XAxiDma_BdRingDumpRegs()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize()</a>, <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a443e5c48e677e9a1a4e85a383eefc2be"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile int XAxiDma_BdRing::RunState</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Whether channel is running. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">XAxiDma_BdRingClone()</a>, <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>, <a class="el" href="group__axidma__v9__0.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw()</a>, <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize()</a>, <a class="el" href="group__axidma__v9__0.html#gadb572b623215a7df62b1e0468e3bd68c">XAxiDma_Pause()</a>, <a class="el" href="group__axidma__v9__0.html#ga5b7d1248ef065915fd8c9e8d5e00640f">XAxiDma_Reset()</a>, <a class="el" href="group__axidma__v9__0.html#ga847cd9a0255fcb444bce58b945de8574">XAxiDma_Resume()</a>, <a class="el" href="group__axidma__v9__0.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw()</a>, and <a class="el" href="group__axidma__v9__0.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc()</a>.</p>
+
+</div>
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+<div class="memitem">
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+          <td class="memname">UINTPTR XAxiDma_BdRing::Separation</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Number of bytes between the starting address of adjacent BDs. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck()</a>, <a class="el" href="group__axidma__v9__0.html#gad044df5bd676a71226411ba7f78ef20b">XAxiDma_BdRingClone()</a>, and <a class="el" href="group__axidma__v9__0.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate()</a>.</p>
+
+</div>
+</div>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>

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+<div class="title">XAxiDma_Config Struct Reference<div class="ingroups"><a class="el" href="group__axidma__v9__0.html">Axidma_v9_0</a></div></div>  </div>
+</div><!--header-->
+<div class="contents">
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+<div class="textblock"><p>This structure passes the hardware building information to the driver </p>
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+<a class="anchor" id="a6fc1c26fb40944182ff84e370e667eb0"></a>
+<div class="memitem">
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+          <td class="memname">int XAxiDma_Config::AddrWidth</td>
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+<p>Address Width. </p>
+
+<p>Referenced by <a class="el" href="group__axidma__v9__0.html#ga8026e76c90d891d21c9c355ff776cb77">XAxiDma_CfgInitialize()</a>.</p>
+
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+<tr class="separator:gad4ea3039216916336ae1c7598ff26afc"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>

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+   <div id="projectname">axidma_v9_0
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+   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
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+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="globals.html"><span>APIs</span></a></li>
+      <li><a href="files.html"><span>File&#160;List</span></a></li>
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+<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_457bf2146d2f72d07796ff92ec9d3b09.html">axidma_v9_0</a></li><li class="navelem"><a class="el" href="dir_239ebfe70a102f9d662a37767b146b91.html">src</a></li>  </ul>
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+<div class="header">
+  <div class="summary">
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">xaxidma_bd.c File Reference</div>  </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
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+</table>
+</div><!-- contents -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
+  </ul>
+</div>
+</body>
+</html>