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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
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Steffen Vogel 2024-02-29 19:04:37 +01:00
commit 02a6f1d466
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# Project-wide dockerignore file
#
# SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0
*
!thirdparty/criterion/

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# EditorConfig is awesome: http://EditorConfig.org
# SPDX-FileCopyrightText: 2014-2023 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0
# top-most EditorConfig file
root = true
# Unix-style newlines with a newline ending every file
[*]
charset = utf-8
end_of_line = lf
insert_final_newline = true
trim_trailing_whitespace=true
# Matches multiple files with brace expansion notation
# Set default charset
[*.{c,h,proto,cpp,hpp,h.in,hpp.in}]
indent_style = space
indent_size = 2
[*.py]
indent_style = space
indent_size = 4
[*.conf]
indent_style = tab
indent_size = 8
[*.nix]
indent_style = space
indent_size = 2

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# Project-wide gitignore file
#
# SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0
build/
.vscode/
*.a
*.o
*.so
*.user
graph.dot

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# GitLab CI configuration
#
# SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0
variables:
GIT_SUBMODULE_STRATEGY: recursive
PREFIX: /usr/
DOCKER_TAG: ${CI_COMMIT_REF_NAME}
DOCKER_IMAGE_DEV: villas/fpga-dev
stages:
- prepare
- build
- test
# Stage: prepare
# Build docker image which is used to build & test VILLASnode
docker-dev:
stage: prepare
script:
- docker build -t ${DOCKER_IMAGE_DEV}:${DOCKER_TAG} .
tags:
- docker
# Stage: build
build:source:
stage: build
script:
- mkdir build && cd build && cmake3 .. && make -j8
artifacts:
expire_in: 1 week
name: ${CI_PROJECT_NAME}-${CI_BUILD_REF}
paths:
- build/
image: ${DOCKER_IMAGE_DEV}:${DOCKER_TAG}
tags:
- docker
# Stage: test
test:unit:
stage: test
tags:
- docker
allow_failure: true
image: ${DOCKER_IMAGE_DEV}:${DOCKER_TAG}
script: |
rm -r build && mkdir build && cd build
cmake ..
make -j$(nproc) unit-tests-fpga
if [ "$(who | wc -l)" -eq "0" ]; then
tests/unit/unit-tests-fpga --jobs 1 --filter 'fpga/*'
else
echo "System is currently used by: $(who)"
echo "We are skipping the test. Please restart manually."
fi
test:cppcheck:
stage: test
script:
- cppcheck -j $(nproc)
--max-configs=32
--error-exitcode=1
--quiet
--inline-suppr
--enable=warning,performance,portability,information,missingInclude
--std=c++11
--suppress=noValidConfiguration
-I include
-I common/include
gpu/
src/
lib/
tests/unit/
--suppress=unmatchedSuppression
-igpu/thirdparty | tee cppcheck.log
image: ${DOCKER_IMAGE_DEV}:${DOCKER_TAG}
dependencies:
- build:source
tags:
- docker
artifacts:
when: on_failure
paths:
- cppcheck.log
expose_as: cppcheck
test:reuse:
tags:
- docker
stage: test
image:
name: fsfe/reuse:latest
entrypoint: [""]
script:
- reuse lint

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# Git submodule list
#
# SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0
[submodule "common"]
path = common
url = https://github.com/VILLASframework/common.git
[submodule "thirdparty/libxil"]
path = thirdparty/libxil
url = https://github.com/VILLASframework/libxil.git
[submodule "thirdparty/udmabuf"]
path = thirdparty/udmabuf
url = https://github.com/ikwzm/udmabuf
[submodule "lib/gpu/gdrcopy"]
path = gpu/thirdparty/gdrcopy
url = https://github.com/daniel-k/gdrcopy.git

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Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/
Upstream-Name: VILLASfpga
Upstream-Contact: Steffen Vogel <post@steffenvogel.de>
Source: https://fein-aachen.org/en/projects/villas-fpga/
Files: .vscode/* doc/pictures/* etc/**.json
Copyright: 2018-2023, Institute for Automation of Complex Power Systems, RWTH Aachen University
License: Apache-2.0

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{
"configurations": [
{
"name": "Linux",
"includePath": [
"${workspaceFolder}/**"
],
"defines": [],
"cStandard": "c11",
"cppStandard": "c++17",
"intelliSenseMode": "clang-x64",
"configurationProvider": "vector-of-bool.cmake-tools",
"compileCommands": "${workspaceFolder}/build/compile_commands.json"
}
],
"version": 4
}

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{
// Use IntelliSense to learn about possible attributes.
// Hover to view descriptions of existing attributes.
// For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
"version": "0.2.0",
"configurations": [
{
"name": "(gdb) Launch",
"type": "cppdbg",
"request": "launch",
"program": "${workspaceFolder}/build/src/villas-fpga-ctrl",
"args": [
"-c", "${workspaceFolder}/etc/fpgas.json", "--connect", "\"2<->stdout\""
],
"stopAtEntry": false,
"cwd": "${workspaceFolder}",
"environment": [
{
"name": "LD_LIBRARY_PATH",
"value": "/usr/local/lib64/"
}
],
"externalConsole": false,
"MIMode": "gdb",
"miDebuggerPath": "${workspaceFolder}/scripts/gdb_sudo.sh",
"setupCommands": [
{
"description": "Enable pretty-printing for gdb",
"text": "-enable-pretty-printing",
"ignoreFailures": true
}
]
}
]
}

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# Changelog
<!--
SPDX-FileCopyrightText: 2023 OPAL-RT Germany GmbH
SPDX-License-Identifier: Apache-2.0
-->
All notable changes to this project will be documented in this file.
The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
## [Unreleased]
### Added
### Changed
### Fixed
## [0.1.0] - 2017-11-21
### Changed
- Switched to CMake
### Added
- Sourcecode import from VILLASnode project:
http://git.rwth-aachen.de/VILLASframework/VILLASnode

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## CMakeLists.txt
#
# Author: Daniel Krebs <github@daniel-krebs.net>
# SPDX-FileCopyrightText: 2018 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0
cmake_minimum_required(VERSION 3.5)
project(VILLASfpga
LANGUAGES C CXX
VERSION 0.1.0
)
set(CMAKE_MODULE_PATH ${CMAKE_CURRENT_LIST_DIR}/cmake)
# Several CMake settings/defaults
set(CMAKE_CXX_STANDARD 17)
set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -Wextra -Werror")
if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME)
set(TOPLEVEL_PROJECT ON)
else()
set(TOPLEVEL_PROJECT OFF)
endif()
# GPU library is optional, check for CUDA presence
include(CheckLanguage)
check_language(CUDA)
if(CMAKE_CUDA_COMPILER)
add_subdirectory(gpu)
else()
message("No CUDA support, not building GPU library")
endif()
include(FindPkgConfig)
set(ENV{PKG_CONFIG_PATH} "$ENV{PKG_CONFIG_PATH}:/usr/local/lib/pkgconfig:/usr/local/lib64/pkgconfig:/usr/local/share/pkgconfig:/usr/lib64/pkgconfig")
pkg_check_modules(JANSSON REQUIRED IMPORTED_TARGET jansson)
find_package(Threads)
find_package(Criterion)
include_directories(thirdparty/CLI11)
include_directories(thirdparty/rang)
add_subdirectory(thirdparty/libxil)
add_subdirectory(lib)
add_subdirectory(src)
if(CRITERION_FOUND AND TOPLEVEL_PROJECT)
add_subdirectory(tests/unit)
endif()
if(NOT CMAKE_PROJECT_NAME STREQUAL "villas-node")
add_subdirectory(common)
endif()
# Project settings
set(PROJECT_NAME "VILLASfpga")
set(PROJECT_DESCRIPTION "Host library for configuring and communicating with VILLASfpga")
set(PROJECT_VENDOR "Institute for Automation of Complex Power Systems, RWTH Aachen University")
set(PROJECT_URL "https://www.fein-aachen.org/projects/villas-fpga/")
set(PROJECT_VERSION_MAJOR "0")
set(PROJECT_VERSION_MINOR "1")
set(PROJECT_VERSION_PATCH "0")
set(PROJECT_RELEASE "1")
# pkg-config
configure_file("libvillas-fpga.pc.in" "libvillas-fpga.pc" @ONLY)
install(FILES "${CMAKE_CURRENT_BINARY_DIR}/libvillas-fpga.pc" DESTINATION "${CMAKE_INSTALL_PREFIX}/lib${LIB_SUFFIX}/pkgconfig")
# CPack
set(CPACK_PACKAGE_DESCRIPTION_SUMMARY ${PROJECT_DESCRIPTION})
set(CPACK_PACKAGE_VENDOR ${PROJECT_VENDOR})
set(CPACK_PACKAGE_DESCRIPTION_FILE "${CMAKE_CURRENT_SOURCE_DIR}/README.md")
set(CPACK_RESOURCE_FILE_LICENSE "${CMAKE_CURRENT_SOURCE_DIR}/LICENSES/Apache-2.0.txt")
set(CPACK_RESOURCE_FILE_README "${CMAKE_CURRENT_SOURCE_DIR}/README.md")
set(CPACK_PACKAGE_NAME "villas-fpga")
set(CPACK_PACKAGE_VERSION_MAJOR ${PROJECT_VERSION_MAJOR})
set(CPACK_PACKAGE_VERSION_MINOR ${PROJECT_VERSION_MINOR})
set(CPACK_PACKAGE_VERSION_PATCH ${PROJECT_VERSION_PATCH})
set(CPACK_PACKAGE_VERSION "${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}.${PROJECT_VERSION_PATCH}")
set(CPACK_SOURCE_GENERATOR "TGZ")
set(CPACK_SOURCE_PACKAGE_FILE_NAME "${CPACK_PACKAGE_NAME}-${CPACK_PACKAGE_VERSION}")
set(CPACK_SOURCE_IGNORE_FILES "/build/;/.git/;~$;${CPACK_SOURCE_IGNORE_FILES}")
set(CPACK_RPM_PACKAGE_RELEASE ${PROJECT_RELEASE})
set(CPACK_RPM_PACKAGE_ARCHITECTURE "x86_64")
set(CPACK_RPM_PACKAGE_LICENSE "Apache-2.0")
set(CPACK_RPM_PACKAGE_URL ${PROJECT_URL})
set(CPACK_RPM_PACKAGE_REQUIRES "libxil")
set(CPACK_RPM_PACKAGE_GROUP "Development/Libraries")
# As close as possible to Fedoras naming
set(CPACK_PACKAGE_FILE_NAME "${CPACK_SOURCE_PACKAGE_FILE_NAME}-${CPACK_RPM_PACKAGE_RELEASE}.${CPACK_RPM_PACKAGE_ARCHITECTURE}")
set(CPACK_GENERATOR "RPM")
include(CPack)

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# Dockerfile for VILLASfpga development.
#
# This Dockerfile builds an image which contains all library dependencies
# and tools to build VILLASfpga.
# However, VILLASfpga itself it not part of the image.
#
# This image can be used for developing VILLASfpga
# by running:
# make docker
#
# Author: Steffen Vogel <post@steffenvogel.de>
# SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0
FROM rockylinux:9
LABEL \
org.label-schema.schema-version="1.0" \
org.label-schema.name="VILLASfpga" \
org.label-schema.license="Apache-2.0" \
org.label-schema.vendor="Institute for Automation of Complex Power Systems, RWTH Aachen University" \
org.label-schema.author.name="Steffen Vogel" \
org.label-schema.author.email="post@steffenvogel.de" \
org.label-schema.description="A image containing all build-time dependencies for VILLASfpga based on Fedora" \
org.label-schema.url="http://fein-aachen.org/projects/villas-framework/" \
org.label-schema.vcs-url="https://git.rwth-aachen.de/VILLASframework/VILLASfpga" \
org.label-schema.usage="https://villas.fein-aachen.org/doc/fpga.html"
# Enable Extra Packages for Enterprise Linux (EPEL) and Software collection repo
RUN dnf -y update && \
dnf install -y epel-release dnf-plugins-core && \
dnf install -y https://rpms.remirepo.net/enterprise/remi-release-9.rpm && \
dnf config-manager --set-enabled crb && \
dnf config-manager --set-enabled remi
# Toolchain
RUN dnf -y install \
git clang gdb ccache \
redhat-rpm-config \
rpmdevtools rpm-build\
make cmake ninja-build \
wget \
pkgconfig \
autoconf automake libtool \
cppcheck \
git curl tar
# Dependencies
RUN dnf -y install \
jansson-devel \
openssl-devel \
curl-devel \
lapack-devel \
libuuid-devel
# Build & Install Fmtlib
RUN git clone --recursive https://github.com/fmtlib/fmt.git /tmp/fmt && \
mkdir -p /tmp/fmt/build && cd /tmp/fmt/build && \
git checkout 6.1.2 && \
cmake3 -DBUILD_SHARED_LIBS=1 -DFMT_TEST=OFF .. && \
make -j$(nproc) install && \
rm -rf /tmp/fmt
# Build & Install spdlog
RUN git clone --recursive https://github.com/gabime/spdlog.git /tmp/spdlog && \
mkdir -p /tmp/spdlog/build && cd /tmp/spdlog/build && \
git checkout v1.8.2 && \
cmake -DSPDLOG_FMT_EXTERNAL=ON \
-DSPDLOG_BUILD_BENCH=OFF \
-DSPDLOG_BUILD_SHARED=ON \
-DSPDLOG_BUILD_TESTS=OFF .. && \
make -j$(nproc) install && \
rm -rf /tmp/spdlog
# Build & Install Criterion
RUN git clone --recursive https://github.com/Snaipe/Criterion /tmp/criterion && \
mkdir -p /tmp/criterion/build && cd /tmp/criterion/build && \
git checkout v2.3.3 && \
cmake .. && \
make -j$(nproc) install && \
rm -rf /tmp/*
# Build & Install libxil
RUN git clone https://git.rwth-aachen.de/acs/public/villas/fpga/libxil.git /tmp/libxil && \
mkdir -p /tmp/libxil/build && cd /tmp/libxil/build && \
cmake .. && \
make -j$(nproc) install && \
rm -rf /tmp/*
ENV LD_LIBRARY_PATH /usr/local/lib:/usr/local/lib64
WORKDIR /fpga

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Apache License
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http://www.apache.org/licenses/
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
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Copyright (c) 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed.
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To protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it.
For example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights.
We protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software.
Also, for each author's protection and ours, we want to make certain that everyone understands that there is no warranty for this free software. If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors' reputations.
Finally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone's free use or not licensed at all.
The precise terms and conditions for copying, distribution and modification follow.
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
0. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The "Program", below, refers to any such program or work, and a "work based on the Program" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term "modification".) Each licensee is addressed as "you".
Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does.
1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program.
You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee.
2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions:
a) You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change.
b) You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License.
c) If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.)
These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it.
Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program.
In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License.
3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following:
a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or,
b) Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or,
c) Accompany it with the information you received as to the offer to distribute corresponding source code. (This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer, in accord with Subsection b above.)
The source code for a work means the preferred form of the work for making modifications to it. For an executable work, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the executable. However, as a special exception, the source code distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable.
If distribution of executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code.
4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance.
5. You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Program or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it.
6. Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License.
7. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Program at all. For example, if a patent license would not permit royalty-free redistribution of the Program by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program.
If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances.
It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system, which is implemented by public license practices. Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice.
This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License.
8. If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License.
9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns.
Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation.
10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally.
NO WARRANTY
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found.
one line to give the program's name and an idea of what it does. Copyright (C) yyyy name of author
This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this when it starts in an interactive mode:
Gnomovision version 69, Copyright (C) year name of author Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than `show w' and `show c'; they could even be mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the program, if necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision' (which makes passes at compilers) written by James Hacker.
signature of Ty Coon, 1 April 1989 Ty Coon, President of Vice

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GNU GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
Copyright © 2007 Free Software Foundation, Inc. <https://fsf.org/>
Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed.
Preamble
The GNU General Public License is a free, copyleft license for software and other kinds of works.
The licenses for most software and other practical works are designed to take away your freedom to share and change the works. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change all versions of a program--to make sure it remains free software for all its users. We, the Free Software Foundation, use the GNU General Public License for most of our software; it applies also to any other work released this way by its authors. You can apply it to your programs, too.
When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for them if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs, and that you know you can do these things.
To protect your rights, we need to prevent others from denying you these rights or asking you to surrender the rights. Therefore, you have certain responsibilities if you distribute copies of the software, or if you modify it: responsibilities to respect the freedom of others.
For example, if you distribute copies of such a program, whether gratis or for a fee, you must pass on to the recipients the same freedoms that you received. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights.
Developers that use the GNU GPL protect your rights with two steps: (1) assert copyright on the software, and (2) offer you this License giving you legal permission to copy, distribute and/or modify it.
For the developers' and authors' protection, the GPL clearly explains that there is no warranty for this free software. For both users' and authors' sake, the GPL requires that modified versions be marked as changed, so that their problems will not be attributed erroneously to authors of previous versions.
Some devices are designed to deny users access to install or run modified versions of the software inside them, although the manufacturer can do so. This is fundamentally incompatible with the aim of protecting users' freedom to change the software. The systematic pattern of such abuse occurs in the area of products for individuals to use, which is precisely where it is most unacceptable. Therefore, we have designed this version of the GPL to prohibit the practice for those products. If such problems arise substantially in other domains, we stand ready to extend this provision to those domains in future versions of the GPL, as needed to protect the freedom of users.
Finally, every program is threatened constantly by software patents. States should not allow patents to restrict development and use of software on general-purpose computers, but in those that do, we wish to avoid the special danger that patents applied to a free program could make it effectively proprietary. To prevent this, the GPL assures that patents cannot be used to render the program non-free.
The precise terms and conditions for copying, distribution and modification follow.
TERMS AND CONDITIONS
0. Definitions.
“This License” refers to version 3 of the GNU General Public License.
“Copyright” also means copyright-like laws that apply to other kinds of works, such as semiconductor masks.
“The Program” refers to any copyrightable work licensed under this License. Each licensee is addressed as “you”. “Licensees” and “recipients” may be individuals or organizations.
To “modify” a work means to copy from or adapt all or part of the work in a fashion requiring copyright permission, other than the making of an exact copy. The resulting work is called a “modified version” of the earlier work or a work “based on” the earlier work.
A “covered work” means either the unmodified Program or a work based on the Program.
To “propagate” a work means to do anything with it that, without permission, would make you directly or secondarily liable for infringement under applicable copyright law, except executing it on a computer or modifying a private copy. Propagation includes copying, distribution (with or without modification), making available to the public, and in some countries other activities as well.
To “convey” a work means any kind of propagation that enables other parties to make or receive copies. Mere interaction with a user through a computer network, with no transfer of a copy, is not conveying.
An interactive user interface displays “Appropriate Legal Notices” to the extent that it includes a convenient and prominently visible feature that (1) displays an appropriate copyright notice, and (2) tells the user that there is no warranty for the work (except to the extent that warranties are provided), that licensees may convey the work under this License, and how to view a copy of this License. If the interface presents a list of user commands or options, such as a menu, a prominent item in the list meets this criterion.
1. Source Code.
The “source code” for a work means the preferred form of the work for making modifications to it. “Object code” means any non-source form of a work.
A “Standard Interface” means an interface that either is an official standard defined by a recognized standards body, or, in the case of interfaces specified for a particular programming language, one that is widely used among developers working in that language.
The “System Libraries” of an executable work include anything, other than the work as a whole, that (a) is included in the normal form of packaging a Major Component, but which is not part of that Major Component, and (b) serves only to enable use of the work with that Major Component, or to implement a Standard Interface for which an implementation is available to the public in source code form. A “Major Component”, in this context, means a major essential component (kernel, window system, and so on) of the specific operating system (if any) on which the executable work runs, or a compiler used to produce the work, or an object code interpreter used to run it.
The “Corresponding Source” for a work in object code form means all the source code needed to generate, install, and (for an executable work) run the object code and to modify the work, including scripts to control those activities. However, it does not include the work's System Libraries, or general-purpose tools or generally available free programs which are used unmodified in performing those activities but which are not part of the work. For example, Corresponding Source includes interface definition files associated with source files for the work, and the source code for shared libraries and dynamically linked subprograms that the work is specifically designed to require, such as by intimate data communication or control flow between those subprograms and other parts of the work.
The Corresponding Source need not include anything that users can regenerate automatically from other parts of the Corresponding Source.
The Corresponding Source for a work in source code form is that same work.
2. Basic Permissions.
All rights granted under this License are granted for the term of copyright on the Program, and are irrevocable provided the stated conditions are met. This License explicitly affirms your unlimited permission to run the unmodified Program. The output from running a covered work is covered by this License only if the output, given its content, constitutes a covered work. This License acknowledges your rights of fair use or other equivalent, as provided by copyright law.
You may make, run and propagate covered works that you do not convey, without conditions so long as your license otherwise remains in force. You may convey covered works to others for the sole purpose of having them make modifications exclusively for you, or provide you with facilities for running those works, provided that you comply with the terms of this License in conveying all material for which you do not control copyright. Those thus making or running the covered works for you must do so exclusively on your behalf, under your direction and control, on terms that prohibit them from making any copies of your copyrighted material outside their relationship with you.
Conveying under any other circumstances is permitted solely under the conditions stated below. Sublicensing is not allowed; section 10 makes it unnecessary.
3. Protecting Users' Legal Rights From Anti-Circumvention Law.
No covered work shall be deemed part of an effective technological measure under any applicable law fulfilling obligations under article 11 of the WIPO copyright treaty adopted on 20 December 1996, or similar laws prohibiting or restricting circumvention of such measures.
When you convey a covered work, you waive any legal power to forbid circumvention of technological measures to the extent such circumvention is effected by exercising rights under this License with respect to the covered work, and you disclaim any intention to limit operation or modification of the work as a means of enforcing, against the work's users, your or third parties' legal rights to forbid circumvention of technological measures.
4. Conveying Verbatim Copies.
You may convey verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice; keep intact all notices stating that this License and any non-permissive terms added in accord with section 7 apply to the code; keep intact all notices of the absence of any warranty; and give all recipients a copy of this License along with the Program.
You may charge any price or no price for each copy that you convey, and you may offer support or warranty protection for a fee.
5. Conveying Modified Source Versions.
You may convey a work based on the Program, or the modifications to produce it from the Program, in the form of source code under the terms of section 4, provided that you also meet all of these conditions:
a) The work must carry prominent notices stating that you modified it, and giving a relevant date.
b) The work must carry prominent notices stating that it is released under this License and any conditions added under section 7. This requirement modifies the requirement in section 4 to “keep intact all notices”.
c) You must license the entire work, as a whole, under this License to anyone who comes into possession of a copy. This License will therefore apply, along with any applicable section 7 additional terms, to the whole of the work, and all its parts, regardless of how they are packaged. This License gives no permission to license the work in any other way, but it does not invalidate such permission if you have separately received it.
d) If the work has interactive user interfaces, each must display Appropriate Legal Notices; however, if the Program has interactive interfaces that do not display Appropriate Legal Notices, your work need not make them do so.
A compilation of a covered work with other separate and independent works, which are not by their nature extensions of the covered work, and which are not combined with it such as to form a larger program, in or on a volume of a storage or distribution medium, is called an “aggregate” if the compilation and its resulting copyright are not used to limit the access or legal rights of the compilation's users beyond what the individual works permit. Inclusion of a covered work in an aggregate does not cause this License to apply to the other parts of the aggregate.
6. Conveying Non-Source Forms.
You may convey a covered work in object code form under the terms of sections 4 and 5, provided that you also convey the machine-readable Corresponding Source under the terms of this License, in one of these ways:
a) Convey the object code in, or embodied in, a physical product (including a physical distribution medium), accompanied by the Corresponding Source fixed on a durable physical medium customarily used for software interchange.
b) Convey the object code in, or embodied in, a physical product (including a physical distribution medium), accompanied by a written offer, valid for at least three years and valid for as long as you offer spare parts or customer support for that product model, to give anyone who possesses the object code either (1) a copy of the Corresponding Source for all the software in the product that is covered by this License, on a durable physical medium customarily used for software interchange, for a price no more than your reasonable cost of physically performing this conveying of source, or (2) access to copy the Corresponding Source from a network server at no charge.
c) Convey individual copies of the object code with a copy of the written offer to provide the Corresponding Source. This alternative is allowed only occasionally and noncommercially, and only if you received the object code with such an offer, in accord with subsection 6b.
d) Convey the object code by offering access from a designated place (gratis or for a charge), and offer equivalent access to the Corresponding Source in the same way through the same place at no further charge. You need not require recipients to copy the Corresponding Source along with the object code. If the place to copy the object code is a network server, the Corresponding Source may be on a different server (operated by you or a third party) that supports equivalent copying facilities, provided you maintain clear directions next to the object code saying where to find the Corresponding Source. Regardless of what server hosts the Corresponding Source, you remain obligated to ensure that it is available for as long as needed to satisfy these requirements.
e) Convey the object code using peer-to-peer transmission, provided you inform other peers where the object code and Corresponding Source of the work are being offered to the general public at no charge under subsection 6d.
A separable portion of the object code, whose source code is excluded from the Corresponding Source as a System Library, need not be included in conveying the object code work.
A “User Product” is either (1) a “consumer product”, which means any tangible personal property which is normally used for personal, family, or household purposes, or (2) anything designed or sold for incorporation into a dwelling. In determining whether a product is a consumer product, doubtful cases shall be resolved in favor of coverage. For a particular product received by a particular user, “normally used” refers to a typical or common use of that class of product, regardless of the status of the particular user or of the way in which the particular user actually uses, or expects or is expected to use, the product. A product is a consumer product regardless of whether the product has substantial commercial, industrial or non-consumer uses, unless such uses represent the only significant mode of use of the product.
“Installation Information” for a User Product means any methods, procedures, authorization keys, or other information required to install and execute modified versions of a covered work in that User Product from a modified version of its Corresponding Source. The information must suffice to ensure that the continued functioning of the modified object code is in no case prevented or interfered with solely because modification has been made.
If you convey an object code work under this section in, or with, or specifically for use in, a User Product, and the conveying occurs as part of a transaction in which the right of possession and use of the User Product is transferred to the recipient in perpetuity or for a fixed term (regardless of how the transaction is characterized), the Corresponding Source conveyed under this section must be accompanied by the Installation Information. But this requirement does not apply if neither you nor any third party retains the ability to install modified object code on the User Product (for example, the work has been installed in ROM).
The requirement to provide Installation Information does not include a requirement to continue to provide support service, warranty, or updates for a work that has been modified or installed by the recipient, or for the User Product in which it has been modified or installed. Access to a network may be denied when the modification itself materially and adversely affects the operation of the network or violates the rules and protocols for communication across the network.
Corresponding Source conveyed, and Installation Information provided, in accord with this section must be in a format that is publicly documented (and with an implementation available to the public in source code form), and must require no special password or key for unpacking, reading or copying.
7. Additional Terms.
“Additional permissions” are terms that supplement the terms of this License by making exceptions from one or more of its conditions. Additional permissions that are applicable to the entire Program shall be treated as though they were included in this License, to the extent that they are valid under applicable law. If additional permissions apply only to part of the Program, that part may be used separately under those permissions, but the entire Program remains governed by this License without regard to the additional permissions.
When you convey a copy of a covered work, you may at your option remove any additional permissions from that copy, or from any part of it. (Additional permissions may be written to require their own removal in certain cases when you modify the work.) You may place additional permissions on material, added by you to a covered work, for which you have or can give appropriate copyright permission.
Notwithstanding any other provision of this License, for material you add to a covered work, you may (if authorized by the copyright holders of that material) supplement the terms of this License with terms:
a) Disclaiming warranty or limiting liability differently from the terms of sections 15 and 16 of this License; or
b) Requiring preservation of specified reasonable legal notices or author attributions in that material or in the Appropriate Legal Notices displayed by works containing it; or
c) Prohibiting misrepresentation of the origin of that material, or requiring that modified versions of such material be marked in reasonable ways as different from the original version; or
d) Limiting the use for publicity purposes of names of licensors or authors of the material; or
e) Declining to grant rights under trademark law for use of some trade names, trademarks, or service marks; or
f) Requiring indemnification of licensors and authors of that material by anyone who conveys the material (or modified versions of it) with contractual assumptions of liability to the recipient, for any liability that these contractual assumptions directly impose on those licensors and authors.
All other non-permissive additional terms are considered “further restrictions” within the meaning of section 10. If the Program as you received it, or any part of it, contains a notice stating that it is governed by this License along with a term that is a further restriction, you may remove that term. If a license document contains a further restriction but permits relicensing or conveying under this License, you may add to a covered work material governed by the terms of that license document, provided that the further restriction does not survive such relicensing or conveying.
If you add terms to a covered work in accord with this section, you must place, in the relevant source files, a statement of the additional terms that apply to those files, or a notice indicating where to find the applicable terms.
Additional terms, permissive or non-permissive, may be stated in the form of a separately written license, or stated as exceptions; the above requirements apply either way.
8. Termination.
You may not propagate or modify a covered work except as expressly provided under this License. Any attempt otherwise to propagate or modify it is void, and will automatically terminate your rights under this License (including any patent licenses granted under the third paragraph of section 11).
However, if you cease all violation of this License, then your license from a particular copyright holder is reinstated (a) provisionally, unless and until the copyright holder explicitly and finally terminates your license, and (b) permanently, if the copyright holder fails to notify you of the violation by some reasonable means prior to 60 days after the cessation.
Moreover, your license from a particular copyright holder is reinstated permanently if the copyright holder notifies you of the violation by some reasonable means, this is the first time you have received notice of violation of this License (for any work) from that copyright holder, and you cure the violation prior to 30 days after your receipt of the notice.
Termination of your rights under this section does not terminate the licenses of parties who have received copies or rights from you under this License. If your rights have been terminated and not permanently reinstated, you do not qualify to receive new licenses for the same material under section 10.
9. Acceptance Not Required for Having Copies.
You are not required to accept this License in order to receive or run a copy of the Program. Ancillary propagation of a covered work occurring solely as a consequence of using peer-to-peer transmission to receive a copy likewise does not require acceptance. However, nothing other than this License grants you permission to propagate or modify any covered work. These actions infringe copyright if you do not accept this License. Therefore, by modifying or propagating a covered work, you indicate your acceptance of this License to do so.
10. Automatic Licensing of Downstream Recipients.
Each time you convey a covered work, the recipient automatically receives a license from the original licensors, to run, modify and propagate that work, subject to this License. You are not responsible for enforcing compliance by third parties with this License.
An “entity transaction” is a transaction transferring control of an organization, or substantially all assets of one, or subdividing an organization, or merging organizations. If propagation of a covered work results from an entity transaction, each party to that transaction who receives a copy of the work also receives whatever licenses to the work the party's predecessor in interest had or could give under the previous paragraph, plus a right to possession of the Corresponding Source of the work from the predecessor in interest, if the predecessor has it or can get it with reasonable efforts.
You may not impose any further restrictions on the exercise of the rights granted or affirmed under this License. For example, you may not impose a license fee, royalty, or other charge for exercise of rights granted under this License, and you may not initiate litigation (including a cross-claim or counterclaim in a lawsuit) alleging that any patent claim is infringed by making, using, selling, offering for sale, or importing the Program or any portion of it.
11. Patents.
A “contributor” is a copyright holder who authorizes use under this License of the Program or a work on which the Program is based. The work thus licensed is called the contributor's “contributor version”.
A contributor's “essential patent claims” are all patent claims owned or controlled by the contributor, whether already acquired or hereafter acquired, that would be infringed by some manner, permitted by this License, of making, using, or selling its contributor version, but do not include claims that would be infringed only as a consequence of further modification of the contributor version. For purposes of this definition, “control” includes the right to grant patent sublicenses in a manner consistent with the requirements of this License.
Each contributor grants you a non-exclusive, worldwide, royalty-free patent license under the contributor's essential patent claims, to make, use, sell, offer for sale, import and otherwise run, modify and propagate the contents of its contributor version.
In the following three paragraphs, a “patent license” is any express agreement or commitment, however denominated, not to enforce a patent (such as an express permission to practice a patent or covenant not to sue for patent infringement). To “grant” such a patent license to a party means to make such an agreement or commitment not to enforce a patent against the party.
If you convey a covered work, knowingly relying on a patent license, and the Corresponding Source of the work is not available for anyone to copy, free of charge and under the terms of this License, through a publicly available network server or other readily accessible means, then you must either (1) cause the Corresponding Source to be so available, or (2) arrange to deprive yourself of the benefit of the patent license for this particular work, or (3) arrange, in a manner consistent with the requirements of this License, to extend the patent license to downstream recipients. “Knowingly relying” means you have actual knowledge that, but for the patent license, your conveying the covered work in a country, or your recipient's use of the covered work in a country, would infringe one or more identifiable patents in that country that you have reason to believe are valid.
If, pursuant to or in connection with a single transaction or arrangement, you convey, or propagate by procuring conveyance of, a covered work, and grant a patent license to some of the parties receiving the covered work authorizing them to use, propagate, modify or convey a specific copy of the covered work, then the patent license you grant is automatically extended to all recipients of the covered work and works based on it.
A patent license is “discriminatory” if it does not include within the scope of its coverage, prohibits the exercise of, or is conditioned on the non-exercise of one or more of the rights that are specifically granted under this License. You may not convey a covered work if you are a party to an arrangement with a third party that is in the business of distributing software, under which you make payment to the third party based on the extent of your activity of conveying the work, and under which the third party grants, to any of the parties who would receive the covered work from you, a discriminatory patent license (a) in connection with copies of the covered work conveyed by you (or copies made from those copies), or (b) primarily for and in connection with specific products or compilations that contain the covered work, unless you entered into that arrangement, or that patent license was granted, prior to 28 March 2007.
Nothing in this License shall be construed as excluding or limiting any implied license or other defenses to infringement that may otherwise be available to you under applicable patent law.
12. No Surrender of Others' Freedom.
If conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot convey a covered work so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not convey it at all. For example, if you agree to terms that obligate you to collect a royalty for further conveying from those to whom you convey the Program, the only way you could satisfy both those terms and this License would be to refrain entirely from conveying the Program.
13. Use with the GNU Affero General Public License.
Notwithstanding any other provision of this License, you have permission to link or combine any covered work with a work licensed under version 3 of the GNU Affero General Public License into a single combined work, and to convey the resulting work. The terms of this License will continue to apply to the part which is the covered work, but the special requirements of the GNU Affero General Public License, section 13, concerning interaction through a network will apply to the combination as such.
14. Revised Versions of this License.
The Free Software Foundation may publish revised and/or new versions of the GNU General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns.
Each version is given a distinguishing version number. If the Program specifies that a certain numbered version of the GNU General Public License “or any later version” applies to it, you have the option of following the terms and conditions either of that numbered version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of the GNU General Public License, you may choose any version ever published by the Free Software Foundation.
If the Program specifies that a proxy can decide which future versions of the GNU General Public License can be used, that proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Program.
Later license versions may give you additional or different permissions. However, no additional obligations are imposed on any author or copyright holder as a result of your choosing to follow a later version.
15. Disclaimer of Warranty.
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
17. Interpretation of Sections 15 and 16.
If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, reviewing courts shall apply local law that most closely approximates an absolute waiver of all civil liability in connection with the Program, unless a warranty or assumption of liability accompanies a copy of the Program in return for a fee.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively state the exclusion of warranty; and each file should have at least the “copyright” line and a pointer to where the full notice is found.
<one line to give the program's name and a brief idea of what it does.>
Copyright (C) <year> <name of author>
This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program. If not, see <https://www.gnu.org/licenses/>.
Also add information on how to contact you by electronic and paper mail.
If the program does terminal interaction, make it output a short notice like this when it starts in an interactive mode:
<program> Copyright (C) <year> <name of author>
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, your program's commands might be different; for a GUI interface, you would use an “about box”.
You should also get your employer (if you work as a programmer) or school, if any, to sign a “copyright disclaimer” for the program, if necessary. For more information on this, and how to apply and follow the GNU GPL, see <https://www.gnu.org/licenses/>.
The GNU General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. But first, please read <https://www.gnu.org/philosophy/why-not-lgpl.html>.

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This is free and unencumbered software released into the public domain.
Anyone is free to copy, modify, publish, use, compile, sell, or distribute this software, either in source code form or as a compiled binary, for any purpose, commercial or non-commercial, and by any means.
In jurisdictions that recognize copyright laws, the author or authors of this software dedicate any and all copyright interest in the software to the public domain. We make this dedication for the benefit of the public at large and to the detriment of our heirs and
successors. We intend this dedication to be an overt act of relinquishment in perpetuity of all present and future rights to this software under copyright law.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
For more information, please refer to <http://unlicense.org/>

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DO WHAT THE FUCK YOU WANT TO PUBLIC LICENSE
Version 2, December 2004
Copyright (C) 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
Everyone is permitted to copy and distribute verbatim or modified copies of this license document, and changing it is allowed as long as the name is changed.
DO WHAT THE FUCK YOU WANT TO PUBLIC LICENSE
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
0. You just DO WHAT THE FUCK YOU WANT TO.

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# <img src="doc/pictures/villas_fpga.png" width=40 /> VILLASfpga
[![build status](https://git.rwth-aachen.de/acs/public/villas/fpga/fpga/badges/master/pipeline.svg)](https://git.rwth-aachen.de/acs/public/villas/fpga/fpga/-/pipelines/)
VILLASfpga provides a flexbible, real-time capable interconnect between FPGAs and Linux, e.g., to connect simulators and devices for hardware-in-the loop simulations. VILLASfpga can guarantee fixed latencies in the nanosecond range.
VILLASfpga supports Xilinx FPGAs connected to a Linux system via PCI-Express or via a platform bus as found on MPSoC devices.
## Documentation
User documentation is available here: <https://villas.fein-aachen.org/doc/fpga.html>
## License
This project is released under the terms of the [Apache 2.0](LICENSE) license:
- SPDX-FileCopyrightText: 2022-2023 Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
- SPDX-FileCopyrightText: 2018-2023 Steffen Vogel <post@steffenvogel.de>
- SPDX-FileCopyrightText: 2018 Daniel Krebs <dkrebs@eonerc.rwth-aachen.de>
- SPDX-License-Identifier: Apache-2.0
We kindly ask all academic publications employing components of VILLASframework to cite one of the following papers:
- A. Monti et al., "[A Global Real-Time Superlab: Enabling High Penetration of Power Electronics in the Electric Grid](https://ieeexplore.ieee.org/document/8458285/)," in IEEE Power Electronics Magazine, vol. 5, no. 3, pp. 35-44, Sept. 2018.
- S. Vogel, M. Mirz, L. Razik and A. Monti, "[An open solution for next-generation real-time power system simulation](http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8245739&isnumber=8244404)," 2017 IEEE Conference on Energy Internet and Energy System Integration (EI2), Beijing, 2017, pp. 1-6.
## Related Projects
- [MIOB](https://github.com/RWTH-ACS/miob)
- [DINO](https://github.com/RWTH-ACS/dino)
## Contact
- Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
- Steffen Vogel <post@steffenvogel.de>
- Daniel Krebs <dkrebs@eonerc.rwth-aachen.de>
[Institute for Automation of Complex Power Systems (ACS)](http://www.acs.eonerc.rwth-aachen.de)
[RWTH University Aachen, Germany](http://www.rwth-aachen.de)

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# Try to find Criterion
#
# Once done this will define
# CRITERION_FOUND - System has Criterion
# CRITERION_INCLUDE_DIRS - The Criterion include directories
# CRITERION_LIBRARIES - The libraries needed to use Criterion
#
# SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: WTFPL
find_package(PkgConfig)
find_path(CRITERION_INCLUDE_DIR criterion/criterion.h
PATH_SUFFIXES criterion)
find_library(CRITERION_LIBRARY NAMES criterion libcriterion)
set(CRITERION_LIBRARIES ${CRITERION_LIBRARY})
set(CRITERION_INCLUDE_DIRS ${CRITERION_INCLUDE_DIR})
include(FindPackageHandleStandardArgs)
# Handle the QUIET and REQUIRED arguments and set CRITERION_FOUND to TRUE
# if all listed variables are TRUE
find_package_handle_standard_args(Criterion DEFAULT_MSG
CRITERION_LIBRARY CRITERION_INCLUDE_DIR)
mark_as_advanced(CRITERION_INCLUDE_DIR CRITERION_LIBRARY)

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{
"fpgas": {
"vc707": {
"id": "10ee:7021",
"slot": "0000:88:00.0",
"do_reset": true,
"ips": "vc707-xbar-pcie-dino/vc707-xbar-pcie-dino-v2.json",
"polling": true,
"interface": "pcie"
}
}
}

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## CMakeLists.txt
#
# Author: Daniel Krebs <github@daniel-krebs.net>
# SPDX-FileCopyrightText: 2018 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0
cmake_minimum_required(VERSION 3.8)
project(villas-gpu
VERSION 1.0
DESCRIPTION "VILLASgpu"
LANGUAGES C CXX CUDA)
add_subdirectory(thirdparty/gdrcopy)
add_library(villas-gpu
SHARED
src/gpu.cpp
src/kernels.cu
)
target_compile_options(villas-gpu PRIVATE -g)
set_source_files_properties(src/gpu.cpp PROPERTIES
LANGUAGE CUDA
)
target_include_directories(villas-gpu
PRIVATE
/opt/cuda/include
)
target_link_libraries(villas-gpu
PUBLIC
villas-common
gdrapi
cuda
)
target_include_directories(villas-gpu
PUBLIC
${CMAKE_CURRENT_LIST_DIR}/include
PRIVATE
${CMAKE_CURRENT_LIST_DIR}
)

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/* GPU managment.
*
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <sstream>
#include <villas/plugin.hpp>
#include <villas/memory_manager.hpp>
#include <villas/memory.hpp>
#include <villas/log.hpp>
namespace villas {
namespace gpu {
class GpuAllocator;
class Gpu {
friend GpuAllocator;
public:
Gpu(int gpuId);
~Gpu();
bool init();
std::string getName() const;
GpuAllocator &getAllocator() const
{ return *allocator; }
bool makeAccessibleToPCIeAndVA(const MemoryBlock &mem);
// Make some memory block accssible for this GPU
bool makeAccessibleFromPCIeOrHostRam(const MemoryBlock &mem);
void memcpySync(const MemoryBlock &src, const MemoryBlock &dst, size_t size);
void memcpyKernel(const MemoryBlock &src, const MemoryBlock &dst, size_t size);
MemoryTranslation
translate(const MemoryBlock &dst);
private:
bool registerIoMemory(const MemoryBlock &mem);
bool registerHostMemory(const MemoryBlock &mem);
private:
class impl;
std::unique_ptr<impl> pImpl;
// Master, will be used to derived slave addr spaces for allocation
MemoryManager::AddressSpaceId masterPciEAddrSpaceId;
MemoryManager::AddressSpaceId slaveMemoryAddrSpaceId;
Logger logger;
int gpuId;
std::unique_ptr<GpuAllocator> allocator;
};
class GpuAllocator : public BaseAllocator<GpuAllocator> {
public:
static constexpr size_t GpuPageSize = 64UL << 10;
GpuAllocator(Gpu &gpu);
std::string getName() const;
std::unique_ptr<MemoryBlock, MemoryBlock::deallocator_fn>
allocateBlock(size_t size);
private:
Gpu &gpu;
// TODO: replace by multimap (key is available memory)
std::list<std::unique_ptr<LinearAllocator>> chunks;
};
class GpuFactory : public Plugin {
public:
GpuFactory();
std::list<std::unique_ptr<Gpu>>
make();
void run(void*);
private:
Logger logger;
};
} // namespace villas
} // namespace gpu

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/* GPU Kernels.
*
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <cstdint>
#include <cuda_runtime.h>
namespace villas {
namespace gpu {
__global__ void
kernel_mailbox(volatile uint32_t *mailbox, volatile uint32_t* counter);
__global__ void
kernel_memcpy(volatile uint8_t* dst, volatile uint8_t* src, size_t length);
} // namespace villas
} // namespace gpu

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/* GPU managment.
*
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#include <cstdio>
#include <cstdint>
#include <sys/mman.h>
#include <memory>
#include <algorithm>
#include <villas/gpu.hpp>
#include <villas/log.hpp>
#include <villas/kernel/pci.hpp>
#include <villas/memory_manager.hpp>
#include <cuda.h>
#include <cuda_runtime.h>
#include <gdrapi.h>
#include "kernels.hpp"
using namespace villas::gpu;
static GpuFactory gpuFactory;
GpuAllocator::GpuAllocator(Gpu &gpu) :
BaseAllocator(gpu.masterPciEAddrSpaceId),
gpu(gpu)
{
free = [&](MemoryBlock* mem) {
cudaSetDevice(gpu.gpuId);
if (cudaFree(reinterpret_cast<void*>(mem->getOffset())) != cudaSuccess) {
logger->warn("cudaFree() failed for {:#x} of size {:#x}",
mem->getOffset(), mem->getSize());
}
removeMemoryBlock(*mem);
};
}
std::string
villas::gpu::GpuAllocator::getName() const
{
std::stringstream name;
name << "GpuAlloc" << getAddrSpaceId();
return name.str();
}
GpuFactory::GpuFactory() :
Plugin("cuda", "CUDA capable GPUs")
{
logger = villas::logging.get("gpu:factory");
}
// Required to be defined here for PIMPL to compile
Gpu::~Gpu()
{
auto &mm = MemoryManager::get();
mm.removeAddressSpace(masterPciEAddrSpaceId);
}
// We use PIMPL in order to hide gdrcopy types from the public header
class Gpu::impl {
public:
gdr_t gdr;
struct pci_device pdev;
};
std::string Gpu::getName() const
{
cudaDeviceProp deviceProp;
if (cudaGetDeviceProperties(&deviceProp, gpuId) != cudaSuccess) {
// Logger not yet availabe
villas::logging.get("gpu")->error("Cannot retrieve properties for GPU {}", gpuId);
throw std::exception();
}
std::stringstream name;
name << "gpu" << gpuId << "(" << deviceProp.name << ")";
return name.str();
}
bool Gpu::registerIoMemory(const MemoryBlock &mem)
{
auto &mm = MemoryManager::get();
const auto pciAddrSpaceId = mm.getPciAddressSpace();
// Check if we need to map anything at all, maybe it's already reachable
try {
// TODO: there might already be a path through the graph, but there's no
// overlapping window, so this will fail badly!
auto translation = mm.getTranslation(masterPciEAddrSpaceId,
mem.getAddrSpaceId());
if (translation.getSize() >= mem.getSize())
// There is already a sufficient path
logger->debug("Already mapped through another mapping");
return true;
else
logger->warn("There's already a mapping, but too small");
} catch (const std::out_of_range&) {
// Not yet reachable, that's okay, proceed
}
// In order to register IO memory with CUDA, it has to be mapped to the VA
// space of the current process (requirement of CUDA API). Check this now.
MemoryManager::AddressSpaceId mappedBaseAddrSpaceId;
try {
auto path = mm.findPath(mm.getProcessAddressSpace(), mem.getAddrSpaceId());
// First node in path is the mapped memory space whose virtual address
// we need to hand to CUDA
mappedBaseAddrSpaceId = path.front();
} catch (const std::out_of_range&) {
logger->error("Memory not reachable from process, but required by CUDA");
return false;
}
// Determine the base address of the mapped memory region needed by CUDA
const auto translationProcess = mm.getTranslationFromProcess(mappedBaseAddrSpaceId);
const uintptr_t baseAddrForProcess = translationProcess.getLocalAddr(0);
// Now check that the memory is also reachable via PCIe bus, otherwise GPU
// has no means to access it.
uintptr_t baseAddrOnPci;
size_t sizeOnPci;
try {
auto translationPci = mm.getTranslation(pciAddrSpaceId,
mappedBaseAddrSpaceId);
baseAddrOnPci = translationPci.getLocalAddr(0);
sizeOnPci = translationPci.getSize();
} catch (const std::out_of_range&) {
logger->error("Memory is not reachable via PCIe bus");
return false;
}
if (sizeOnPci < mem.getSize()) {
logger->warn("VA mapping of IO memory is too small: {:#x} instead of {:#x} bytes",
sizeOnPci, mem.getSize());
logger->warn("If something later on fails or behaves strangely, this might be the cause!");
}
cudaSetDevice(gpuId);
auto baseAddrVA = reinterpret_cast<void*>(baseAddrForProcess);
if (cudaHostRegister(baseAddrVA, sizeOnPci, cudaHostRegisterIoMemory) != cudaSuccess) {
logger->error("Cannot register IO memory for block {}", mem.getAddrSpaceId());
return false;
}
void* devicePointer = nullptr;
if (cudaHostGetDevicePointer(&devicePointer, baseAddrVA, 0) != cudaSuccess) {
logger->error("Cannot retrieve device pointer for IO memory");
return false;
}
mm.createMapping(reinterpret_cast<uintptr_t>(devicePointer), baseAddrOnPci,
sizeOnPci, "CudaIoMem", masterPciEAddrSpaceId, pciAddrSpaceId);
return true;
}
bool
Gpu::registerHostMemory(const MemoryBlock &mem)
{
auto &mm = MemoryManager::get();
auto translation = mm.getTranslationFromProcess(mem.getAddrSpaceId());
auto localBase = reinterpret_cast<void*>(translation.getLocalAddr(0));
int ret = cudaHostRegister(localBase, mem.getSize(), 0);
if (ret != cudaSuccess) {
logger->error("Cannot register memory block {} addr={:p} size={:#x} to CUDA: ret={}",
mem.getAddrSpaceId(), localBase, mem.getSize(), ret);
return false;
}
void* devicePointer = nullptr;
ret = cudaHostGetDevicePointer(&devicePointer, localBase, 0);
if (ret != cudaSuccess) {
logger->error("Cannot retrieve device pointer for IO memory: ret={}", ret);
return false;
}
mm.createMapping(reinterpret_cast<uintptr_t>(devicePointer), 0, mem.getSize(),
"CudaHostMem", masterPciEAddrSpaceId, mem.getAddrSpaceId());
return true;
}
bool Gpu::makeAccessibleToPCIeAndVA(const MemoryBlock &mem)
{
if (pImpl->gdr == nullptr) {
logger->warn("GDRcopy not available");
return false;
}
auto &mm = MemoryManager::get();
try {
auto path = mm.findPath(masterPciEAddrSpaceId, mem.getAddrSpaceId());
// If first hop is the PCIe bus, we know that memory is off-GPU
if (path.front() == mm.getPciAddressSpace())
throw std::out_of_range("Memory block is outside of this GPU");
} catch (const std::out_of_range&) {
logger->error("Trying to map non-GPU memory block");
return false;
}
logger->debug("retrieve complete device pointer from point of view of GPU");
// Retrieve complete device pointer from point of view of GPU
auto translation = mm.getTranslation(masterPciEAddrSpaceId,
mem.getAddrSpaceId());
CUdeviceptr devptr = translation.getLocalAddr(0);
int ret;
// Required to set this flag before mapping
unsigned int enable = 1;
ret = cuPointerSetAttribute(&enable, CU_POINTER_ATTRIBUTE_SYNC_MEMOPS, devptr);
if (ret != CUDA_SUCCESS) {
logger->error("Cannot set pointer attributes on memory block {}: {}",
mem.getAddrSpaceId(), ret);
return false;
}
gdr_mh_t mh;
ret = gdr_pin_buffer(pImpl->gdr, devptr, mem.getSize(), 0, 0, &mh);
if (ret != 0) {
logger->error("Cannot pin memory block {} via gdrcopy: {}",
mem.getAddrSpaceId(), ret);
return false;
}
void* bar = nullptr;
ret = gdr_map(pImpl->gdr, mh, &bar, mem.getSize());
if (ret != 0) {
logger->error("Cannot map memory block {} via gdrcopy: {}",
mem.getAddrSpaceId(), ret);
return false;
}
gdr_info_t info;
ret = gdr_get_info(pImpl->gdr, mh, &info);
if (ret != 0) {
logger->error("Cannot get info for mapping of memory block {}: {}",
mem.getAddrSpaceId(), ret);
return false;
}
const uintptr_t offset = info.va - devptr;
const uintptr_t userPtr = reinterpret_cast<uintptr_t>(bar) + offset;
logger->debug("BAR ptr: {:p}", bar);
logger->debug("info.va: {:#x}", info.va);
logger->debug("info.mapped_size: {:#x}", info.mapped_size);
logger->debug("info.page_size: {:#x}", info.page_size);
logger->debug("offset: {:#x}", offset);
logger->debug("user pointer: {:#x}", userPtr);
// Mapping to acceses memory block from process
mm.createMapping(userPtr, 0, info.mapped_size, "GDRcopy",
mm.getProcessAddressSpace(), mem.getAddrSpaceId());
// Retrieve bus address
uint64_t addr[8];
ret = gdr_map_dma(pImpl->gdr, mh, 3, 0, 0, addr, 8);
for (int i = 0; i < ret; i++)
logger->debug("DMA addr[{}]: {:#x}", i, addr[i]);
if (ret != 1) {
logger->error("Only one DMA address per block supported at the moment");
return false;
}
// Mapping to access memory block from peer devices via PCIe
mm.createMapping(addr[0], 0, mem.getSize(), "GDRcopyDMA",
mm.getPciAddressSpace(), mem.getAddrSpaceId());
return true;
}
bool
Gpu::makeAccessibleFromPCIeOrHostRam(const MemoryBlock &mem)
{
// Check which kind of memory this is and where it resides
// There are two possibilities:
// - Host memory not managed by CUDA
// - IO memory somewhere on the PCIe bus
auto &mm = MemoryManager::get();
bool isIoMemory = false;
try {
auto path = mm.findPath(mm.getPciAddressSpace(), mem.getAddrSpaceId());
isIoMemory = true;
} catch (const std::out_of_range&) {
// Not reachable via PCI -> not IO memory
}
if (isIoMemory) {
logger->debug("Memory block {} is assumed to be IO memory",
mem.getAddrSpaceId());
return registerIoMemory(mem);
}
else {
logger->debug("Memory block {} is assumed to be non-CUDA host memory",
mem.getAddrSpaceId());
return registerHostMemory(mem);
}
}
void Gpu::memcpySync(const MemoryBlock &src, const MemoryBlock &dst, size_t size)
{
auto &mm = MemoryManager::get();
auto src_translation = mm.getTranslation(masterPciEAddrSpaceId,
src.getAddrSpaceId());
const void* src_buf = reinterpret_cast<void*>(src_translation.getLocalAddr(0));
auto dst_translation = mm.getTranslation(masterPciEAddrSpaceId,
dst.getAddrSpaceId());
void* dst_buf = reinterpret_cast<void*>(dst_translation.getLocalAddr(0));
cudaSetDevice(gpuId);
cudaMemcpy(dst_buf, src_buf, size, cudaMemcpyDefault);
}
void Gpu::memcpyKernel(const MemoryBlock &src, const MemoryBlock &dst, size_t size)
{
auto &mm = MemoryManager::get();
auto src_translation = mm.getTranslation(masterPciEAddrSpaceId,
src.getAddrSpaceId());
auto src_buf = reinterpret_cast<uint8_t*>(src_translation.getLocalAddr(0));
auto dst_translation = mm.getTranslation(masterPciEAddrSpaceId,
dst.getAddrSpaceId());
auto dst_buf = reinterpret_cast<uint8_t*>(dst_translation.getLocalAddr(0));
cudaSetDevice(gpuId);
kernel_memcpy<<<1, 1>>>(dst_buf, src_buf, size);
cudaDeviceSynchronize();
}
MemoryTranslation
Gpu::translate(const MemoryBlock &dst)
{
auto &mm = MemoryManager::get();
return mm.getTranslation(masterPciEAddrSpaceId, dst.getAddrSpaceId());
}
std::unique_ptr<villas::MemoryBlock, villas::MemoryBlock::deallocator_fn>
GpuAllocator::allocateBlock(size_t size)
{
cudaSetDevice(gpu.gpuId);
void* addr;
auto &mm = MemoryManager::get();
// Search for an existing chunk that has enough free memory
auto chunk = std::find_if(chunks.begin(), chunks.end(), [&](const auto &chunk) {
return chunk->getAvailableMemory() >= size;
});
if (chunk != chunks.end()) {
logger->debug("Found existing chunk that can host the requested block");
return (*chunk)->allocateBlock(size);
}
else {
// Allocate a new chunk
// Rounded-up multiple of GPU page size
const size_t chunkSize = size - (size & (GpuPageSize - 1)) + GpuPageSize;
logger->debug("Allocate new chunk of {:#x} bytes", chunkSize);
if (cudaSuccess != cudaMalloc(&addr, chunkSize)) {
logger->error("cudaMalloc(..., size={}) failed", chunkSize);
throw std::bad_alloc();
}
// Assemble name for this block
std::stringstream name;
name << std::showbase << std::hex << reinterpret_cast<uintptr_t>(addr);
auto blockName = mm.getSlaveAddrSpaceName(getName(), name.str());
auto blockAddrSpaceId = mm.getOrCreateAddressSpace(blockName);
const auto localAddr = reinterpret_cast<uintptr_t>(addr);
std::unique_ptr<MemoryBlock, MemoryBlock::deallocator_fn>
mem(new MemoryBlock(localAddr, chunkSize, blockAddrSpaceId), this->free);
insertMemoryBlock(*mem);
// Already make accessible to CPU
gpu.makeAccessibleToPCIeAndVA(*mem);
// Create a new allocator to manage the chunk and push to chunk list
chunks.push_front(std::make_unique<LinearAllocator>(std::move(mem)));
// Call again, this time there's a large enough chunk
return allocateBlock(size);
}
}
Gpu::Gpu(int gpuId) :
pImpl{std::make_unique<impl>()},
gpuId(gpuId)
{
logger = villas::logging.get(getName());
pImpl->gdr = gdr_open();
if (pImpl->gdr == nullptr) {
logger->warn("No GDRcopy support enabled, cannot open /dev/gdrdrv");
}
}
bool Gpu::init()
{
auto &mm = MemoryManager::get();
const auto gpuPciEAddrSpaceName = mm.getMasterAddrSpaceName(getName(), "pcie");
masterPciEAddrSpaceId = mm.getOrCreateAddressSpace(gpuPciEAddrSpaceName);
allocator = std::make_unique<GpuAllocator>(*this);
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, gpuId);
pImpl->pdev.slot = {
deviceProp.pciDomainID,
deviceProp.pciBusID,
deviceProp.pciDeviceID,
0};
struct pci_region* pci_regions = nullptr;
const size_t pci_num_regions = pci_get_regions(&pImpl->pdev, &pci_regions);
for (size_t i = 0; i < pci_num_regions; i++) {
const size_t region_size = pci_regions[i].end - pci_regions[i].start + 1;
logger->info("BAR{}: bus addr={:#x} size={:#x}",
pci_regions[i].num, pci_regions[i].start, region_size);
char name[] = "BARx";
name[3] = '0' + pci_regions[i].num;
auto gpuBarXAddrSpaceName = mm.getSlaveAddrSpaceName(getName(), name);
auto gpuBarXAddrSpaceId = mm.getOrCreateAddressSpace(gpuBarXAddrSpaceName);
mm.createMapping(pci_regions[i].start, 0, region_size,
std::string("PCI-") + name,
mm.getPciAddressSpace(), gpuBarXAddrSpaceId);
}
free(pci_regions);
return true;
}
std::list<std::unique_ptr<Gpu>>
GpuFactory::make()
{
int deviceCount = 0;
cudaGetDeviceCount(&deviceCount);
std::list<std::unique_ptr<Gpu>> gpuList;
for (int gpuId = 0; gpuId < deviceCount; gpuId++) {
if (cudaSetDevice(gpuId) != cudaSuccess) {
logger->warn("Cannot activate GPU {}", gpuId);
continue;
}
auto gpu = std::make_unique<Gpu>(gpuId);
if (not gpu->init()) {
logger->warn("Cannot initialize GPU {}", gpuId);
continue;
}
gpuList.emplace_back(std::move(gpu));
}
logger->info("Initialized {} GPUs", gpuList.size());
for (auto &gpu : gpuList) {
logger->debug(" - {}", gpu->getName());
}
return gpuList;
}

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fpga/gpu/src/kernels.cu Normal file
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/** GPU Kernels.
*
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*********************************************************************************/
#include <stdio.h>
#include <villas/gpu.hpp>
#include <cuda_runtime.h>
#include <cuda.h>
#include "kernels.hpp"
using namespace villas::gpu;
__global__ void
kernel_mailbox(volatile uint32_t *mailbox, volatile uint32_t* counter)
{
printf("[gpu] hello!\n");
printf("[gpu] mailbox: %p\n", mailbox);
printf("[kernel] started\n");
while (1) {
if (*mailbox == 1) {
*mailbox = 0;
printf("[gpu] counter = %d\n", *counter);
break;
}
}
printf("[gpu] quit\n");
}
__global__ void
kernel_memcpy(volatile uint8_t* dst, volatile uint8_t* src, size_t length)
{
while (length > 0) {
*dst++ = *src++;
length--;
}
}

1
fpga/gpu/thirdparty/gdrcopy vendored Submodule

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Subproject commit fcf4bc56687c01e71379c174b6875bd3a99b31c7

58
fpga/include/villas/fpga/card.hpp Normal file
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/* FPGA card
*
* This class represents a FPGA device.
*
* Author: Steffen Vogel <post@steffenvogel.de>
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <set>
#include <villas/fpga/core.hpp>
#include <villas/kernel/vfio_container.hpp>
namespace villas {
namespace fpga {
class Card
{
public:
bool polling;
std::string name; // The name of the FPGA card
std::shared_ptr<kernel::vfio::Container> vfioContainer;
std::shared_ptr<kernel::vfio::Device> vfioDevice;
// Slave address space ID to access the PCIe address space from the
// FPGA
MemoryManager::AddressSpaceId addrSpaceIdDeviceToHost;
// Address space identifier of the master address space of this FPGA
// card. This will be used for address resolution of all IPs on this
// card.
MemoryManager::AddressSpaceId addrSpaceIdHostToDevice;
std::list<std::shared_ptr<ip::Core>> ips;
virtual ~Card();
virtual bool mapMemoryBlock(const std::shared_ptr<MemoryBlock> block);
virtual bool unmapMemoryBlock(const MemoryBlock &block);
std::shared_ptr<ip::Core> lookupIp(const std::string &name) const;
std::shared_ptr<ip::Core> lookupIp(const Vlnv &vlnv) const;
std::shared_ptr<ip::Core> lookupIp(const ip::IpIdentifier &id) const;
protected:
// Keep a map of already mapped memory blocks
std::map<MemoryManager::AddressSpaceId, std::shared_ptr<MemoryBlock>> memoryBlocksMapped;
Logger logger;
};
} // namespace fpga
} // namespace villas

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fpga/include/villas/fpga/config.h Normal file
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/* Compile time configuration
*
* This file contains some compiled-in settings.
* This settings are not part of the configuration file.
*
* Author: Steffen Vogel <post@steffenvogel.de>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// PCIe BAR number of VILLASfpga registers
#define FPGA_PCI_BAR 0
#define FPGA_PCI_VID_XILINX 0x10ee
#define FPGA_PCI_PID_VFPGA 0x7022
/* AXI Bus frequency for all components
* except RTDS AXI Stream bridge which runs at RTDS_HZ (100 Mhz) */
#define FPGA_AXI_HZ 125000000 // 125 MHz

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/* Interlectual Property component.
*
* This class represents a module within the FPGA.
*
* Author: Steffen Vogel <post@steffenvogel.de>
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <map>
#include <list>
#include <memory>
#include <jansson.h>
#include <fmt/ostream.h>
#include <villas/log.hpp>
#include <villas/colors.hpp>
#include <villas/config.hpp>
#include <villas/memory.hpp>
#include <villas/plugin.hpp>
#include <villas/fpga/vlnv.hpp>
namespace villas {
namespace fpga {
// Forward declarations
class Card;
namespace ip {
// Forward declarations
class Core;
class CoreFactory;
class InterruptController;
class IpIdentifier {
public:
IpIdentifier(const Vlnv &vlnv = Vlnv::getWildcard(), const std::string &name = "") :
vlnv(vlnv),
name(name)
{ }
IpIdentifier(const std::string &vlnvString, const std::string &name = "") :
vlnv(vlnvString),
name(name)
{ }
const std::string&
getName() const
{
return name;
}
const Vlnv&
getVlnv() const
{
return vlnv;
}
friend std::ostream&
operator<< (std::ostream &stream, const IpIdentifier &id)
{
return stream << id.name << " vlnv=" << id.vlnv;
}
bool
operator==(const IpIdentifier &otherId) const {
const bool vlnvWildcard = otherId.getVlnv() == Vlnv::getWildcard();
const bool nameWildcard = this->getName().empty() or otherId.getName().empty();
const bool vlnvMatch = vlnvWildcard or this->getVlnv() == otherId.getVlnv();
const bool nameMatch = nameWildcard or this->getName() == otherId.getName();
return vlnvMatch and nameMatch;
}
bool
operator!=(const IpIdentifier &otherId) const
{
return !(*this == otherId);
}
private:
Vlnv vlnv;
std::string name;
};
class Core {
friend CoreFactory;
public:
Core() :
card(nullptr)
{ }
virtual
~Core() = default;
public:
// Generic management interface for IPs
// Runtime setup of IP, should access and initialize hardware
virtual
bool init()
{
return true;
}
// Runtime check of IP, should verify basic functionality
virtual
bool check()
{
return true;
}
// Generic disabling of IP, meaning may depend on IP
virtual
bool stop()
{
return true;
}
// Reset the IP, it should behave like freshly initialized afterwards
virtual
bool reset()
{
return true;
}
// Print some debug information about the IP
virtual
void dump();
protected:
// Key-type for accessing maps addressTranslations and slaveAddressSpaces
using MemoryBlockName = std::string;
// Each IP can declare via this function which memory blocks it requires
virtual
std::list<MemoryBlockName> getMemoryBlocks() const
{
return {};
}
public:
const std::string& getInstanceName() const
{
return id.getName();
}
// Operators
bool operator==(const Vlnv &otherVlnv) const
{
return id.getVlnv() == otherVlnv;
}
bool operator!=(const Vlnv &otherVlnv) const
{
return id.getVlnv() != otherVlnv;
}
bool operator==(const IpIdentifier &otherId) const
{
return this->id == otherId;
}
bool operator!=(const IpIdentifier &otherId) const
{
return this->id != otherId;
}
bool operator==(const std::string &otherName) const
{
return getInstanceName() == otherName;
}
bool operator!=(const std::string &otherName) const
{
return getInstanceName() != otherName;
}
bool operator==(const Core &otherIp) const
{
return this->id == otherIp.id;
}
bool operator!=(const Core &otherIp) const
{
return this->id != otherIp.id;
}
friend
std::ostream& operator<< (std::ostream &stream, const Core &ip)
{
return stream << ip.id;
}
protected:
uintptr_t getBaseAddr(const MemoryBlockName &block) const
{
return getLocalAddr(block, 0);
}
uintptr_t getLocalAddr(const MemoryBlockName &block, uintptr_t address) const;
MemoryManager::AddressSpaceId getAddressSpaceId(const MemoryBlockName &block) const
{
return slaveAddressSpaces.at(block);
}
InterruptController* getInterruptController(const std::string &interruptName) const;
MemoryManager::AddressSpaceId getMasterAddrSpaceByInterface(const std::string &masterInterfaceName) const
{
return busMasterInterfaces.at(masterInterfaceName);
}
template<typename T>
T readMemory(const std::string &block, uintptr_t address) const
{
return *(reinterpret_cast<T*>(getLocalAddr(block, address)));
}
template<typename T>
void writeMemory(const std::string &block, uintptr_t address, T value)
{
T* ptr = reinterpret_cast<T*>(getLocalAddr(block, address)); *ptr = value;
}
protected:
struct IrqPort {
int num;
InterruptController* irqController;
std::string description;
};
// Specialized logger instance with the IPs name set as category
Logger logger;
// FPGA card this IP is instantiated on (populated by FpgaIpFactory)
Card* card;
// Identifier of this IP with its instance name and VLNV
IpIdentifier id;
// All interrupts of this IP with their associated interrupt controller
std::map<std::string, IrqPort> irqs;
// Cached translations from the process address space to each memory block
std::map<MemoryBlockName, MemoryTranslation> addressTranslations;
// Lookup for IP's slave address spaces (= memory blocks)
std::map<MemoryBlockName, MemoryManager::AddressSpaceId> slaveAddressSpaces;
// AXI bus master interfaces to access memory somewhere
std::map<std::string, MemoryManager::AddressSpaceId> busMasterInterfaces;
};
class CoreFactory : public plugin::Plugin {
public:
using plugin::Plugin::Plugin;
// Returns a running and checked FPGA IP
static
std::list<std::shared_ptr<Core>> make(Card* card, json_t *json_ips);
virtual
std::string getType() const
{
return "core";
}
protected:
enum PollingMode {
POLL,
IRQ,
};
Logger getLogger()
{
return villas::logging.get(getName());
}
// Configure IP instance from JSON config
virtual
void parse(Core &, json_t *)
{ }
static
Logger getStaticLogger()
{
return villas::logging.get("core:factory");
}
private:
virtual
void configurePollingMode(Core &, PollingMode)
{ }
virtual
Vlnv getCompatibleVlnv() const = 0;
// Create a concrete IP instance
virtual
Core* make() const = 0;
static
CoreFactory* lookup(const Vlnv &vlnv);
};
template<typename T, const char *name, const char *desc, const char *vlnv>
class CorePlugin : public CoreFactory {
public:
virtual
std::string getName() const
{
return name;
}
virtual
std::string getDescription() const
{
return desc;
}
private:
virtual
Vlnv getCompatibleVlnv() const
{
return Vlnv(vlnv);
}
// Create a concrete IP instance
Core* make() const
{
return new T;
};
};
} // namespace ip
} // namespace fpga
} // namespace villas
#ifndef FMT_LEGACY_OSTREAM_FORMATTER
template <>
class fmt::formatter<villas::fpga::ip::IpIdentifier>
: public fmt::ostream_formatter {};
template <>
class fmt::formatter<villas::fpga::ip::Core>
: public fmt::ostream_formatter {};
#endif

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/* C bindings for VILLASfpga
*
* Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
* SPDX-FileCopyrightText: 2023 Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _VILLASFPGA_DMA_H
#define _VILLASFPGA_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stddef.h>
typedef struct villasfpga_handle_t *villasfpga_handle;
typedef struct villasfpga_memory_t *villasfpga_memory;
villasfpga_handle villasfpga_init(const char *configFile);
void villasfpga_destroy(villasfpga_handle handle);
int villasfpga_alloc(villasfpga_handle handle, villasfpga_memory *mem, size_t size);
int villasfpga_register(villasfpga_handle handle, villasfpga_memory *mem);
int villasfpga_free(villasfpga_memory mem);
void* villasfpga_get_ptr(villasfpga_memory mem);
int villasfpga_read(villasfpga_handle handle, villasfpga_memory mem, size_t size);
int villasfpga_read_complete(villasfpga_handle handle, size_t *size);
int villasfpga_write(villasfpga_handle handle, villasfpga_memory mem, size_t size);
int villasfpga_write_complete(villasfpga_handle handle, size_t *size);
#ifdef __cplusplus
} // extern "C"
#endif
#endif // _VILLASFPGA_DMA_H

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/* Driver for wrapper around Aurora (acs.eonerc.rwth-aachen.de:user:aurora)
*
* Author: Hatim Kanchwala <hatim@hatimak.me>
* SPDX-FileCopyrightText: 2020 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <villas/fpga/node.hpp>
namespace villas {
namespace fpga {
namespace ip {
class Aurora : public Node {
public:
static constexpr const char* masterPort = "m_axis";
static constexpr const char* slavePort = "s_axis";
virtual
void dump() override;
std::list<std::string> getMemoryBlocks() const
{
return {
registerMemory
};
}
const StreamVertex&
getDefaultSlavePort() const
{
return getSlavePort(slavePort);
}
const StreamVertex&
getDefaultMasterPort() const
{
return getMasterPort(masterPort);
}
void
setLoopback(bool state);
void
resetFrameCounters();
private:
static constexpr const char registerMemory[] = "reg0";
};
} // namespace ip
} // namespace fpga
} // namespace villas

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/* Driver for wrapper around standard Xilinx Aurora (xilinx.com:ip:aurora_8b10b)
*
* Author: Steffen Vogel <post@steffenvogel.de>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <villas/fpga/node.hpp>
namespace villas {
namespace fpga {
namespace ip {
class AuroraXilinx : public Node {
public:
static constexpr const char* masterPort = "USER_DATA_M_AXI_RX";
static constexpr const char* slavePort = "USER_DATA_S_AXI_TX";
const StreamVertex&
getDefaultSlavePort() const
{
return getSlavePort(slavePort);
}
const StreamVertex&
getDefaultMasterPort() const
{
return getMasterPort(masterPort);
}
};
} // namespace ip
} // namespace fpga
} // namespace villas

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/* Block-Raam related helper functions
*
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2018 Daniel Krebs <github@daniel-krebs.net>
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <villas/memory.hpp>
#include <villas/fpga/core.hpp>
namespace villas {
namespace fpga {
namespace ip {
class BramFactory;
class Bram : public Core {
friend class BramFactory;
public:
virtual
bool init() override;
LinearAllocator& getAllocator()
{
return *allocator;
}
private:
static constexpr
const char* memoryBlock = "Mem0";
std::list<MemoryBlockName> getMemoryBlocks() const
{
return {
memoryBlock
};
}
size_t size;
std::unique_ptr<LinearAllocator> allocator;
};
class BramFactory : public CoreFactory {
public:
virtual
std::string getName() const
{
return "bram";
}
virtual
std::string getDescription() const
{
return "Block RAM";
}
private:
virtual
Vlnv getCompatibleVlnv() const
{
return Vlnv("xilinx.com:ip:axi_bram_ctrl:");
}
// Create a concrete IP instance
Core* make() const
{
return new Bram;
};
protected:
virtual
void parse(Core &, json_t *) override;
};
} // namespace ip
} // namespace fpga
} // namespace villas

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/* Driver for wrapper around Dino
*
* Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
* Author: Steffen Vogel <svogel2@eonerc.rwth-aachen.de>
* SPDX-FileCopyrightText: 2024 Niklas Eiling
* SPDX-FileCopyrightText: 2020 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <villas/fpga/ips/i2c.hpp>
#include <villas/fpga/node.hpp>
namespace villas {
namespace fpga {
namespace ip {
class Dino : public Node {
public:
friend class DinoFactory;
union IoextPorts {
struct __attribute__((packed)) {
bool clk_dir : 1;
bool data_dir : 1;
bool status_led : 1;
bool n_we : 1; // write enable (active low)
bool input_zero : 1;
bool sat_detect : 1;
bool gain_lsb : 1;
bool gain_msb : 1;
} fields;
uint8_t raw;
friend std::ostream &operator<<(std::ostream &stream,
const IoextPorts &ports) {
return stream << "IoextPorts [clk_dir=" << ports.fields.clk_dir
<< ", data_dir=" << ports.fields.data_dir
<< ", status_led=" << ports.fields.status_led
<< ", n_we=" << ports.fields.n_we
<< ", input_zero=" << ports.fields.input_zero
<< ", sat_detect=" << ports.fields.sat_detect
<< ", gain_lsb=" << ports.fields.gain_lsb
<< ", gain_msb=" << ports.fields.gain_msb << "]";
}
std::string toString() {
std::stringstream s;
s << *this;
return s.str();
}
};
enum Gain { GAIN_1 = 0, GAIN_2 = 1, GAIN_5 = 2, GAIN_10 = 3 };
Dino();
virtual ~Dino();
virtual bool init() override;
void setI2c(std::shared_ptr<I2c> i2cdev, uint8_t i2c_channel) {
this->i2cdev = i2cdev;
this->i2c_channel = i2c_channel;
}
virtual void configureHardware() = 0;
static constexpr const char *masterPort = "M00_AXIS";
static constexpr const char *slavePort = "S00_AXIS";
const StreamVertex &getDefaultSlavePort() const {
return getSlavePort(slavePort);
}
const StreamVertex &getDefaultMasterPort() const {
return getMasterPort(masterPort);
}
IoextPorts getIoextDirectionRegister();
IoextPorts getIoextOutputRegister();
protected:
std::shared_ptr<I2c> i2cdev;
uint8_t i2c_channel;
bool configDone;
IoextPorts getIoextDir();
IoextPorts getIoextOut();
void setIoextDir(IoextPorts ports);
void setIoextOut(IoextPorts ports);
};
class DinoAdc : public Dino {
public:
DinoAdc();
virtual ~DinoAdc();
virtual void configureHardware() override;
};
class DinoDac : public Dino {
public:
DinoDac();
virtual ~DinoDac();
virtual void configureHardware() override;
void setGain(Gain gain);
Gain getGain();
};
class DinoFactory : NodeFactory {
public:
virtual std::string getDescription() const { return "Dino Analog I/O"; }
protected:
virtual void parse(Core &ip, json_t *json) override;
};
class DinoAdcFactory : DinoFactory {
public:
virtual std::string getName() const { return "dinoAdc"; }
private:
virtual Vlnv getCompatibleVlnv() const {
return Vlnv("xilinx.com:module_ref:dinoif_fast:");
}
Core *make() const { return new DinoAdc; };
};
class DinoDacFactory : DinoFactory {
public:
virtual std::string getName() const { return "dinoDac"; }
private:
virtual Vlnv getCompatibleVlnv() const {
return Vlnv("xilinx.com:module_ref:dinoif_dac:");
}
Core *make() const { return new DinoDac; };
};
} // namespace ip
} // namespace fpga
} // namespace villas
#ifndef FMT_LEGACY_OSTREAM_FORMATTER
template <>
class fmt::formatter<villas::fpga::ip::Dino> : public fmt::ostream_formatter {};
template <>
class fmt::formatter<villas::fpga::ip::Dino::IoextPorts>
: public fmt::ostream_formatter {};
#endif

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/* DMA driver
*
* Author: Daniel Krebs <github@daniel-krebs.net>
* Author: Steffen Vogel <post@steffenvogel.de>
* Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
* SPDX-FileCopyrightText: 2018 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <fmt/ostream.h>
#include <xilinx/xaxidma.h>
#include <villas/config.hpp>
#include <villas/memory.hpp>
#include <villas/fpga/node.hpp>
#include <villas/exceptions.hpp>
namespace villas {
namespace fpga {
namespace ip {
class Dma : public Node
{
public:
friend class DmaFactory;
virtual
~Dma();
virtual
bool init() override;
bool reset() override;
// Memory-mapped to stream (MM2S)
bool write(const MemoryBlock &mem, size_t len);
// Stream to memory-mapped (S2MM)
bool read(const MemoryBlock &mem, size_t len);
struct Completion {
Completion() : bytes(0), bds(0), interrupts(0) { }
size_t bytes; // Number of bytes transferred
size_t bds; // Number of buffer descriptors used (only for scatter-gather)
size_t interrupts; // Number of interrupts received since last call (only if interrupts enabled)
};
Completion writeComplete()
{
return hasScatterGather() ? writeCompleteScatterGather() : writeCompleteSimple();
}
Completion readComplete()
{
return hasScatterGather() ? readCompleteScatterGather() : readCompleteSimple();
}
bool memcpy(const MemoryBlock &src, const MemoryBlock &dst, size_t len);
void makeAccesibleFromVA(std::shared_ptr<MemoryBlock> mem);
bool makeInaccesibleFromVA(const MemoryBlock &mem);
inline
bool hasScatterGather() const
{
return xConfig.HasSg;
}
const StreamVertex& getDefaultSlavePort() const
{
return getSlavePort(s2mmPort);
}
const StreamVertex& getDefaultMasterPort() const
{
return getMasterPort(mm2sPort);
}
static constexpr const char* s2mmPort = "S2MM";
static constexpr const char* mm2sPort = "MM2S";
bool isMemoryBlockAccesible(const MemoryBlock &mem, const std::string &interface);
virtual
void dump() override;
private:
bool writeScatterGather(const void* buf, size_t len);
bool readScatterGather(void* buf, size_t len);
Completion writeCompleteScatterGather();
Completion readCompleteScatterGather();
bool writeSimple(const void* buf, size_t len);
bool readSimple(void* buf, size_t len);
Completion writeCompleteSimple();
Completion readCompleteSimple();
void setupScatterGather();
void setupScatterGatherRingRx();
void setupScatterGatherRingTx();
static constexpr char registerMemory[] = "Reg";
static constexpr char mm2sInterrupt[] = "mm2s_introut";
static constexpr char mm2sInterface[] = "M_AXI_MM2S";
static constexpr char s2mmInterrupt[] = "s2mm_introut";
static constexpr char s2mmInterface[] = "M_AXI_S2MM";
// Optional Scatter-Gather interface to access descriptors
static constexpr char sgInterface[] = "M_AXI_SG";
std::list<MemoryBlockName> getMemoryBlocks() const
{
return {
registerMemory
};
}
XAxiDma xDma;
XAxiDma_Config xConfig;
std::mutex hwLock;
bool configDone = false;
// use polling to wait for DMA completion or interrupts via efds
bool polling = false;
// Timeout after which the DMA controller issues in interrupt if no data has been received
// Delay is 125 x <delay> x (clock period of SG clock). SG clock is 100 MHz by default.
int delay = 0;
// Coalesce is the number of messages/BDs to wait for before issuing an interrupt
uint32_t writeCoalesce = 1;
uint32_t readCoalesce = 1;
// (maximum) size of a single message on the read channel in bytes.
// The message buffer/BD should have enough room for this many bytes.
size_t readMsgSize = 4;
// When using SG: ringBdSize is the maximum number of BDs usable in the ring
// Depending on alignment, the actual number of BDs usable can be smaller
static constexpr size_t requestedRingBdSize = 2048;
static constexpr size_t requestedRingBdSizeMemory = requestedRingBdSize * sizeof(XAxiDma_Bd);
uint32_t actualRingBdSize = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT, requestedRingBdSizeMemory);
std::shared_ptr<MemoryBlock> sgRingTx;
std::shared_ptr<MemoryBlock> sgRingRx;
};
class DmaFactory : NodeFactory {
public:
virtual
std::string getName() const
{
return "dma";
}
virtual
std::string getDescription() const
{
return "Xilinx's AXI4 Direct Memory Access Controller";
}
private:
virtual
Vlnv getCompatibleVlnv() const
{
return Vlnv("xilinx.com:ip:axi_dma:");
}
// Create a concrete IP instance
Core* make() const
{
return new Dma;
};
protected:
virtual
void parse(Core& ip, json_t* json) override;
virtual
void configurePollingMode(Core& ip, PollingMode mode) override
{
dynamic_cast<Dma&>(ip).polling = (mode == POLL);
}
};
} // namespace ip
} // namespace fpga
} // namespace villas
#ifndef FMT_LEGACY_OSTREAM_FORMATTER
template <>
class fmt::formatter<villas::fpga::ip::Dma>
: public fmt::ostream_formatter {};
#endif

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/* AXI External Memory Controller (EMC)
*
* Author: Steffen Vogel <post@steffenvogel.de>
* SPDX-FileCopyrightText: 2017 Steffen Vogel <post@steffenvogel.de>
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <xilinx/xilflash.h>
#include <villas/fpga/core.hpp>
namespace villas {
namespace fpga {
namespace ip {
class EMC : public Core {
public:
virtual
bool init() override;
bool flash(uint32_t offset, const std::string &filename);
bool flash(uint32_t offset, uint32_t length, uint8_t *data);
bool read(uint32_t offset, uint32_t length, uint8_t *data);
private:
XFlash xflash;
static constexpr char registerMemory[] = "Reg";
std::list<MemoryBlockName> getMemoryBlocks() const
{
return {
registerMemory
};
}
};
} // namespace ip
} // namespace fpga
} // namespace villas

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/* Timer related helper functions
*
* These functions present a simpler interface to Xilinx' Timer Counter driver (XTmrCtr_*)
*
* Author: Steffen Vogel <post@steffenvogel.de>
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Steffen Vogel <post@steffenvogel.de>
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <xilinx/xllfifo.h>
#include <villas/fpga/node.hpp>
namespace villas {
namespace fpga {
namespace ip {
class Fifo : public Node {
public:
friend class FifoFactory;
virtual
bool init() override;
virtual
bool stop() override;
size_t write(const void* buf, size_t len);
size_t read(void* buf, size_t len);
private:
static constexpr char registerMemory[] = "Mem0";
static constexpr char axi4Memory[] = "Mem1";
static constexpr char irqName[] = "interrupt";
std::list<MemoryBlockName> getMemoryBlocks() const
{
return {
registerMemory,
axi4Memory
};
}
XLlFifo xFifo;
};
class FifoData : public Node {
friend class FifoDataFactory;
};
} // namespace ip
} // namespace fpga
} // namespace villas

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/* AXI General Purpose IO (GPIO)
*
* Author: Steffen Vogel <post@steffenvogel.de>
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Steffen Vogel <post@steffenvogel.de>
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <villas/fpga/core.hpp>
namespace villas {
namespace fpga {
namespace ip {
class Gpio : public Core {
public:
virtual
bool init() override;
private:
static constexpr char registerMemory[] = "Reg";
std::list<MemoryBlockName> getMemoryBlocks() const
{
return {
registerMemory
};
}
};
} // namespace ip
} // namespace fpga
} // namespace villas

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/* GPU2RTDS IP core
*
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Daniel Krebs <github@daniel-krebs.net>
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <villas/memory.hpp>
#include <villas/fpga/node.hpp>
#include <villas/fpga/ips/hls.hpp>
#include <villas/fpga/ips/rtds2gpu/register_types.hpp>
#include <villas/fpga/ips/rtds2gpu/xgpu2rtds_hw.h>
namespace villas {
namespace fpga {
namespace ip {
class Gpu2Rtds : public Node, public Hls
{
public:
friend class Gpu2RtdsFactory;
virtual
bool init() override;
void dump(spdlog::level::level_enum logLevel = spdlog::level::info);
bool startOnce(size_t frameSize);
size_t getMaxFrameSize();
const StreamVertex&
getDefaultMasterPort() const
{
return getMasterPort(rtdsOutputStreamPort);
}
MemoryBlock
getRegisterMemory() const
{
return MemoryBlock(0, 1 << 10, getAddressSpaceId(registerMemory));
}
private:
bool updateStatus();
public:
static constexpr const char* rtdsOutputStreamPort = "rtds_output";
struct StatusControlRegister { uint32_t
status_ap_vld : 1,
_res : 31;
};
using StatusRegister = axilite_reg_status_t;
static constexpr uintptr_t registerStatusOffset = XGPU2RTDS_CTRL_ADDR_STATUS_DATA;
static constexpr uintptr_t registerStatusCtrlOffset = XGPU2RTDS_CTRL_ADDR_STATUS_CTRL;
static constexpr uintptr_t registerFrameSizeOffset = XGPU2RTDS_CTRL_ADDR_FRAME_SIZE_DATA;
static constexpr uintptr_t registerFrameOffset = XGPU2RTDS_CTRL_ADDR_FRAME_BASE;
static constexpr uintptr_t registerFrameLength = XGPU2RTDS_CTRL_DEPTH_FRAME;
public:
StatusRegister* registerStatus;
StatusControlRegister* registerStatusCtrl;
uint32_t* registerFrameSize;
uint32_t* registerFrames;
size_t maxFrameSize;
bool started;
};
} // namespace ip
} // namespace fpga
} // namespace villas

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/* HLS IP core
*
* Author: Steffen Vogel <post@steffenvogel.de>
* SPDX-FileCopyrightText: 2017 Steffen Vogel
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <villas/memory.hpp>
#include <villas/fpga/node.hpp>
namespace villas {
namespace fpga {
namespace ip {
class Hls : public virtual Core
{
public:
virtual
bool init() override
{
auto &registers = addressTranslations.at(registerMemory);
controlRegister = reinterpret_cast<ControlRegister*>(registers.getLocalAddr(registerControlAddr));
globalIntRegister = reinterpret_cast<GlobalIntRegister*>(registers.getLocalAddr(registerGlobalIntEnableAddr));
ipIntEnableRegister = reinterpret_cast<IpIntRegister*>(registers.getLocalAddr(registerIntEnableAddr));
ipIntStatusRegister = reinterpret_cast<IpIntRegister*>(registers.getLocalAddr(registerIntStatusAddr));
setAutoRestart(false);
setGlobalInterrupt(false);
return true;
}
bool start()
{
controlRegister->ap_start = true;
running = true;
return true;
}
virtual bool isFinished()
{
updateRunningStatus();
return !running;
}
bool isRunning()
{
updateRunningStatus();
return running;
}
void setAutoRestart(bool enabled) const
{
controlRegister->auto_restart = enabled;
}
void setGlobalInterrupt(bool enabled) const
{
globalIntRegister->globalInterruptEnable = enabled;
}
void setReadyInterrupt(bool enabled) const
{
ipIntEnableRegister->ap_ready = enabled;
}
void setDoneInterrupt(bool enabled) const
{
ipIntEnableRegister->ap_done = enabled;
}
bool isIdleBit() const
{
return controlRegister->ap_idle;
}
bool isReadyBit() const
{
return controlRegister->ap_ready;
}
// Warning: the corresponding bit is cleared on read of the register, so if
// not used correctly, this function may never return true. Only use this
// function if you really know what you are doing!
bool isDoneBit() const
{
return controlRegister->ap_done;
}
bool isAutoRestartBit() const
{
return controlRegister->auto_restart;
}
private:
void updateRunningStatus()
{
if (running and isIdleBit())
running = false;
}
protected:
// Memory block handling
static constexpr const char* registerMemory = "Reg";
virtual std::list<MemoryBlockName> getMemoryBlocks() const
{
return {
registerMemory
};
}
public:
// Register definitions
static constexpr uintptr_t registerControlAddr = 0x00;
static constexpr uintptr_t registerGlobalIntEnableAddr = 0x04;
static constexpr uintptr_t registerIntEnableAddr = 0x08;
static constexpr uintptr_t registerIntStatusAddr = 0x0c;
union ControlRegister {
uint32_t value;
struct { uint32_t
ap_start : 1,
ap_done : 1,
ap_idle : 1,
ap_ready : 1,
_res1 : 3,
auto_restart : 1,
_res2 : 24;
};
};
struct GlobalIntRegister { uint32_t
globalInterruptEnable : 1,
_res : 31;
};
struct IpIntRegister { uint32_t
ap_done : 1,
ap_ready : 1,
_res : 30;
};
protected:
ControlRegister* controlRegister;
GlobalIntRegister* globalIntRegister;
IpIntRegister* ipIntEnableRegister;
IpIntRegister* ipIntStatusRegister;
bool running;
};
} // namespace ip
} // namespace fpga
} // namespace villas

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/* I2C driver
*
* Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
* SPDX-FileCopyrightText: 2023 Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <fmt/ostream.h>
#include <villas/config.hpp>
#include <villas/exceptions.hpp>
#include <villas/fpga/node.hpp>
#include <villas/memory.hpp>
#include <xilinx/xiic.h>
namespace villas {
namespace fpga {
namespace ip {
#define I2C_SWTICH_ADDR 0x70
#define I2C_SWITCH_CHANNEL_MAP \
{ 0x20, 0x80, 0x02, 0x08, 0x10, 0x40, 0x01, 0x04 }
#define I2C_IOEXT_ADDR 0x20
#define I2C_IOEXT_REG_DIR 0x03
#define I2C_IOEXT_REG_OUT 0x01
#define I2C_EEPROM_ADDR 0x50
class I2c : public Node {
public:
friend class I2cFactory;
I2c();
virtual ~I2c();
virtual bool init() override;
virtual bool check() override;
virtual bool reset() override;
virtual bool stop() override;
bool write(u8 address, std::vector<u8> &data);
bool read(u8 address, std::vector<u8> &data, size_t max_read);
bool readRegister(u8 address, u8 reg, std::vector<u8> &data, size_t max_read);
int transmitIntrs;
int receiveIntrs;
int statusIntrs;
class Switch {
public:
Switch(I2c *i2c, uint8_t address,
Logger logger = villas::logging.get("i2c"))
: i2c(i2c), address(address), channel(0), readOnce(false), switchLock(),
logger(logger){};
Switch(const Switch &other) = delete;
Switch &operator=(const Switch &other) = delete;
void setChannel(uint8_t channel);
void setAndLockChannel(uint8_t channel) {
switchLock.lock();
setChannel(channel);
}
void unlockChannel() { switchLock.unlock(); }
uint8_t getChannel();
void setAddress(uint8_t address) { this->address = address; }
uint8_t getAddress() { return address; }
bool selfTest();
private:
I2c *i2c;
uint8_t address;
uint8_t channel;
bool readOnce;
std::mutex switchLock;
Logger logger;
};
Switch &getSwitch(uint8_t address = I2C_SWTICH_ADDR) {
if (switchInstance == nullptr) {
switchInstance = std::make_unique<Switch>(this, address, logger);
} else {
switchInstance->setAddress(address);
}
return *switchInstance;
}
private:
static constexpr char registerMemory[] = "Reg";
static constexpr char i2cInterrupt[] = "iic2intc_irpt";
XIic xIic;
XIic_Config xConfig;
std::mutex hwLock;
bool configDone;
bool initDone;
bool polling;
std::unique_ptr<Switch> switchInstance;
std::list<MemoryBlockName> getMemoryBlocks() const {
return {registerMemory};
}
// assumes hwLock is locked
void waitForBusNotBusy();
void driverWriteBlocking(u8 *dataPtr, size_t size);
void driverReadBlocking(u8 *dataPtr, size_t max_read);
};
class I2cFactory : NodeFactory {
public:
virtual std::string getName() const { return "i2c"; }
virtual std::string getDescription() const {
return "Xilinx's AXI4 iic IP";
}
private:
virtual Vlnv getCompatibleVlnv() const {
return Vlnv("xilinx.com:ip:axi_iic:");
}
// Create a concrete IP instance
Core *make() const { return new I2c; };
protected:
virtual void parse(Core &ip, json_t *json) override;
virtual void configurePollingMode(Core &ip, PollingMode mode) override {
dynamic_cast<I2c &>(ip).polling = (mode == POLL);
}
};
} // namespace ip
} // namespace fpga
} // namespace villas
#ifndef FMT_LEGACY_OSTREAM_FORMATTER
template <>
class fmt::formatter<villas::fpga::ip::I2c> : public fmt::ostream_formatter {};
#endif

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/* AXI-PCIe Interrupt controller
*
* Author: Steffen Vogel <post@steffenvogel.de>
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Steffen Vogel <post@steffenvogel.de>
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <xilinx/xintc.h>
#include <villas/fpga/core.hpp>
namespace villas {
namespace fpga {
namespace ip {
class InterruptController : public Core {
public:
using IrqMaskType = uint32_t;
static constexpr int maxIrqs = 32;
virtual ~InterruptController();
virtual bool init() override;
virtual bool stop() override;
bool enableInterrupt(IrqMaskType mask, bool polling);
bool enableInterrupt(IrqPort irq, bool polling) {
return enableInterrupt(1 << irq.num, polling);
}
bool disableInterrupt(IrqMaskType mask);
bool disableInterrupt(IrqPort irq) { return disableInterrupt(1 << irq.num); }
ssize_t waitForInterrupt(int irq);
ssize_t waitForInterrupt(IrqPort irq) { return waitForInterrupt(irq.num); }
private:
static constexpr char registerMemory[] = "reg0";
std::list<MemoryBlockName> getMemoryBlocks() const
{
return {
registerMemory
};
}
struct Interrupt {
int eventFd; // Event file descriptor
int number; // Interrupt number from /proc/interrupts
bool polling; // Polled or not
};
int num_irqs; // Number of available MSI vectors
int efds[maxIrqs];
int nos[maxIrqs];
bool polling[maxIrqs];
};
} // namespace ip
} // namespace fpga
} // namespace villas

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/* AXI Stream interconnect related helper functions
*
* These functions present a simpler interface to Xilinx' AXI Stream switch driver (XAxis_Switch_*)
*
* Author: Steffen Vogel <post@steffenvogel.de>
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Steffen Vogel <post@steffenvogel.de>
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <xilinx/xaxis_switch.h>
#include <villas/fpga/node.hpp>
namespace villas {
namespace fpga {
namespace ip {
class AxiPciExpressBridge : public Core {
public:
friend class AxiPciExpressBridgeFactory;
virtual
bool init() override;
private:
static constexpr char axiInterface[] = "M_AXI";
static constexpr char pcieMemory[] = "BAR0";
struct AxiBar {
uintptr_t base;
size_t size;
uintptr_t translation;
};
struct PciBar {
uintptr_t translation;
};
std::map<std::string, AxiBar> axiToPcieTranslations;
std::map<std::string, PciBar> pcieToAxiTranslations;
};
class AxiPciExpressBridgeFactory : CoreFactory {
public:
virtual
std::string getName() const
{
return "pcie";
}
virtual
std::string getDescription() const
{
return "Xilinx's AXI-PCIe Bridge";
}
private:
virtual
Vlnv getCompatibleVlnv() const
{
return Vlnv("xilinx.com:ip:axi_pcie:");
}
// Create a concrete IP instance
Core* make() const
{
return new AxiPciExpressBridge;
};
protected:
virtual
void parse(Core &, json_t *) override;
};
} // namespace ip
} // namespace fpga
} // namespace villas

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/* Driver for register interface 'registerif'
*
* Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
* SPDX-FileCopyrightText: 2024 Niklas Eiling
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <villas/fpga/node.hpp>
namespace villas {
namespace fpga {
namespace ip {
class Register : public Node {
public:
Register();
virtual ~Register();
virtual bool init() override;
virtual bool check() override;
void setRegister(size_t reg, uint32_t value);
void setRegister(size_t reg, float value);
uint32_t getRegister(size_t reg);
float getRegisterFloat(size_t reg);
void resetRegister(size_t reg);
void resetAllRegisters();
protected:
const size_t registerNum = 8;
const size_t registerSize = 32;
static constexpr char registerMemory[] = "reg0";
std::list<MemoryBlockName> getMemoryBlocks() const {
return {registerMemory};
}
};
} // namespace ip
} // namespace fpga
} // namespace villas
#ifndef FMT_LEGACY_OSTREAM_FORMATTER
template <>
class fmt::formatter<villas::fpga::ip::Register>
: public fmt::ostream_formatter {};
#endif

54
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/* Driver for AXI Stream wrapper around RTDS_InterfaceModule (rtds_axis )
*
* Author: Steffen Vogel <post@steffenvogel.de>
* SPDX-FileCopyrightText: 2017 Steffen Vogel <post@steffenvogel.de>
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <villas/fpga/node.hpp>
namespace villas {
namespace fpga {
namespace ip {
class RtdsGtfpga : public Node {
public:
static constexpr const char* masterPort = "m_axis";
static constexpr const char* slavePort = "s_axis";
virtual
void dump() override;
double getDt();
std::list<std::string> getMemoryBlocks() const
{
return {
registerMemory
};
}
const StreamVertex&
getDefaultSlavePort() const
{
return getSlavePort(slavePort);
}
const StreamVertex&
getDefaultMasterPort() const
{
return getMasterPort(masterPort);
}
private:
static constexpr const char registerMemory[] = "reg0";
static constexpr const char* irqTs = "irq_ts";
static constexpr const char* irqOverflow = "irq_overflow";
static constexpr const char* irqCase = "irq_case";
};
} // namespace ip
} // namespace fpga
} // namespace villas

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/* GPU2RTDS IP core
*
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Daniel Krebs <github@daniel-krebs.net>
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <villas/memory.hpp>
#include <villas/fpga/node.hpp>
#include <villas/fpga/ips/hls.hpp>
#include "rtds2gpu/xrtds2gpu.h"
#include "rtds2gpu/register_types.hpp"
namespace villas {
namespace fpga {
namespace ip {
union ControlRegister {
uint32_t value;
struct { uint32_t
ap_start : 1,
ap_done : 1,
ap_idle : 1,
ap_ready : 1,
_res1 : 3,
auto_restart : 1,
_res2 : 24;
};
};
class Rtds2Gpu : public Node, public Hls
{
public:
friend class Rtds2GpuFactory;
virtual
bool init() override;
void dump(spdlog::level::level_enum logLevel = spdlog::level::info);
virtual
void dump() override
{
dump(spdlog::level::info);
}
bool startOnce(const MemoryBlock &mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset);
size_t getMaxFrameSize();
void dumpDoorbell(uint32_t doorbellRegister) const;
bool doorbellIsValid(const uint32_t &doorbellRegister) const
{
return reinterpret_cast<const reg_doorbell_t&>(doorbellRegister).is_valid;
}
void doorbellReset(uint32_t &doorbellRegister) const
{
doorbellRegister = 0;
}
std::list<MemoryBlockName> getMemoryBlocks() const
{
return {
registerMemory
};
}
const StreamVertex&
getDefaultSlavePort() const
{
return getSlavePort(rtdsInputStreamPort);
}
private:
bool updateStatus();
private:
static constexpr const char* axiInterface = "m_axi_axi_mm";
static constexpr const char* rtdsInputStreamPort = "rtds_input";
XRtds2gpu xInstance;
axilite_reg_status_t status;
size_t maxFrameSize;
bool started;
};
} // namespace ip
} // namespace fpga
} // namespace villas

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/* GPU2RTDS register types
*
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Daniel Krebs <github@daniel-krebs.net>
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <cstddef>
#include <cstdint>
union axilite_reg_status_t {
uint32_t value;
struct {
uint32_t
last_seq_nr : 16,
last_count : 6,
max_frame_size : 6,
invalid_frame_size : 1,
frame_too_short : 1,
frame_too_long : 1,
is_running : 1;
};
};
union reg_doorbell_t {
uint32_t value;
struct {
uint32_t
seq_nr : 16,
count : 6,
is_valid : 1;
};
constexpr reg_doorbell_t() : value(0) {}
};
template<size_t N, typename T = uint32_t>
struct Rtds2GpuMemoryBuffer {
// This type is only for memory interpretation, it makes no sense to create
// an instance so it's forbidden
Rtds2GpuMemoryBuffer() = delete;
// T can be a more complex type that wraps multiple values
static constexpr size_t rawValueCount = N * (sizeof(T) / 4);
// As of C++14, offsetof() is not working for non-standard layout types (i.e.
// composed of non-POD members). This might work in C++17 though.
// More info: https://gist.github.com/graphitemaster/494f21190bb2c63c5516
//static constexpr size_t doorbellOffset = offsetof(Rtds2GpuMemoryBuffer, doorbell);
//static constexpr size_t dataOffset = offsetof(Rtds2GpuMemoryBuffer, data);
// HACK: This might break horribly, let's just hope C++17 will be there soon
static constexpr size_t dataOffset = 0;
static constexpr size_t doorbellOffset = N * sizeof(Rtds2GpuMemoryBuffer::data);
T data[N];
reg_doorbell_t doorbell;
};

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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.3
// SPDX-FileCopyrightText: 1986 Xilinx, Inc. All Rights Reserved.
// SPDX-License-Identifier: Apache-2.0
// ==============================================================
// CTRL
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : Data signal of frame_size
// bit 31~0 - frame_size[31:0] (Read/Write)
// 0x14 : reserved
// 0x80 : Data signal of status
// bit 31~0 - status[31:0] (Read)
// 0x84 : Control signal of status
// bit 0 - status_ap_vld (Read/COR)
// others - reserved
// 0x40 ~
// 0x7f : Memory 'frame' (16 * 32b)
// Word n : bit [31:0] - frame[n]
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
#define XGPU2RTDS_CTRL_ADDR_AP_CTRL 0x00
#define XGPU2RTDS_CTRL_ADDR_GIE 0x04
#define XGPU2RTDS_CTRL_ADDR_IER 0x08
#define XGPU2RTDS_CTRL_ADDR_ISR 0x0c
#define XGPU2RTDS_CTRL_ADDR_FRAME_SIZE_DATA 0x10
#define XGPU2RTDS_CTRL_BITS_FRAME_SIZE_DATA 32
#define XGPU2RTDS_CTRL_ADDR_STATUS_DATA 0x80
#define XGPU2RTDS_CTRL_BITS_STATUS_DATA 32
#define XGPU2RTDS_CTRL_ADDR_STATUS_CTRL 0x84
#define XGPU2RTDS_CTRL_ADDR_FRAME_BASE 0x40
#define XGPU2RTDS_CTRL_ADDR_FRAME_HIGH 0x7f
#define XGPU2RTDS_CTRL_WIDTH_FRAME 32
#define XGPU2RTDS_CTRL_DEPTH_FRAME 16

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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.3
// SPDX-FileCopyrightText: 1986 Xilinx, Inc. All Rights Reserved.
// SPDX-License-Identifier: Apache-2.0
// ==============================================================
#ifndef XRTDS2GPU_H
#define XRTDS2GPU_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#ifndef __linux__
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xil_io.h"
#else
#include <stdint.h>
#include <assert.h>
#include <dirent.h>
#include <fcntl.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include <unistd.h>
#include <stddef.h>
#endif
#include "xrtds2gpu_hw.h"
/**************************** Type Definitions ******************************/
#ifdef __linux__
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
#else
typedef struct {
u16 DeviceId;
u32 Ctrl_BaseAddress;
} XRtds2gpu_Config;
#endif
typedef struct {
u32 Ctrl_BaseAddress;
u32 IsReady;
} XRtds2gpu;
/***************** Macros (Inline Functions) Definitions *********************/
#ifndef __linux__
#define XRtds2gpu_WriteReg(BaseAddress, RegOffset, Data) \
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
#define XRtds2gpu_ReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))
#else
#define XRtds2gpu_WriteReg(BaseAddress, RegOffset, Data) \
*(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data)
#define XRtds2gpu_ReadReg(BaseAddress, RegOffset) \
*(volatile u32*)((BaseAddress) + (RegOffset))
#define Xil_AssertVoid(expr) assert(expr)
#define Xil_AssertNonvoid(expr) assert(expr)
#define XST_SUCCESS 0
#define XST_DEVICE_NOT_FOUND 2
#define XST_OPEN_DEVICE_FAILED 3
#define XIL_COMPONENT_IS_READY 1
#endif
/************************** Function Prototypes *****************************/
#ifndef __linux__
int XRtds2gpu_Initialize(XRtds2gpu *InstancePtr, u16 DeviceId);
XRtds2gpu_Config* XRtds2gpu_LookupConfig(u16 DeviceId);
int XRtds2gpu_CfgInitialize(XRtds2gpu *InstancePtr, XRtds2gpu_Config *ConfigPtr);
#else
int XRtds2gpu_Initialize(XRtds2gpu *InstancePtr, const char* InstanceName);
int XRtds2gpu_Release(XRtds2gpu *InstancePtr);
#endif
void XRtds2gpu_Start(XRtds2gpu *InstancePtr);
u32 XRtds2gpu_IsDone(XRtds2gpu *InstancePtr);
u32 XRtds2gpu_IsIdle(XRtds2gpu *InstancePtr);
u32 XRtds2gpu_IsReady(XRtds2gpu *InstancePtr);
void XRtds2gpu_EnableAutoRestart(XRtds2gpu *InstancePtr);
void XRtds2gpu_DisableAutoRestart(XRtds2gpu *InstancePtr);
void XRtds2gpu_Set_baseaddr(XRtds2gpu *InstancePtr, u32 Data);
u32 XRtds2gpu_Get_baseaddr(XRtds2gpu *InstancePtr);
void XRtds2gpu_Set_data_offset(XRtds2gpu *InstancePtr, u32 Data);
u32 XRtds2gpu_Get_data_offset(XRtds2gpu *InstancePtr);
void XRtds2gpu_Set_doorbell_offset(XRtds2gpu *InstancePtr, u32 Data);
u32 XRtds2gpu_Get_doorbell_offset(XRtds2gpu *InstancePtr);
void XRtds2gpu_Set_frame_size(XRtds2gpu *InstancePtr, u32 Data);
u32 XRtds2gpu_Get_frame_size(XRtds2gpu *InstancePtr);
u32 XRtds2gpu_Get_status(XRtds2gpu *InstancePtr);
u32 XRtds2gpu_Get_status_vld(XRtds2gpu *InstancePtr);
void XRtds2gpu_InterruptGlobalEnable(XRtds2gpu *InstancePtr);
void XRtds2gpu_InterruptGlobalDisable(XRtds2gpu *InstancePtr);
void XRtds2gpu_InterruptEnable(XRtds2gpu *InstancePtr, u32 Mask);
void XRtds2gpu_InterruptDisable(XRtds2gpu *InstancePtr, u32 Mask);
void XRtds2gpu_InterruptClear(XRtds2gpu *InstancePtr, u32 Mask);
u32 XRtds2gpu_InterruptGetEnabled(XRtds2gpu *InstancePtr);
u32 XRtds2gpu_InterruptGetStatus(XRtds2gpu *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif

61
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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.3
// SPDX-FileCopyrightText: 1986 Xilinx, Inc. All Rights Reserved.
// SPDX-License-Identifier: Apache-2.0
// ==============================================================
// CTRL
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : Data signal of baseaddr
// bit 31~0 - baseaddr[31:0] (Read/Write)
// 0x14 : reserved
// 0x18 : Data signal of data_offset
// bit 31~0 - data_offset[31:0] (Read/Write)
// 0x1c : reserved
// 0x20 : Data signal of doorbell_offset
// bit 31~0 - doorbell_offset[31:0] (Read/Write)
// 0x24 : reserved
// 0x28 : Data signal of frame_size
// bit 31~0 - frame_size[31:0] (Read/Write)
// 0x2c : reserved
// 0x30 : Data signal of status
// bit 31~0 - status[31:0] (Read)
// 0x34 : Control signal of status
// bit 0 - status_ap_vld (Read/COR)
// others - reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
#define XRTDS2GPU_CTRL_ADDR_AP_CTRL 0x00
#define XRTDS2GPU_CTRL_ADDR_GIE 0x04
#define XRTDS2GPU_CTRL_ADDR_IER 0x08
#define XRTDS2GPU_CTRL_ADDR_ISR 0x0c
#define XRTDS2GPU_CTRL_ADDR_BASEADDR_DATA 0x10
#define XRTDS2GPU_CTRL_BITS_BASEADDR_DATA 32
#define XRTDS2GPU_CTRL_ADDR_DATA_OFFSET_DATA 0x18
#define XRTDS2GPU_CTRL_BITS_DATA_OFFSET_DATA 32
#define XRTDS2GPU_CTRL_ADDR_DOORBELL_OFFSET_DATA 0x20
#define XRTDS2GPU_CTRL_BITS_DOORBELL_OFFSET_DATA 32
#define XRTDS2GPU_CTRL_ADDR_FRAME_SIZE_DATA 0x28
#define XRTDS2GPU_CTRL_BITS_FRAME_SIZE_DATA 32
#define XRTDS2GPU_CTRL_ADDR_STATUS_DATA 0x30
#define XRTDS2GPU_CTRL_BITS_STATUS_DATA 32
#define XRTDS2GPU_CTRL_ADDR_STATUS_CTRL 0x34

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/* AXI Stream interconnect related helper functions
*
* These functions present a simpler interface to Xilinx' AXI Stream switch driver (XAxis_Switch_*)
*
* Author: Steffen Vogel <post@steffenvogel.de>
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Steffen Vogel <post@steffenvogel.de>
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <map>
#include <xilinx/xaxis_switch.h>
#include <villas/fpga/node.hpp>
namespace villas {
namespace fpga {
namespace ip {
class AxiStreamSwitch : public Node {
public:
friend class AxiStreamSwitchFactory;
virtual bool init() override;
bool connectInternal(const std::string &slavePort,
const std::string &masterPort);
void printConfig() const;
private:
int portNameToNum(const std::string &portName);
static constexpr const char *PORT_DISABLED = "DISABLED";
static constexpr char registerMemory[] = "Reg";
std::list<MemoryBlockName> getMemoryBlocks() const {
return {registerMemory};
}
XAxis_Switch xSwitch;
XAxis_Switch_Config xConfig;
std::map<std::string, std::string> portMapping;
};
class AxiStreamSwitchFactory : NodeFactory {
public:
virtual std::string getName() const { return "switch"; }
virtual std::string getDescription() const {
return "Xilinx's AXI4-Stream switch";
}
private:
virtual Vlnv getCompatibleVlnv() const {
return Vlnv("xilinx.com:ip:axis_switch:");
}
// Create a concrete IP instance
Core *make() const { return new AxiStreamSwitch; };
protected:
virtual void parse(Core &, json_t *) override;
};
} // namespace ip
} // namespace fpga
} // namespace villas

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/* Timer related helper functions
*
* These functions present a simpler interface to Xilinx' Timer Counter driver (XTmrCtr_*)
*
* Author: Steffen Vogel <post@steffenvogel.de>
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Steffen Vogel <post@steffenvogel.de>
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <cstdint>
#include <xilinx/xtmrctr.h>
#include <villas/fpga/config.h>
#include <villas/fpga/core.hpp>
namespace villas {
namespace fpga {
namespace ip {
class Timer : public Core {
friend class TimerFactory;
public:
virtual
bool init() override;
bool start(uint32_t ticks);
bool wait();
uint32_t remaining();
inline
bool isRunning()
{
return remaining() != 0;
}
inline
bool isFinished()
{
return remaining() == 0;
}
static constexpr
uint32_t getFrequency()
{
return FPGA_AXI_HZ;
}
private:
std::list<MemoryBlockName> getMemoryBlocks() const
{
return {
registerMemory
};
}
static constexpr char irqName[] = "generateout0";
static constexpr char registerMemory[] = "Reg";
XTmrCtr xTmr;
};
} // namespace ip
} // namespace fpga
} // namespace villas

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/* Interlectual Property component.
*
* This class represents a module within the FPGA.
*
* Author: Steffen Vogel <post@steffenvogel.de>
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <map>
#include <string>
#include <jansson.h>
#include <fmt/ostream.h>
#include <villas/config.hpp>
#include <villas/fpga/core.hpp>
#include <villas/graph/directed.hpp>
namespace villas {
namespace fpga {
namespace ip {
class StreamVertex : public graph::Vertex {
public:
StreamVertex(const std::string &node, const std::string &port, bool isMaster) :
graph::Vertex(),
nodeName(node),
portName(port),
isMaster(isMaster)
{ }
std::string getName() const
{
return nodeName + "/" + portName + "(" + (isMaster ? "M" : "S") + ")";
}
friend
std::ostream& operator<< (std::ostream &stream, const StreamVertex &vertex)
{
return stream << vertex.getIdentifier() << ": " << vertex.getName();
}
public:
std::string nodeName;
std::string portName;
bool isMaster;
};
class StreamGraph : public graph::DirectedGraph<StreamVertex> {
public:
StreamGraph() :
graph::DirectedGraph<StreamVertex>("stream:graph")
{ }
std::shared_ptr<StreamVertex> getOrCreateStreamVertex(const std::string &node,
const std::string &port,
bool isMaster)
{
for (auto &vertexEntry : vertices) {
auto &vertex = vertexEntry.second;
if (vertex->nodeName == node and vertex->portName == port and vertex->isMaster == isMaster)
return vertex;
}
// Vertex not found, create new one
auto vertex = std::make_shared<StreamVertex>(node, port, isMaster);
addVertex(vertex);
return vertex;
}
};
class Node : public virtual Core {
public:
using Ptr = std::shared_ptr<Node>;
friend class NodeFactory;
const StreamVertex& getMasterPort(const std::string &name) const
{
return *portsMaster.at(name);
}
const std::map<std::string, std::shared_ptr<StreamVertex>> &getMasterPorts() const
{
return portsMaster;
}
const StreamVertex& getSlavePort(const std::string &name) const
{
return *portsSlave.at(name);
}
const std::map<std::string, std::shared_ptr<StreamVertex>> &getSlavePorts() const
{
return portsSlave;
}
bool connect(const StreamVertex &from, const StreamVertex &to);
bool connect(const StreamVertex &from, const StreamVertex &to, bool reverse)
{
bool ret;
ret = connect(from, to);
if (reverse)
ret &= connect(to, from);
return ret;
}
// Easy-usage assuming that the slave IP to connect to only has one slave
// port and implements the getDefaultSlavePort() function
bool connect(const Node &slaveNode, bool reverse = false)
{
return this->connect(this->getDefaultMasterPort(), slaveNode.getDefaultSlavePort(), reverse);
}
// Used by easy-usage connect, will throw if not implemented by derived node
virtual
const StreamVertex& getDefaultSlavePort() const;
// Used by easy-usage connect, will throw if not implemented by derived node
virtual
const StreamVertex& getDefaultMasterPort() const;
static
const StreamGraph& getGraph()
{
return streamGraph;
}
bool loopbackPossible() const;
bool connectLoopback();
protected:
virtual
bool connectInternal(const std::string &slavePort,
const std::string &masterPort);
private:
std::pair<std::string, std::string> getLoopbackPorts() const;
protected:
std::map<std::string, std::shared_ptr<StreamVertex>> portsMaster;
std::map<std::string, std::shared_ptr<StreamVertex>> portsSlave;
static
StreamGraph streamGraph;
};
class NodeFactory : public CoreFactory {
public:
using CoreFactory::CoreFactory;
virtual
void parse(Core &, json_t *);
};
template<typename T, const char *name, const char *desc, const char *vlnv>
class NodePlugin : public NodeFactory {
public:
virtual
std::string getName() const
{
return name;
}
virtual
std::string getDescription() const
{
return desc;
}
private:
// Get a VLNV identifier for which this IP / Node type can be used.
virtual
Vlnv getCompatibleVlnv() const
{
return Vlnv(vlnv);
}
// Create a concrete IP instance
Core* make() const
{
return new T;
}
};
} // namespace ip
} // namespace fpga
} // namespace villas
#ifndef FMT_LEGACY_OSTREAM_FORMATTER
template <>
class fmt::formatter<villas::fpga::ip::StreamVertex>
: public fmt::ostream_formatter {};
template <>
class fmt::formatter<villas::fpga::ip::Node>
: public fmt::ostream_formatter {};
#endif

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/* FPGA pciecard
*
* This class represents a FPGA device.
*
* Author: Steffen Vogel <post@steffenvogel.de>
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <list>
#include <set>
#include <string>
#include <jansson.h>
#include <filesystem>
#include <villas/plugin.hpp>
#include <villas/memory.hpp>
#include <villas/kernel/pci.hpp>
#include <villas/kernel/vfio_container.hpp>
#include <villas/fpga/card.hpp>
#include <villas/fpga/config.h>
#include <villas/fpga/core.hpp>
namespace villas {
namespace fpga {
// Forward declarations
struct vfio_container;
class PCIeCardFactory;
class PCIeCard : public Card {
public:
~PCIeCard();
bool init();
bool stop()
{
return true;
}
bool check()
{
return true;
}
bool reset()
{
// TODO: Try via sysfs?
// echo 1 > /sys/bus/pci/devices/0000\:88\:00.0/reset
return true;
}
void dump()
{ }
public: // TODO: make this private
bool doReset; // Reset VILLASfpga during startup?
int affinity; // Affinity for MSI interrupts
std::shared_ptr<kernel::pci::Device> pdev; // PCI device handle
protected:
Logger getLogger() const { return villas::logging.get(name); }
};
class PCIeCardFactory : public plugin::Plugin {
public:
static std::shared_ptr<PCIeCard>
make(json_t *json, std::string card_name,
std::shared_ptr<kernel::vfio::Container> vc,
const std::filesystem::path &searchPath);
static PCIeCard *make() { return new PCIeCard(); }
static Logger getStaticLogger() {
return villas::logging.get("pcie:card:factory");
}
virtual std::string getName() const { return "pcie"; }
virtual std::string getDescription() const {
return "Xilinx PCIe FPGA cards";
}
virtual std::string getType() const { return "card"; }
};
} // namespace fpga
} // namespace villas

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/* Helper function for directly using VILLASfpga outside of VILLASnode
* Author: Niklas Eiling <niklas.eiling@rwth-aachen.de>
* SPDX-FileCopyrightText: 2022-2023 Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <string>
#include <villas/fpga/ips/aurora_xilinx.hpp>
#include <villas/fpga/ips/dma.hpp>
#include <villas/fpga/pcie_card.hpp>
namespace villas {
namespace fpga {
std::shared_ptr<fpga::Card>
setupFpgaCard(const std::string &configFile, const std::string &fpgaName);
std::shared_ptr<fpga::Card>
createCard(json_t *config, const std::filesystem::path &searchPath,
std::shared_ptr<kernel::vfio::Container> vfioContainer,
std::string card_name = "anonymous Card");
int createCards(
json_t *config, std::list<std::shared_ptr<fpga::Card>> &cards,
const std::filesystem::path &searchPath,
std::shared_ptr<kernel::vfio::Container> vfioContainer = nullptr);
int createCards(
json_t *config, std::list<std::shared_ptr<fpga::Card>> &cards,
const std::string &searchPath,
std::shared_ptr<kernel::vfio::Container> vfioContainer = nullptr);
std::shared_ptr<std::vector<std::shared_ptr<fpga::ip::Node>>>
getAuroraChannels(std::shared_ptr<fpga::Card> card);
void setupColorHandling();
class ConnectString {
public:
enum class ConnectType { AURORA, DMA, DINO, LOOPBACK };
ConnectString(std::string &connectString, int maxPortNum = 7);
void parseString(std::string &connectString);
int portStringToInt(std::string &str) const;
void configCrossBar(std::shared_ptr<villas::fpga::Card> card) const;
bool isBidirectional() const { return bidirectional; };
bool isDmaLoopback() const { return srcType == ConnectType::LOOPBACK; };
bool isSrcStdin() const { return srcType == ConnectType::DMA; };
bool isDstStdout() const { return dstType == ConnectType::DMA; };
int getSrcAsInt() const { return srcAsInt; };
int getDstAsInt() const { return dstAsInt; };
static std::string connectTypeToString(ConnectType type) {
static const std::string connectTypeStrings[] = {"aurora", "dma", "dino",
"loopback"};
return connectTypeStrings[(int)type];
}
protected:
villas::Logger log;
int maxPortNum;
bool bidirectional;
bool invert;
ConnectType srcType;
ConnectType dstType;
int srcAsInt;
int dstAsInt;
};
class BufferedSampleFormatter {
public:
virtual void format(float value) = 0;
virtual void output(std::ostream &out) {
out << buf.data() << std::flush;
clearBuf();
}
virtual void clearBuf() {
for (size_t i = 0; i < bufSamples && buf[i * bufSampleSize] != '\0';
i++) {
buf[i * bufSampleSize] = '\0';
}
currentBufLoc = 0;
}
protected:
std::vector<char> buf;
const size_t bufSamples;
const size_t bufSampleSize;
size_t currentBufLoc;
BufferedSampleFormatter(const size_t bufSamples, const size_t bufSampleSize)
: buf(bufSamples * bufSampleSize + 1), // Leave room for a final `\0'
bufSamples(bufSamples), bufSampleSize(bufSampleSize),
currentBufLoc(0){};
BufferedSampleFormatter() = delete;
BufferedSampleFormatter(const BufferedSampleFormatter &) = delete;
virtual char *nextBufPos() {
return &buf[(currentBufLoc++) * bufSampleSize];
}
};
class BufferedSampleFormatterShort : public BufferedSampleFormatter {
public:
BufferedSampleFormatterShort(size_t bufSizeInSamples)
: BufferedSampleFormatter(bufSizeInSamples, formatStringSize){};
virtual void format(float value) override {
size_t chars;
if ((chars = std::snprintf(nextBufPos(), formatStringSize + 1,
formatString, value)) >
(int)formatStringSize) {
throw RuntimeError("Output buffer too small. Expected " +
std::to_string(formatStringSize) +
" characters, got " + std::to_string(chars));
}
}
protected:
static constexpr char formatString[] = "%013.6f\n";
static constexpr size_t formatStringSize = 14;
};
class BufferedSampleFormatterLong : public BufferedSampleFormatter {
public:
BufferedSampleFormatterLong(size_t bufSizeInSamples)
: BufferedSampleFormatter(bufSizeInSamples, formatStringSize),
sampleCnt(0){};
virtual void format(float value) override {
if (std::snprintf(nextBufPos(), formatStringSize + 1, formatString,
sampleCnt, value) > (int)formatStringSize) {
throw RuntimeError("Output buffer too small");
}
sampleCnt = (sampleCnt + 1) % 100000;
}
protected:
static constexpr char formatString[] = "%05zd: %013.6f\n";
static constexpr size_t formatStringSize = 22;
size_t sampleCnt;
};
std::unique_ptr<BufferedSampleFormatter>
getBufferedSampleFormatter(const std::string &format,
size_t bufSizeInSamples);
} // namespace fpga
} // namespace villas

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/* Vendor, Library, Name, Version (VLNV) tag.
*
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <string>
#include <sstream>
#include <iostream>
#include <fmt/ostream.h>
#include <villas/config.hpp>
namespace villas {
namespace fpga {
class Vlnv {
public:
static constexpr char delimiter = ':';
Vlnv() :
vendor(""),
library(""),
name(""),
version("")
{ }
Vlnv(const std::string &s)
{
parseFromString(s);
}
static Vlnv
getWildcard()
{
return Vlnv();
}
std::string
toString() const;
bool
operator==(const Vlnv &other) const;
bool
operator!=(const Vlnv &other) const
{
return !(*this == other);
}
friend std::ostream&
operator<< (std::ostream &stream, const Vlnv &vlnv)
{
return stream
<< (vlnv.vendor.empty() ? "*" : vlnv.vendor) << ":"
<< (vlnv.library.empty() ? "*" : vlnv.library) << ":"
<< (vlnv.name.empty() ? "*" : vlnv.name) << ":"
<< (vlnv.version.empty() ? "*" : vlnv.version);
}
private:
void
parseFromString(std::string vlnv);
std::string vendor;
std::string library;
std::string name;
std::string version;
};
} // namespace fpga
} // namespace villas
#ifndef FMT_LEGACY_OSTREAM_FORMATTER
template <>
class fmt::formatter<villas::fpga::Vlnv>
: public fmt::ostream_formatter {};
#endif

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## CMakeLists.txt
#
# Author: Daniel Krebs <github@daniel-krebs.net>
# SPDX-FileCopyrightText: 2018 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0
set(SOURCES
vlnv.cpp
card.cpp
pcie_card.cpp
core.cpp
node.cpp
utils.cpp
dma.cpp
ips/aurora_xilinx.cpp
ips/aurora.cpp
ips/bram.cpp
ips/dino.cpp
ips/dma.cpp
ips/emc.cpp
ips/fifo.cpp
ips/gpio.cpp
ips/intc.cpp
ips/pcie.cpp
ips/rtds.cpp
ips/switch.cpp
ips/timer.cpp
ips/i2c.cpp
ips/register.cpp
ips/rtds2gpu/rtds2gpu.cpp
ips/rtds2gpu/xrtds2gpu.c
ips/rtds2gpu/gpu2rtds.cpp
)
# we don't have much influence on drivers generated by Xilinx, so ignore warnings
set_source_files_properties(ips/rtds2gpu/xrtds2gpu.c
PROPERTIES COMPILE_FLAGS -Wno-int-to-pointer-cast)
add_library(villas-fpga SHARED ${SOURCES})
target_link_libraries(villas-fpga PUBLIC villas-common)
target_compile_definitions(villas-fpga PRIVATE
BUILDID=\"abc\"
_GNU_SOURCE
)
target_include_directories(villas-fpga
PUBLIC
${PROJECT_BINARY_DIR}/include
${PROJECT_SOURCE_DIR}/include
${JANSSON_INCLUDE_DIRS}
)
target_link_libraries(villas-fpga PUBLIC
${CMAKE_THREAD_LIBS_INIT}
${CMAKE_DL_LIBS}
m
xil
villas-common
"$<$<AND:$<CXX_COMPILER_ID:GNU>,$<VERSION_LESS:$<CXX_COMPILER_VERSION>,9.0>>:stdc++fs>"
)
if(CMAKE_CUDA_COMPILER)
target_link_libraries(villas-fpga PUBLIC villas-gpu)
endif()
include(GNUInstallDirs)
install(TARGETS villas-fpga
RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}
LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}
ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}/static
)
install(DIRECTORY ../include/villas DESTINATION include)

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/* FPGA card
*
* This class represents a FPGA device.
*
* Author: Steffen Vogel <post@steffenvogel.de>
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#include <villas/fpga/card.hpp>
using namespace villas;
using namespace villas::fpga;
Card::~Card()
{
for (auto ip = ips.rbegin(); ip != ips.rend(); ++ip){
(*ip)->stop();
}
// Ensure IP destructors are called before memory is unmapped
ips.clear();
auto &mm = MemoryManager::get();
// Unmap all memory blocks
for (auto &mappedMemoryBlock : memoryBlocksMapped) {
auto translation =
mm.getTranslation(addrSpaceIdDeviceToHost, mappedMemoryBlock.first);
const uintptr_t iova = translation.getLocalAddr(0);
const size_t size = translation.getSize();
logger->debug("Unmap block {} at IOVA {:#x} of size {:#x}",
mappedMemoryBlock.first, iova, size);
vfioContainer->memoryUnmap(iova, size);
}
}
std::shared_ptr<ip::Core> Card::lookupIp(const std::string &name) const
{
for(auto &ip : ips) {
if(*ip == name) {
return ip;
}
}
return nullptr;
}
std::shared_ptr<ip::Core> Card::lookupIp(const Vlnv &vlnv) const
{
for(auto &ip : ips) {
if(*ip == vlnv) {
return ip;
}
}
return nullptr;
}
std::shared_ptr<ip::Core> Card::lookupIp(const ip::IpIdentifier &id) const
{
for (auto &ip : ips) {
if (*ip == id) {
return ip;
}
}
return nullptr;
}
bool Card::unmapMemoryBlock(const MemoryBlock& block)
{
if (memoryBlocksMapped.find(block.getAddrSpaceId()) == memoryBlocksMapped.end()) {
throw std::runtime_error("Block " + std::to_string(block.getAddrSpaceId()) + " is not mapped but was requested to be unmapped.");
}
auto &mm = MemoryManager::get();
auto translation = mm.getTranslation(addrSpaceIdDeviceToHost, block.getAddrSpaceId());
const uintptr_t iova = translation.getLocalAddr(0);
const size_t size = translation.getSize();
logger->debug("Unmap block {} at IOVA {:#x} of size {:#x}",
block.getAddrSpaceId(), iova, size);
vfioContainer->memoryUnmap(iova, size);
memoryBlocksMapped.erase(block.getAddrSpaceId());
return true;
}
bool Card::mapMemoryBlock(const std::shared_ptr<MemoryBlock> block)
{
if (not vfioContainer->isIommuEnabled()) {
logger->warn("VFIO mapping not supported without IOMMU");
return false;
}
auto &mm = MemoryManager::get();
const auto &addrSpaceId = block->getAddrSpaceId();
if (memoryBlocksMapped.find(addrSpaceId) != memoryBlocksMapped.end())
// Block already mapped
return true;
else
logger->debug("Create VFIO mapping for {}", addrSpaceId);
auto translationFromProcess = mm.getTranslationFromProcess(addrSpaceId);
uintptr_t processBaseAddr = translationFromProcess.getLocalAddr(0);
uintptr_t iovaAddr = vfioContainer->memoryMap(processBaseAddr,
UINTPTR_MAX,
block->getSize());
if (iovaAddr == UINTPTR_MAX) {
logger->error("Cannot map memory at {:#x} of size {:#x}",
processBaseAddr, block->getSize());
return false;
}
mm.createMapping(iovaAddr, 0, block->getSize(),
"VFIO-D2H",
this->addrSpaceIdDeviceToHost,
addrSpaceId);
// Remember that this block has already been mapped for later
memoryBlocksMapped.insert({addrSpaceId, block});
return true;
}

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/* FPGA IP component.
*
* Author: Steffen Vogel <post@steffenvogel.de>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#include <memory>
#include <string>
#include <utility>
#include <villas/exceptions.hpp>
#include <villas/log.hpp>
#include <villas/memory.hpp>
#include <villas/utils.hpp>
#include <villas/fpga/card.hpp>
#include <villas/fpga/utils.hpp>
#include <villas/fpga/vlnv.hpp>
#include <villas/fpga/core.hpp>
#include <villas/fpga/ips/intc.hpp>
#include <villas/fpga/ips/pcie.hpp>
#include <villas/fpga/ips/switch.hpp>
using namespace villas::fpga;
using namespace villas::fpga::ip;
// Special IPs that have to be initialized first. Will be initialized in the
// same order as they appear in this list, i.e. first here will be initialized
// first.
static std::list<Vlnv> vlnvInitializationOrder = {
Vlnv("xilinx.com:ip:axi_pcie:"),
Vlnv("xilinx.com:module_ref:axi_pcie_intc:"),
Vlnv("xilinx.com:ip:axis_switch:"),
Vlnv("xilinx.com:ip:axi_iic:"),
};
std::list<std::shared_ptr<Core>> CoreFactory::make(Card *card,
json_t *json_ips) {
// We only have this logger until we know the factory to build an IP with
auto loggerStatic = getStaticLogger();
std::list<IpIdentifier> allIps; // All IPs available in config
std::list<IpIdentifier> orderedIps; // IPs ordered in initialization order
std::list<std::shared_ptr<Core>> configuredIps; // Successfully configured IPs
if (!card->ips.empty()) {
loggerStatic->error("IP list of card {} already contains IPs.", card->name);
throw RuntimeError("IP list of card {} already contains IPs.", card->name);
}
// Parse all IP instance names and their VLNV into list `allIps`
const char *ipName;
json_t *json_ip;
json_object_foreach(json_ips, ipName, json_ip) {
const char *vlnv;
json_error_t err;
int ret = json_unpack_ex(json_ip, &err, 0, "{ s: s }", "vlnv", &vlnv);
if (ret != 0)
throw ConfigError(json_ip, err, "", "IP {} has no VLNV", ipName);
allIps.push_back({vlnv, ipName});
}
// Pick out IPs to be initialized first.
//
// Reverse walktrough, because we push to the
// front of the output list, so that the first element will also be the
// first to be initialized.
for (auto viIt = vlnvInitializationOrder.rbegin();
viIt != vlnvInitializationOrder.rend(); ++viIt) {
// Iterate over IPs, if VLNV matches, push to front and remove from list
for (auto it = allIps.begin(); it != allIps.end(); ++it) {
if (*viIt == it->getVlnv()) {
orderedIps.push_front(*it);
it = allIps.erase(it);
}
}
}
// Insert all other IPs at the end
orderedIps.splice(orderedIps.end(), allIps);
loggerStatic->debug("IP initialization order:");
for (auto &id : orderedIps) {
loggerStatic->debug(" " CLR_BLD("{}"), id.getName());
}
// Configure all IPs
for (auto &id : orderedIps) {
loggerStatic->info("Configuring {}", id);
// Find the appropriate factory that can create the specified VLNV
// Note:
// This is the magic part! Factories automatically register as a
// plugin as soon as they are instantiated. If there are multiple
// candidates, the first suitable factory will be used.
auto *f = lookup(id.getVlnv());
if (f == nullptr) {
loggerStatic->warn("No plugin found to handle {}", id.getVlnv());
continue;
} else
loggerStatic->debug("Using {} for IP {}", f->getName(), id.getVlnv());
auto logger = f->getLogger();
// Create new IP instance. Since this function is virtual, it will
// construct the right, specialized type without knowing it here
// because we have already picked the right factory.
// If something goes wrong with initialization, the shared_ptr will
// take care to desctruct the Core again as it is not pushed to
// the list and will run out of scope.
auto ip = std::unique_ptr<Core>(f->make());
if (ip == nullptr) {
logger->warn("Cannot create an instance of {}", f->getName());
continue;
}
// Setup generic IP type properties
ip->card = card;
ip->id = id;
ip->logger = villas::logging.get(id.getName());
json_t *json_ip = json_object_get(json_ips, id.getName().c_str());
json_t *json_irqs = json_object_get(json_ip, "irqs");
if (json_is_object(json_irqs)) {
logger->debug("Parse IRQs of {}", *ip);
const char *irqName;
json_t *json_irq;
json_object_foreach(json_irqs, irqName, json_irq) {
const char *irqEntry = json_string_value(json_irq);
auto tokens = utils::tokenize(irqEntry, ":");
if (tokens.size() != 2) {
logger->warn("Cannot parse IRQ '{}' of " CLR_BLD("{}"), irqEntry,
id.getName());
continue;
}
const std::string &irqControllerName = tokens[0];
InterruptController *intc = nullptr;
for (auto &configuredIp : configuredIps) {
if (*configuredIp == irqControllerName) {
intc = dynamic_cast<InterruptController *>(configuredIp.get());
break;
}
}
if (intc == nullptr) {
logger->error("Interrupt Controller {} for IRQ {} not found",
irqControllerName, irqName);
continue;
}
int num;
try {
num = std::stoi(tokens[1]);
} catch (const std::invalid_argument &) {
logger->warn("IRQ number is not an integer: '{}'", irqEntry);
continue;
}
logger->debug("IRQ: {} -> {}:{}", irqName, irqControllerName, num);
ip->irqs[irqName] = {num, intc, ""};
}
}
json_t *json_memory_view = json_object_get(json_ip, "memory-view");
if (json_is_object(json_memory_view)) {
logger->debug("Parse memory view of {}", *ip);
// Now find all slave address spaces this master can access
const char *bus_name;
json_t *json_bus;
json_object_foreach(json_memory_view, bus_name, json_bus) {
// This IP has a memory view => it is a bus master somewhere
// Assemble name for master address space
const std::string myAddrSpaceName =
MemoryManager::getMasterAddrSpaceName(ip->getInstanceName(),
bus_name);
// Create a master address space
const MemoryManager::AddressSpaceId myAddrSpaceId =
MemoryManager::get().getOrCreateAddressSpace(myAddrSpaceName);
ip->busMasterInterfaces[bus_name] = myAddrSpaceId;
const char *instance_name;
json_t *json_instance;
json_object_foreach(json_bus, instance_name, json_instance) {
const char *block_name;
json_t *json_block;
json_object_foreach(json_instance, block_name, json_block) {
json_int_t base, high, size;
json_error_t err;
int ret = json_unpack_ex(json_block, &err, 0,
"{ s: I, s: I, s: I }", "baseaddr", &base,
"highaddr", &high, "size", &size);
if (ret != 0)
throw ConfigError(
json_block, err, "", "Cannot parse address block {}/{}/{}/{}",
ip->getInstanceName(), bus_name, instance_name, block_name);
// Get or create the slave address space
const std::string slaveAddrSpace =
MemoryManager::getSlaveAddrSpaceName(instance_name, block_name);
const MemoryManager::AddressSpaceId slaveAddrSpaceId =
MemoryManager::get().getOrCreateAddressSpace(slaveAddrSpace);
// Create a new mapping to the slave address space
MemoryManager::get().createMapping(
static_cast<uintptr_t>(base), 0, static_cast<uintptr_t>(size),
bus_name, myAddrSpaceId, slaveAddrSpaceId);
}
}
}
}
// IP-specific setup via JSON config
f->parse(*ip, json_ip);
// Set polling mode
f->configurePollingMode(
*ip, (card->polling ? PollingMode::POLL : PollingMode::IRQ));
// IP has been configured now
configuredIps.push_back(std::move(ip));
}
// Start and check IPs now
for (auto &ip : configuredIps) {
loggerStatic->info("Initializing {}", *ip);
// Translate all memory blocks that the IP needs to be accessible from
// the process and cache in the instance, so this has not to be done at
// runtime.
for (auto &memoryBlock : ip->getMemoryBlocks()) {
// Construct the global name of this address block
const auto addrSpaceName = MemoryManager::getSlaveAddrSpaceName(
ip->getInstanceName(), memoryBlock);
// Retrieve its address space identifier
const auto addrSpaceId =
MemoryManager::get().findAddressSpace(addrSpaceName);
// ... and save it in IP
ip->slaveAddressSpaces.emplace(memoryBlock, addrSpaceId);
// Get the translation to the address space
const auto &translation =
MemoryManager::get().getTranslationFromProcess(addrSpaceId);
// Cache it in the IP instance only with local name
ip->addressTranslations.emplace(memoryBlock, translation);
}
if (not ip->init()) {
throw RuntimeError("Failed to initialize IP {}", *ip);
}
if (not ip->check()) {
throw RuntimeError("Failed to check IP {}", *ip);
}
// Will only be reached if the IP successfully was initialized
card->ips.push_back(std::move(ip));
}
loggerStatic->debug("Initialized IPs:");
for (auto &ip : card->ips) {
loggerStatic->debug(" {}", *ip);
}
return card->ips;
}
void Core::dump() {
logger->info("IP: {}", *this);
for (auto &[num, irq] : irqs) {
logger->info(" IRQ {}: {}:{}", num, irq.irqController->getInstanceName(),
irq.num);
}
for (auto &[block, translation] : addressTranslations) {
logger->info(" Memory {}: {}", block, translation);
}
}
CoreFactory *CoreFactory::lookup(const Vlnv &vlnv) {
for (auto &ip : plugin::registry->lookup<CoreFactory>()) {
if (ip->getCompatibleVlnv() == vlnv)
return ip;
}
return nullptr;
}
uintptr_t Core::getLocalAddr(const MemoryBlockName &block,
uintptr_t address) const {
// Throws exception if block not present
auto &translation = addressTranslations.at(block);
return translation.getLocalAddr(address);
}
InterruptController *
Core::getInterruptController(const std::string &interruptName) const {
try {
const IrqPort irq = irqs.at(interruptName);
return irq.irqController;
} catch (const std::out_of_range &) {
return nullptr;
}
}

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/* API for interacting with the FPGA DMA Controller.
*
* Author: Niklas Eiling <niklas.eiling@rwth-aachen.de>
* SPDX-FileCopyrightText: 2023 Niklas Eiling <niklas.eiling@rwth-aachen.de>
* SPDX-License-Identifier: Apache-2.0
*/
#include <villas/fpga/dma.h>
#include <csignal>
#include <iostream>
#include <string>
#include <stdexcept>
#include <villas/exceptions.hpp>
#include <villas/log.hpp>
#include <villas/utils.hpp>
#include <villas/fpga/core.hpp>
#include <villas/fpga/card.hpp>
#include <villas/fpga/vlnv.hpp>
#include <villas/fpga/ips/dma.hpp>
#include <villas/fpga/utils.hpp>
using namespace villas;
static std::shared_ptr<kernel::pci::DeviceList> pciDevices;
static auto logger = villas::logging.get("villasfpga_dma");
struct villasfpga_handle_t {
std::shared_ptr<villas::fpga::Card> card;
std::shared_ptr<villas::fpga::ip::Dma> dma;
};
struct villasfpga_memory_t {
std::shared_ptr<villas::MemoryBlock> block;
};
villasfpga_handle villasfpga_init(const char *configFile)
{
std::string fpgaName = "vc707";
std::string connectStr = "3<->pipe";
std::string outputFormat = "short";
bool dumpGraph = false;
bool dumpAuroraChannels = true;
try {
// Logging setup
logging.setLevel(spdlog::level::debug);
fpga::setupColorHandling();
if (configFile == nullptr || configFile[0] == '\0') {
logger->error(
"No configuration file provided/ Please use -c/--config argument");
return nullptr;
}
auto handle = new villasfpga_handle_t;
handle->card = fpga::setupFpgaCard(configFile, fpgaName);
if (dumpGraph) {
auto &mm = MemoryManager::get();
mm.getGraph().dump("graph.dot");
}
if (dumpAuroraChannels) {
auto aurora_channels = getAuroraChannels(handle->card);
for (auto aurora : *aurora_channels)
aurora->dump();
}
// Configure Crossbar switch
const fpga::ConnectString parsedConnectString(connectStr);
parsedConnectString.configCrossBar(handle->card);
return handle;
} catch (const RuntimeError &e) {
logger->error("Error: {}", e.what());
return nullptr;
} catch (const std::exception &e) {
logger->error("Error: {}", e.what());
return nullptr;
} catch (...) {
logger->error("Unknown error");
return nullptr;
}
}
void villasfpga_destroy(villasfpga_handle handle)
{
delete handle;
}
int villasfpga_alloc(villasfpga_handle handle, villasfpga_memory *mem, size_t size)
{
try {
auto &alloc = villas::HostRam::getAllocator();
*mem = new villasfpga_memory_t;
(*mem)->block = alloc.allocateBlock(size);
return villasfpga_register(handle, mem);
} catch (const RuntimeError &e) {
logger->error("Failed to allocate memory: {}", e.what());
return -1;
}
}
int villasfpga_register(villasfpga_handle handle, villasfpga_memory *mem)
{
try {
handle->dma->makeAccesibleFromVA((*mem)->block);
return 0;
} catch (const RuntimeError &e) {
logger->error("Failed to register memory: {}", e.what());
return -1;
}
}
int villasfpga_free(villasfpga_memory mem)
{
try {
delete mem;
return 0;
} catch (const RuntimeError &e) {
logger->error("Failed to free memory: {}", e.what());
return -1;
}
}
int villasfpga_read(villasfpga_handle handle, villasfpga_memory mem, size_t size)
{
try {
if (!handle->dma->read(*mem->block, size)) {
logger->error("Failed to read from device");
return -1;
}
return 0;
} catch (const RuntimeError &e) {
logger->error("Failed to read memory: {}", e.what());
return -1;
}
}
int villasfpga_read_complete(villasfpga_handle handle, size_t *size)
{
try {
auto readComp = handle->dma->readComplete();
logger->debug("Read {} bytes", readComp.bytes);
*size = readComp.bytes;
return 0;
} catch (const RuntimeError &e) {
logger->error("Failed to read memory: {}", e.what());
return -1;
}
}
int villasfpga_write(villasfpga_handle handle, villasfpga_memory mem, size_t size)
{
try {
if (!handle->dma->write(*mem->block, size)) {
logger->error("Failed to write to device");
return -1;
}
return 0;
} catch (const RuntimeError &e) {
logger->error("Failed to write memory: {}", e.what());
return -1;
}
}
int villasfpga_write_complete(villasfpga_handle handle, size_t *size)
{
try {
auto writeComp = handle->dma->writeComplete();
logger->debug("Wrote {} bytes", writeComp.bytes);
*size = writeComp.bytes;
return 0;
} catch (const RuntimeError &e) {
logger->error("Failed to write memory: {}", e.what());
return -1;
}
}
void* villasfpga_get_ptr(villasfpga_memory mem)
{
return (void*)MemoryManager::get().getTranslationFromProcess(mem->block->getAddrSpaceId()).getLocalAddr(0);
}

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/* Driver for wrapper around Aurora (acs.eonerc.rwth-aachen.de:user:aurora)
*
* Author: Hatim Kanchwala <hatim@hatimak.me>
* SPDX-FileCopyrightText: 2020 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#include <cstdint>
#include <villas/utils.hpp>
#include <villas/fpga/ips/aurora.hpp>
// Register offsets
#define AURORA_AXIS_SR_OFFSET 0x00 // Status Register (read-only)
#define AURORA_AXIS_CR_OFFSET 0x04 // Control Register (read/write)
#define AURORA_AXIS_CNTR_IN_HIGH_OFFSET 0x0C // Higher 32-bits of incoming frame counter
#define AURORA_AXIS_CNTR_IN_LOW_OFFSET 0x08 // Lower 32-bits of incoming frame counter
#define AURORA_AXIS_CNTR_OUT_HIGH_OFFSET 0x18 // Higher 32-bits of outgoing frame counter
#define AURORA_AXIS_CNTR_OUT_LOW_OFFSET 0x1C // Lower 32-bits of outgoing frame counter
// Status register bits
#define AURORA_AXIS_SR_CHAN_UP (1 << 0) // 1-bit, asserted when channel initialisation is complete and is ready for data transfer
#define AURORA_AXIS_SR_LANE_UP (1 << 1) // 1-bit, asserted for each lane upon successful lane initialisation
#define AURORA_AXIS_SR_HARD_ERR (1 << 2) // 1-bit hard rror status
#define AURORA_AXIS_SR_SOFT_ERR (1 << 3) // 1-bit soft error status
#define AURORA_AXIS_SR_FRAME_ERR (1 << 4) // 1-bit frame error status
// Control register bits
// 1-bit, assert to put Aurora IP in loopback mode.
#define AURORA_AXIS_CR_LOOPBACK (1 << 0)
// 1-bit, assert to reset counters, incoming and outgoing frame counters.
#define AURORA_AXIS_CR_RST_CTRS (1 << 1)
// 1-bit, assert to turn off any sequence number handling by Aurora IP
// Sequence number must be handled in software then.
#define AURORA_AXIS_CR_SEQ_MODE (1 << 2)
/* 1-bit, assert to strip the received frame of the trailing sequence
* number. Sequence number mode must be set to handled by Aurora IP,
* otherwise this bit is ignored. */
#define AURORA_AXIS_CR_SEQ_STRIP (1 << 3)
/* 1-bit, assert to use the same sequence number in the outgoing
* NovaCor-bound frames as the sequence number received from the
* incoming frames from NovaCor. Sequence number mode must be set to
* handled by Aurora IP, otherwise this bit is ignored.*/
#define AURORA_AXIS_CR_SEQ_ECHO (1 << 4)
using namespace villas::fpga::ip;
void Aurora::dump()
{
// Check Aurora AXI4 registers
const uint32_t sr = readMemory<uint32_t>(registerMemory, AURORA_AXIS_SR_OFFSET);
logger->info("Aurora-NovaCor AXI-Stream interface details:");
logger->info("Aurora status: {:#x}", sr);
logger->info(" Channel up: {}", sr & AURORA_AXIS_SR_CHAN_UP ? CLR_GRN("yes") : CLR_RED("no"));
logger->info(" Lane up: {}", sr & AURORA_AXIS_SR_LANE_UP ? CLR_GRN("yes") : CLR_RED("no"));
logger->info(" Hard error: {}", sr & AURORA_AXIS_SR_HARD_ERR ? CLR_RED("yes") : CLR_GRN("no"));
logger->info(" Soft error: {}", sr & AURORA_AXIS_SR_SOFT_ERR ? CLR_RED("yes") : CLR_GRN("no"));
logger->info(" Frame error: {}", sr & AURORA_AXIS_SR_FRAME_ERR ? CLR_RED("yes") : CLR_GRN("no"));
const uint64_t inCntLow = readMemory<uint32_t>(registerMemory, AURORA_AXIS_CNTR_IN_LOW_OFFSET);
const uint64_t inCntHigh = readMemory<uint32_t>(registerMemory, AURORA_AXIS_CNTR_IN_HIGH_OFFSET);
const uint64_t inCnt = (inCntHigh << 32) | inCntLow;
const uint64_t outCntLow = readMemory<uint32_t>(registerMemory, AURORA_AXIS_CNTR_OUT_LOW_OFFSET);
const uint64_t outCntHigh = readMemory<uint32_t>(registerMemory, AURORA_AXIS_CNTR_OUT_HIGH_OFFSET);
const uint64_t outCnt = (outCntHigh << 32) | outCntLow;
logger->info("Aurora frames received: {}", inCnt);
logger->info("Aurora frames sent: {}", outCnt);
}
void Aurora::setLoopback(bool state)
{
auto cr = readMemory<uint32_t>(registerMemory, AURORA_AXIS_CR_OFFSET);
if (state)
cr |= AURORA_AXIS_CR_LOOPBACK;
else
cr &= ~AURORA_AXIS_CR_LOOPBACK;
writeMemory<uint32_t>(registerMemory, AURORA_AXIS_CR_OFFSET, cr);
}
void Aurora::resetFrameCounters()
{
auto cr = readMemory<uint32_t>(registerMemory, AURORA_AXIS_CR_OFFSET);
cr |= AURORA_AXIS_CR_RST_CTRS;
writeMemory<uint32_t>(registerMemory, AURORA_AXIS_CR_OFFSET, cr);
}
static char n[] = "aurora";
static char d[] = "Aurora 8B/10B and additional support modules, like an AXI4-Lite register interface.";
static char v[] = "acs.eonerc.rwth-aachen.de:user:aurora_axis:";
static NodePlugin<Aurora, n, d, v> f;

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/* Driver for wrapper around standard Xilinx Aurora (xilinx.com:ip:aurora_8b10b)
*
* Author: Steffen Vogel <post@steffenvogel.de>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#include <cstdint>
#include <villas/utils.hpp>
#include <villas/fpga/ips/aurora_xilinx.hpp>
using namespace villas::fpga::ip;
static char n[] = "aurora_xilinx";
static char d[] = "Xilinx Aurora 8B/10B.";
static char v[] = "xilinx.com:ip:aurora_8b10b:";
static NodePlugin<AuroraXilinx, n, d, v> f;

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/* Block RAM IP.
*
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#include <villas/exceptions.hpp>
#include <villas/fpga/ips/bram.hpp>
using namespace villas;
using namespace villas::fpga::ip;
void BramFactory::parse(Core &ip, json_t* cfg)
{
CoreFactory::parse(ip, cfg);
auto &bram = dynamic_cast<Bram&>(ip);
json_error_t err;
int ret = json_unpack_ex(cfg, &err, 0, "{ s: i }",
"size", &bram.size
);
if (ret != 0)
throw ConfigError(cfg, err, "", "Cannot parse BRAM config");
}
bool Bram::init()
{
allocator = std::make_unique<LinearAllocator>
(getAddressSpaceId(memoryBlock), this->size, 0);
return true;
}
static BramFactory f;

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/* Driver for wrapper around standard Xilinx Aurora (xilinx.com:ip:aurora_8b10b)
*
* Author: Steffen Vogel <post@steffenvogel.de>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#include <cstdint>
#include <villas/utils.hpp>
#include <villas/fpga/card.hpp>
#include <villas/fpga/ips/dino.hpp>
using namespace villas::fpga::ip;
Dino::Dino() : Node(), i2cdev(nullptr), i2c_channel(0), configDone(false) {}
Dino::~Dino() {}
bool Dino::init() {
if (!configDone) {
logger->error("Dino configuration not done yet");
throw RuntimeError("Dino configuration not done yet");
}
if (i2cdev == nullptr) {
i2cdev = std::dynamic_pointer_cast<fpga::ip::I2c>(
card->lookupIp(fpga::Vlnv("xilinx.com:ip:axi_iic:")));
if (i2cdev == nullptr) {
logger->error("No I2C found on FPGA");
throw RuntimeError(
"Dino requires and I2C device but none was found on FPGA");
} else {
logger->debug("Found I2C on FPGA");
}
}
configureHardware();
return true;
}
void Dino::setIoextDir(IoextPorts ports) {
if (i2cdev == nullptr) {
throw RuntimeError("I2C device not set");
}
std::vector<u8> data = {I2C_IOEXT_REG_DIR, ports.raw};
i2cdev->write(I2C_IOEXT_ADDR, data);
}
void Dino::setIoextOut(IoextPorts ports) {
if (i2cdev == nullptr) {
throw RuntimeError("I2C device not set");
}
std::vector<u8> data = {I2C_IOEXT_REG_OUT, ports.raw};
i2cdev->write(I2C_IOEXT_ADDR, data);
}
Dino::IoextPorts Dino::getIoextDir() {
if (i2cdev == nullptr) {
throw RuntimeError("I2C device not set");
}
std::vector<u8> data;
i2cdev->readRegister(I2C_IOEXT_ADDR, I2C_IOEXT_REG_DIR, data, 1);
IoextPorts ports;
ports.raw = data[0];
return ports;
}
Dino::IoextPorts Dino::getIoextDirectionRegister() {
if (i2cdev == nullptr) {
throw RuntimeError("I2C device not set");
}
i2cdev->getSwitch().setAndLockChannel(i2c_channel);
auto ret = getIoextDir();
i2cdev->getSwitch().unlockChannel();
return ret;
}
Dino::IoextPorts Dino::getIoextOut() {
if (i2cdev == nullptr) {
throw RuntimeError("I2C device not set");
}
std::vector<u8> data;
i2cdev->readRegister(I2C_IOEXT_ADDR, I2C_IOEXT_REG_OUT, data, 1);
IoextPorts ports;
ports.raw = data[0];
return ports;
}
Dino::IoextPorts Dino::getIoextOutputRegister() {
if (i2cdev == nullptr) {
throw RuntimeError("I2C device not set");
}
i2cdev->getSwitch().setAndLockChannel(i2c_channel);
auto ret = getIoextOut();
i2cdev->getSwitch().unlockChannel();
return ret;
}
DinoAdc::DinoAdc() : Dino() {}
DinoAdc::~DinoAdc() {}
void DinoAdc::configureHardware() {
if (!configDone) {
logger->error("ADC configuration not done yet");
throw RuntimeError("ADC configuration not done yet");
}
if (i2cdev == nullptr) {
throw RuntimeError("I2C device not set");
}
i2cdev->getSwitch().setAndLockChannel(i2c_channel);
IoextPorts ioext = {.raw = 0};
ioext.fields.sat_detect = true;
setIoextDir(ioext);
auto readback = getIoextDir();
if (readback.raw != ioext.raw) {
logger->error("Ioext direction register readback incorrect: {:#x} != {:#x}",
readback.raw, ioext.raw);
throw RuntimeError("Failed to set IOEXT direction register");
}
logger->debug("ADC Ioext: Direction register configured to {}", readback);
ioext.raw = 0;
ioext.fields.data_dir = true;
ioext.fields.status_led = true;
ioext.fields.n_we = true;
ioext.fields.input_zero = true;
setIoextOut(ioext);
ioext.fields.n_we = false;
setIoextOut(ioext);
readback = getIoextOut();
if (readback.raw != ioext.raw) {
logger->error("Ioext output register readback incorrect: {:#x} != {:#x}",
readback.raw, ioext.raw);
throw RuntimeError("Failed to set IOEXT output register");
}
i2cdev->getSwitch().unlockChannel();
logger->debug("ADC Ioext: Output register configured to {}", readback);
}
DinoDac::DinoDac() : Dino() {}
DinoDac::~DinoDac() {}
void DinoDac::configureHardware() {
if (!configDone) {
logger->error("DAC configuration not done yet");
throw RuntimeError("DAC configuration not done yet");
}
if (i2cdev == nullptr) {
throw RuntimeError("I2C device not set");
}
i2cdev->getSwitch().setAndLockChannel(i2c_channel);
IoextPorts ioext = {.raw = 0};
setIoextDir(ioext);
auto readback = getIoextDir();
if (readback.raw != ioext.raw) {
logger->error("Ioext direction register readback incorrect: {:#x} != {:#x}",
readback.raw, ioext.raw);
throw RuntimeError("Failed to set IOEXT direction register");
}
logger->debug("DAC Ioext: Direction register configured to {}", readback);
ioext.fields.status_led = true;
// Default gain is 1. Although not really necessary, let's be explicit here
ioext.fields.gain_lsb = Gain::GAIN_1 & 0x1;
ioext.fields.gain_msb = Gain::GAIN_1 & 0x2;
setIoextOut(ioext);
readback = getIoextOut();
if (readback.raw != ioext.raw) {
logger->error("Ioext output register readback incorrect: {:#x} != {:#x}",
readback.raw, ioext.raw);
throw RuntimeError("Failed to set IOEXT output register");
}
i2cdev->getSwitch().unlockChannel();
logger->debug("DAC Ioext: Output register configured to {}", readback);
}
void DinoDac::setGain(Gain gain) {
if (i2cdev == nullptr) {
throw RuntimeError("I2C device not set");
}
i2cdev->getSwitch().setAndLockChannel(i2c_channel);
IoextPorts ioext = getIoextOut();
ioext.fields.gain_lsb = gain & 0x1;
ioext.fields.gain_msb = gain & 0x2;
setIoextOut(ioext);
i2cdev->getSwitch().unlockChannel();
}
Dino::Gain DinoDac::getGain() {
if (i2cdev == nullptr) {
throw RuntimeError("I2C device not set");
}
i2cdev->getSwitch().setAndLockChannel(i2c_channel);
IoextPorts ioext = getIoextOut();
auto ret =
static_cast<Gain>((ioext.fields.gain_msb << 1) | ioext.fields.gain_lsb);
i2cdev->getSwitch().unlockChannel();
return ret;
}
void DinoFactory::parse(Core &ip, json_t *cfg) {
NodeFactory::parse(ip, cfg);
auto &dino = dynamic_cast<Dino &>(ip);
json_error_t err;
int i2c_channel;
int ret =
json_unpack_ex(cfg, &err, 0, "{ s: i }", "i2c_channel", &i2c_channel);
if (ret != 0) {
throw ConfigError(cfg, err, "", "Failed to parse Dino configuration");
}
if (i2c_channel < 0 || i2c_channel >= 8) {
throw ConfigError(cfg, err, "", "Invalid I2C channel");
}
dino.i2c_channel = static_cast<uint8_t>(i2c_channel);
dino.configDone = true;
}
static DinoAdcFactory fAdc;
static DinoDacFactory fDac;

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/* DMA driver
*
* Author: Daniel Krebs <github@daniel-krebs.net>
* Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
* SPDX-FileCopyrightText: 2018 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#include <sstream>
#include <string>
#include <xilinx/xaxidma.h>
#include <villas/memory.hpp>
#include <villas/fpga/card.hpp>
#include <villas/fpga/ips/dma.hpp>
#include <villas/fpga/ips/intc.hpp>
// Max. size of a DMA transfer in simple mode
#define FPGA_DMA_BOUNDARY 0x1000
using namespace villas::fpga::ip;
bool Dma::init() {
// Check if configJson has been called
if (!configDone)
throw RuntimeError("DMA device not configured");
if (hasScatterGather())
logger->info("Scatter-Gather support: {}", hasScatterGather());
xConfig.BaseAddr = getBaseAddr(registerMemory);
hwLock.lock();
if (XAxiDma_CfgInitialize(&xDma, &xConfig) != XST_SUCCESS) {
logger->error("Cannot initialize Xilinx DMA driver");
return false;
}
if (XAxiDma_Selftest(&xDma) != XST_SUCCESS) {
logger->error("DMA selftest failed");
return false;
} else {
logger->debug("DMA selftest passed");
}
hwLock.unlock();
// Map buffer descriptors
if (hasScatterGather()) {
if (actualRingBdSize < 2 * readCoalesce ||
actualRingBdSize < 2 * writeCoalesce) {
throw RuntimeError(
"Ring buffer size is too small for coalesce value {} < 2*{}",
actualRingBdSize, std::max(readCoalesce, writeCoalesce));
}
setupScatterGather();
}
irqs[mm2sInterrupt].irqController->enableInterrupt(irqs[mm2sInterrupt],
polling);
irqs[s2mmInterrupt].irqController->enableInterrupt(irqs[s2mmInterrupt],
polling);
return true;
}
void Dma::setupScatterGather() {
setupScatterGatherRingRx();
setupScatterGatherRingTx();
}
void Dma::setupScatterGatherRingRx() {
int ret;
hwLock.lock();
auto *rxRingPtr = XAxiDma_GetRxRing(&xDma);
// Disable all RX interrupts before RxBD space setup
XAxiDma_BdRingIntDisable(rxRingPtr, XAXIDMA_IRQ_ALL_MASK);
// Set delay and coalescing
XAxiDma_BdRingSetCoalesce(rxRingPtr, readCoalesce, delay);
// Allocate and map space for BD ring in host RAM
auto &alloc = villas::HostRam::getAllocator();
sgRingRx = alloc.allocateBlock(requestedRingBdSizeMemory);
if (not card->mapMemoryBlock(sgRingRx))
throw RuntimeError("Memory not accessible by DMA");
auto &mm = MemoryManager::get();
auto trans = mm.getTranslation(busMasterInterfaces[sgInterface],
sgRingRx->getAddrSpaceId());
auto physAddr = reinterpret_cast<uintptr_t>(trans.getLocalAddr(0));
auto virtAddr = reinterpret_cast<uintptr_t>(
mm.getTranslationFromProcess(sgRingRx->getAddrSpaceId()).getLocalAddr(0));
// Setup Rx BD space
ret = XAxiDma_BdRingCreate(rxRingPtr, physAddr, virtAddr,
XAXIDMA_BD_MINIMUM_ALIGNMENT, actualRingBdSize);
if (ret != XST_SUCCESS)
throw RuntimeError("Failed to create RX ring: {}", ret);
// Setup an all-zero BD as the template for the Rx channel.
XAxiDma_Bd bdTemplate;
XAxiDma_BdClear(&bdTemplate);
ret = XAxiDma_BdRingClone(rxRingPtr, &bdTemplate);
if (ret != XST_SUCCESS)
throw RuntimeError("Failed to clone BD template: {}", ret);
// Enable completion interrupt
XAxiDma_IntrEnable(&xDma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
// Start the RX channel
ret = XAxiDma_BdRingStart(rxRingPtr);
if (ret != XST_SUCCESS)
throw RuntimeError("Failed to start TX ring: {}", ret);
hwLock.unlock();
}
void Dma::setupScatterGatherRingTx() {
int ret;
hwLock.lock();
auto *txRingPtr = XAxiDma_GetTxRing(&xDma);
// Disable all TX interrupts before TxBD space setup
XAxiDma_BdRingIntDisable(txRingPtr, XAXIDMA_IRQ_ALL_MASK);
// Set TX delay and coalesce
XAxiDma_BdRingSetCoalesce(txRingPtr, writeCoalesce, delay);
// Allocate and map space for BD ring in host RAM
auto &alloc = villas::HostRam::getAllocator();
sgRingTx = alloc.allocateBlock(requestedRingBdSizeMemory);
if (not card->mapMemoryBlock(sgRingTx))
throw RuntimeError("Memory not accessible by DMA");
auto &mm = MemoryManager::get();
auto trans = mm.getTranslation(busMasterInterfaces[sgInterface],
sgRingTx->getAddrSpaceId());
auto physAddr = reinterpret_cast<uintptr_t>(trans.getLocalAddr(0));
auto virtAddr = reinterpret_cast<uintptr_t>(
mm.getTranslationFromProcess(sgRingTx->getAddrSpaceId()).getLocalAddr(0));
// Setup TxBD space
ret = XAxiDma_BdRingCreate(txRingPtr, physAddr, virtAddr,
XAXIDMA_BD_MINIMUM_ALIGNMENT, actualRingBdSize);
if (ret != XST_SUCCESS)
throw RuntimeError("Failed to create TX BD ring: {}", ret);
// We create an all-zero BD as the template.
XAxiDma_Bd BdTemplate;
XAxiDma_BdClear(&BdTemplate);
ret = XAxiDma_BdRingClone(txRingPtr, &BdTemplate);
if (ret != XST_SUCCESS)
throw RuntimeError("Failed to clone TX ring BD: {}", ret);
// Enable completion interrupt
XAxiDma_IntrEnable(&xDma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
// Start the TX channel
ret = XAxiDma_BdRingStart(txRingPtr);
if (ret != XST_SUCCESS)
throw RuntimeError("Failed to start TX ring: {}", ret);
hwLock.unlock();
}
bool Dma::reset() {
if (xDma.RegBase == 0) {
return true;
}
hwLock.lock();
XAxiDma_IntrDisable(&xDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DMA_TO_DEVICE);
XAxiDma_IntrDisable(&xDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DEVICE_TO_DMA);
XAxiDma_Reset(&xDma);
// Value taken from libxil implementation
int timeout = 500;
while (timeout > 0) {
if (XAxiDma_ResetIsDone(&xDma)) {
logger->info("DMA has been reset.");
return true;
}
timeout--;
}
hwLock.unlock();
logger->error("DMA reset timed out");
return false;
}
Dma::~Dma() {
// Unmap memory in our ownership, MemoryBlock gets deleted and removed from
// graph by this destructor as well.
if (hasScatterGather()) {
// Fix memory leak in upstream Xilinx code
auto txRingPtr = XAxiDma_GetTxRing(&xDma);
auto rxRingPtr = XAxiDma_GetRxRing(&xDma);
if (txRingPtr) {
free(txRingPtr->CyclicBd);
txRingPtr->CyclicBd = nullptr;
}
if (rxRingPtr) {
free(rxRingPtr->CyclicBd);
rxRingPtr->CyclicBd = nullptr;
}
// unampe SG memory Blocks
if (sgRingTx) {
card->unmapMemoryBlock(*sgRingTx);
}
if (sgRingRx) {
card->unmapMemoryBlock(*sgRingRx);
}
}
Dma::reset();
}
bool Dma::memcpy(const MemoryBlock &src, const MemoryBlock &dst, size_t len) {
if (len == 0)
return true;
if (not connectLoopback())
return false;
if (this->read(dst, len) == 0)
return false;
if (this->write(src, len) == 0)
return false;
if (not this->writeComplete().bds)
return false;
if (not this->readComplete().bds)
return false;
return true;
}
bool Dma::write(const MemoryBlock &mem, size_t len) {
if (len == 0)
return true;
if (len > FPGA_DMA_BOUNDARY)
return false;
auto &mm = MemoryManager::get();
// User has to make sure that memory is accessible, otherwise this will throw
auto trans = mm.getTranslation(busMasterInterfaces[mm2sInterface],
mem.getAddrSpaceId());
const void *buf = reinterpret_cast<void *>(trans.getLocalAddr(0));
if (buf == nullptr)
throw RuntimeError("Buffer was null");
logger->trace("Write to stream from address {:p}", buf);
return hasScatterGather() ? writeScatterGather(buf, len)
: writeSimple(buf, len);
}
bool Dma::read(const MemoryBlock &mem, size_t len) {
if (len == 0)
return true;
if (len > FPGA_DMA_BOUNDARY)
return false;
auto &mm = MemoryManager::get();
// User has to make sure that memory is accessible, otherwise this will throw
auto trans = mm.getTranslation(busMasterInterfaces[s2mmInterface],
mem.getAddrSpaceId());
void *buf = reinterpret_cast<void *>(trans.getLocalAddr(0));
if (buf == nullptr)
throw RuntimeError("Buffer was null");
return hasScatterGather() ? readScatterGather(buf, len)
: readSimple(buf, len);
}
//Write a single message
bool Dma::writeScatterGather(const void *buf, size_t len) {
// buf is address from view of DMA controller
int ret = XST_FAILURE;
hwLock.lock();
auto *txRing = XAxiDma_GetTxRing(&xDma);
if (txRing == nullptr) {
hwLock.unlock();
throw RuntimeError("TxRing was null.");
}
XAxiDma_Bd *bd;
ret = XAxiDma_BdRingAlloc(txRing, 1, &bd);
if (ret != XST_SUCCESS) {
hwLock.unlock();
throw RuntimeError("Write: BdRingAlloc returned {}.", ret);
}
ret = XAxiDma_BdSetBufAddr(bd, (uintptr_t)buf);
if (ret != XST_SUCCESS) {
hwLock.unlock();
throw RuntimeError("Setting BdBufAddr to {} returned {}.", buf, ret);
}
ret = XAxiDma_BdSetLength(bd, len, txRing->MaxTransferLen);
if (ret != XST_SUCCESS) {
hwLock.unlock();
throw RuntimeError("Setting BdBufLength to {} returned {}.", len, ret);
}
// We have a single descriptor so it is both start and end of the list
XAxiDma_BdSetCtrl(bd,
XAXIDMA_BD_CTRL_TXEOF_MASK | XAXIDMA_BD_CTRL_TXSOF_MASK);
// TODO: Check if we really need this
XAxiDma_BdSetId(bd, (uintptr_t)buf);
// Give control of BD to HW. We should not access it until transfer is finished.
// Failure could also indicate that EOF is not set on last Bd
ret = XAxiDma_BdRingToHw(txRing, 1, bd);
if (ret != XST_SUCCESS) {
hwLock.unlock();
throw RuntimeError("Enqueuing Bd and giving control to HW failed {}", ret);
}
hwLock.unlock();
return true;
}
bool Dma::readScatterGather(void *buf, size_t len) {
int ret = XST_FAILURE;
if (len < readCoalesce * readMsgSize)
throw RuntimeError(
"Read size is smaller than readCoalesce*msgSize. Cannot setup BDs.");
hwLock.lock();
auto *rxRing = XAxiDma_GetRxRing(&xDma);
if (rxRing == nullptr) {
hwLock.unlock();
throw RuntimeError("RxRing was null.");
}
XAxiDma_Bd *bd;
ret = XAxiDma_BdRingAlloc(rxRing, readCoalesce, &bd);
if (ret != XST_SUCCESS) {
hwLock.unlock();
throw RuntimeError("Failed to alloc BD in RX ring: {}", ret);
}
auto curBd = bd;
char *curBuf = (char *)buf;
for (size_t i = 0; i < readCoalesce; i++) {
ret = XAxiDma_BdSetBufAddr(curBd, (uintptr_t)curBuf);
if (ret != XST_SUCCESS) {
hwLock.unlock();
throw RuntimeError("Failed to set buffer address {:x} on BD {:x}: {}",
(uintptr_t)buf, (uintptr_t)bd, ret);
}
ret = XAxiDma_BdSetLength(curBd, readMsgSize, rxRing->MaxTransferLen);
if (ret != XST_SUCCESS) {
hwLock.unlock();
throw RuntimeError("Rx set length {} on BD {:x} failed {}", len,
(uintptr_t)bd, ret);
}
// Receive BDs do not need to set anything for the control
// The hardware will set the SOF/EOF bits per stream status
XAxiDma_BdSetCtrl(curBd, 0);
// TODO: Check if we really need this
XAxiDma_BdSetId(curBd, (uintptr_t)buf);
curBuf += readMsgSize;
curBd = (XAxiDma_Bd *)XAxiDma_BdRingNext(rxRing, curBd);
}
ret = XAxiDma_BdRingToHw(rxRing, readCoalesce, bd);
if (ret != XST_SUCCESS) {
hwLock.unlock();
throw RuntimeError("Failed to submit BD to RX ring: {}", ret);
}
hwLock.unlock();
return true;
}
Dma::Completion Dma::writeCompleteScatterGather() {
Completion c;
XAxiDma_Bd *bd = nullptr, *curBd;
auto txRing = XAxiDma_GetTxRing(&xDma);
int ret = XST_FAILURE;
static size_t errcnt = 32;
c.interrupts = irqs[mm2sInterrupt].irqController->waitForInterrupt(
irqs[mm2sInterrupt].num);
hwLock.lock();
if ((c.bds = XAxiDma_BdRingFromHw(txRing, writeCoalesce, &bd)) <
writeCoalesce) {
logger->warn("Send partial batch of {}/{} BDs.", c.bds, writeCoalesce);
if (errcnt-- == 0) {
hwLock.unlock();
throw RuntimeError("too many partial batches");
}
}
// Acknowledge the interrupt
auto irqStatus = XAxiDma_BdRingGetIrq(txRing);
XAxiDma_BdRingAckIrq(txRing, irqStatus);
if (c.bds == 0) {
c.bytes = 0;
hwLock.unlock();
return c;
}
if (bd == nullptr) {
hwLock.unlock();
throw RuntimeError("Bd was null.");
}
curBd = bd;
for (size_t i = 0; i < c.bds; i++) {
ret = XAxiDma_BdGetSts(curBd);
if ((ret & XAXIDMA_BD_STS_ALL_ERR_MASK) ||
(!(ret & XAXIDMA_BD_STS_COMPLETE_MASK))) {
hwLock.unlock();
throw RuntimeError("Bd Status register shows error: {}", ret);
}
c.bytes += XAxiDma_BdGetLength(bd, txRing->MaxTransferLen);
curBd = (XAxiDma_Bd *)XAxiDma_BdRingNext(txRing, curBd);
}
ret = XAxiDma_BdRingFree(txRing, c.bds, bd);
if (ret != XST_SUCCESS) {
hwLock.unlock();
throw RuntimeError("Failed to free {} TX BDs {}", c.bds, ret);
}
hwLock.unlock();
return c;
}
Dma::Completion Dma::readCompleteScatterGather() {
Completion c;
XAxiDma_Bd *bd = nullptr, *curBd;
auto rxRing = XAxiDma_GetRxRing(&xDma);
int ret = XST_FAILURE;
static size_t errcnt = 32;
ssize_t intrs = irqs[s2mmInterrupt].irqController->waitForInterrupt(
irqs[s2mmInterrupt].num);
if (intrs < 0) {
logger->warn("Interrupt error or timeout: {}", intrs);
// Free all RX BDs for future transmission.
int bds = XAxiDma_BdRingFromHw(rxRing, XAXIDMA_ALL_BDS, &bd);
XAxiDma_BdRingFree(rxRing, bds, bd);
c.interrupts = 0;
return c;
} else {
c.interrupts = intrs;
}
hwLock.lock();
auto irqStatus = XAxiDma_BdRingGetIrq(rxRing);
XAxiDma_BdRingAckIrq(rxRing, irqStatus);
if (!(irqStatus & XAXIDMA_IRQ_IOC_MASK)) {
logger->error("Expected IOC interrupt but IRQ status is: {:#x}", irqStatus);
return c;
}
// Wait until the data has been received by the RX channel.
if ((c.bds = XAxiDma_BdRingFromHw(rxRing, readCoalesce, &bd)) <
readCoalesce) {
logger->warn("Got partial batch of {}/{} BDs.", c.bds, readCoalesce);
if (errcnt-- == 0) {
hwLock.unlock();
throw RuntimeError("too many partial batches");
}
} else {
errcnt = 32;
}
if (c.bds == 0) {
c.bytes = 0;
hwLock.unlock();
return c;
}
if (bd == nullptr) {
hwLock.unlock();
throw RuntimeError("Bd was null.");
}
curBd = bd;
for (size_t i = 0; i < c.bds; i++) {
// logger->trace("Read BD {}/{}: {:#x}", i, c.bds,
// XAxiDma_BdGetBufAddr(curBd));
ret = XAxiDma_BdGetSts(curBd);
if ((ret & XAXIDMA_BD_STS_ALL_ERR_MASK) ||
(!(ret & XAXIDMA_BD_STS_COMPLETE_MASK))) {
hwLock.unlock();
throw RuntimeError("Bd Status register shows error: {}", ret);
}
c.bytes += XAxiDma_BdGetActualLength(bd, rxRing->MaxTransferLen);
curBd = (XAxiDma_Bd *)XAxiDma_BdRingNext(rxRing, curBd);
}
// Free all processed RX BDs for future transmission.
ret = XAxiDma_BdRingFree(rxRing, c.bds, bd);
if (ret != XST_SUCCESS) {
hwLock.unlock();
throw RuntimeError("Failed to free {} TX BDs {}.", c.bds, ret);
}
hwLock.unlock();
return c;
}
bool Dma::writeSimple(const void *buf, size_t len) {
hwLock.lock();
XAxiDma_BdRing *ring = XAxiDma_GetTxRing(&xDma);
if (not ring->HasDRE) {
const uint32_t mask = xDma.MicroDmaMode ? XAXIDMA_MICROMODE_MIN_BUF_ALIGN
: ring->DataWidth - 1;
if (reinterpret_cast<uintptr_t>(buf) & mask) {
hwLock.unlock();
return false;
}
}
const bool dmaChannelHalted =
XAxiDma_ReadReg(ring->ChanBase, XAXIDMA_SR_OFFSET) & XAXIDMA_HALTED_MASK;
const bool dmaToDeviceBusy = XAxiDma_Busy(&xDma, XAXIDMA_DMA_TO_DEVICE);
// If the engine is doing a transfer, cannot submit
if (not dmaChannelHalted and dmaToDeviceBusy) {
hwLock.unlock();
return false;
}
// Set lower 32 bit of source address
XAxiDma_WriteReg(ring->ChanBase, XAXIDMA_SRCADDR_OFFSET,
LOWER_32_BITS(reinterpret_cast<uintptr_t>(buf)));
// If neccessary, set upper 32 bit of source address
if (xDma.AddrWidth > 32)
XAxiDma_WriteReg(ring->ChanBase, XAXIDMA_SRCADDR_MSB_OFFSET,
UPPER_32_BITS(reinterpret_cast<uintptr_t>(buf)));
// Start DMA channel
auto channelControl = XAxiDma_ReadReg(ring->ChanBase, XAXIDMA_CR_OFFSET);
channelControl |= XAXIDMA_CR_RUNSTOP_MASK;
XAxiDma_WriteReg(ring->ChanBase, XAXIDMA_CR_OFFSET, channelControl);
// Set tail descriptor pointer
XAxiDma_WriteReg(ring->ChanBase, XAXIDMA_BUFFLEN_OFFSET, len);
hwLock.unlock();
return true;
}
bool Dma::readSimple(void *buf, size_t len) {
hwLock.lock();
XAxiDma_BdRing *ring = XAxiDma_GetRxRing(&xDma);
if (not ring->HasDRE) {
const uint32_t mask = xDma.MicroDmaMode ? XAXIDMA_MICROMODE_MIN_BUF_ALIGN
: ring->DataWidth - 1;
if (reinterpret_cast<uintptr_t>(buf) & mask) {
hwLock.unlock();
return false;
}
}
const bool dmaChannelHalted =
XAxiDma_ReadReg(ring->ChanBase, XAXIDMA_SR_OFFSET) & XAXIDMA_HALTED_MASK;
const bool deviceToDmaBusy = XAxiDma_Busy(&xDma, XAXIDMA_DEVICE_TO_DMA);
// If the engine is doing a transfer, cannot submit
if (not dmaChannelHalted and deviceToDmaBusy) {
hwLock.unlock();
return false;
}
// Set lower 32 bit of destination address
XAxiDma_WriteReg(ring->ChanBase, XAXIDMA_DESTADDR_OFFSET,
LOWER_32_BITS(reinterpret_cast<uintptr_t>(buf)));
// If neccessary, set upper 32 bit of destination address
if (xDma.AddrWidth > 32)
XAxiDma_WriteReg(ring->ChanBase, XAXIDMA_DESTADDR_MSB_OFFSET,
UPPER_32_BITS(reinterpret_cast<uintptr_t>(buf)));
// Start DMA channel
auto channelControl = XAxiDma_ReadReg(ring->ChanBase, XAXIDMA_CR_OFFSET);
channelControl |= XAXIDMA_CR_RUNSTOP_MASK;
XAxiDma_WriteReg(ring->ChanBase, XAXIDMA_CR_OFFSET, channelControl);
// Set tail descriptor pointer
XAxiDma_WriteReg(ring->ChanBase, XAXIDMA_BUFFLEN_OFFSET, len);
hwLock.unlock();
return true;
}
Dma::Completion Dma::writeCompleteSimple() {
Completion c;
while (!(XAxiDma_IntrGetIrq(&xDma, XAXIDMA_DMA_TO_DEVICE) &
XAXIDMA_IRQ_IOC_MASK))
c.interrupts = irqs[mm2sInterrupt].irqController->waitForInterrupt(
irqs[mm2sInterrupt]);
hwLock.lock();
XAxiDma_IntrAckIrq(&xDma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
const XAxiDma_BdRing *ring = XAxiDma_GetTxRing(&xDma);
const size_t bytesWritten =
XAxiDma_ReadReg(ring->ChanBase, XAXIDMA_BUFFLEN_OFFSET);
hwLock.unlock();
c.bytes = bytesWritten;
return c;
}
Dma::Completion Dma::readCompleteSimple() {
Completion c;
while (!(XAxiDma_IntrGetIrq(&xDma, XAXIDMA_DEVICE_TO_DMA) &
XAXIDMA_IRQ_IOC_MASK))
c.interrupts = irqs[s2mmInterrupt].irqController->waitForInterrupt(
irqs[s2mmInterrupt]);
hwLock.lock();
XAxiDma_IntrAckIrq(&xDma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
const XAxiDma_BdRing *ring = XAxiDma_GetRxRing(&xDma);
const size_t bytesRead =
XAxiDma_ReadReg(ring->ChanBase, XAXIDMA_BUFFLEN_OFFSET);
hwLock.unlock();
c.bytes = bytesRead;
return c;
}
void Dma::makeAccesibleFromVA(std::shared_ptr<MemoryBlock> mem) {
// Only symmetric mapping supported currently
if (isMemoryBlockAccesible(*mem, s2mmInterface) and
isMemoryBlockAccesible(*mem, mm2sInterface))
return;
// Try mapping via FPGA-card (VFIO)
if (not card->mapMemoryBlock(mem))
throw RuntimeError("Memory not accessible by DMA");
// Sanity-check if mapping worked, this shouldn't be neccessary
if (not isMemoryBlockAccesible(*mem, s2mmInterface) or
not isMemoryBlockAccesible(*mem, mm2sInterface))
throw RuntimeError(
"Mapping memory via card didn't work, but reported success?!");
}
bool Dma::isMemoryBlockAccesible(const MemoryBlock &mem,
const std::string &interface) {
auto &mm = MemoryManager::get();
try {
mm.findPath(getMasterAddrSpaceByInterface(interface), mem.getAddrSpaceId());
} catch (const std::out_of_range &) {
return false; // Not (yet) accessible
}
return true;
}
void Dma::dump() {
Core::dump();
logger->info(
"S2MM_DMACR: {:x}",
XAxiDma_ReadReg(xDma.RegBase, XAXIDMA_RX_OFFSET + XAXIDMA_CR_OFFSET));
logger->info(
"S2MM_DMASR: {:x}",
XAxiDma_ReadReg(xDma.RegBase, XAXIDMA_RX_OFFSET + XAXIDMA_SR_OFFSET));
if (!hasScatterGather())
logger->info("S2MM_LENGTH: {:x}",
XAxiDma_ReadReg(xDma.RegBase,
XAXIDMA_RX_OFFSET + XAXIDMA_BUFFLEN_OFFSET));
logger->info(
"MM2S_DMACR: {:x}",
XAxiDma_ReadReg(xDma.RegBase, XAXIDMA_TX_OFFSET + XAXIDMA_CR_OFFSET));
logger->info(
"MM2S_DMASR: {:x}",
XAxiDma_ReadReg(xDma.RegBase, XAXIDMA_TX_OFFSET + XAXIDMA_SR_OFFSET));
}
void DmaFactory::parse(Core &ip, json_t *cfg) {
NodeFactory::parse(ip, cfg);
auto &dma = dynamic_cast<Dma &>(ip);
dma.polling = dma.card->polling;
// Sensible default configuration
dma.xConfig.HasStsCntrlStrm = 0;
dma.xConfig.HasMm2S = 1;
dma.xConfig.HasMm2SDRE = 0;
dma.xConfig.Mm2SDataWidth = 32;
dma.xConfig.HasS2Mm = 1;
dma.xConfig.HasS2MmDRE = 0;
dma.xConfig.HasSg = 1;
dma.xConfig.S2MmDataWidth = 32;
dma.xConfig.Mm2sNumChannels = 1;
dma.xConfig.S2MmNumChannels = 1;
dma.xConfig.Mm2SBurstSize = 16;
dma.xConfig.S2MmBurstSize = 16;
dma.xConfig.MicroDmaMode = 0;
dma.xConfig.AddrWidth = 32;
dma.xConfig.SgLengthWidth = 14;
json_error_t err;
int ret = json_unpack_ex(
cfg, &err, 0,
"{ s: { s?: i, s?: i, s?: i, s?: i, s?: i, s?: i, s?: i, s?: i, s?: i, "
"s?: i, s?: i, s?: i, s?: i } }",
"parameters", "c_sg_include_stscntrl_strm", &dma.xConfig.HasStsCntrlStrm,
"c_include_mm2s", &dma.xConfig.HasMm2S, "c_include_mm2s_dre",
&dma.xConfig.HasMm2SDRE, "c_m_axi_mm2s_data_width",
&dma.xConfig.Mm2SDataWidth, "c_include_s2mm", &dma.xConfig.HasS2Mm,
"c_include_s2mm_dre", &dma.xConfig.HasS2MmDRE, "c_m_axi_s2mm_data_width",
&dma.xConfig.S2MmDataWidth, "c_include_sg", &dma.xConfig.HasSg,
"c_num_mm2s_channels", &dma.xConfig.Mm2sNumChannels,
"c_num_s2mm_channels", &dma.xConfig.S2MmNumChannels, "c_micro_dma",
&dma.xConfig.MicroDmaMode, "c_addr_width", &dma.xConfig.AddrWidth,
"c_sg_length_width", &dma.xConfig.SgLengthWidth);
if (ret != 0)
throw ConfigError(cfg, err, "", "Failed to parse DMA configuration");
dma.configDone = true;
}
static DmaFactory f;

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/* AXI External Memory Controller (EMC)
*
* Author: Steffen Vogel <post@steffenvogel.de>
* SPDX-FileCopyrightText: 2017 Steffen Vogel <post@steffenvogel.de>
* SPDX-License-Identifier: Apache-2.0
*/
#include <iostream>
#include <villas/plugin.hpp>
#include <villas/fpga/ips/emc.hpp>
using namespace villas::fpga::ip;
bool EMC::init()
{
int ret;
const uintptr_t base = getBaseAddr(registerMemory);
const int busWidth = 2;
#if defined(XPAR_XFL_DEVICE_FAMILY_INTEL) && XFL_TO_ASYNCMODE
// Set Flash to Async mode.
if (busWidth == 1) {
WRITE_FLASH_8(base + ASYNC_ADDR, 0x60);
WRITE_FLASH_8(base + ASYNC_ADDR, 0x03);
}
else if (busWidth == 2) {
WRITE_FLASH_16(base + ASYNC_ADDR, INTEL_CMD_CONFIG_REG_SETUP);
WRITE_FLASH_16(base + ASYNC_ADDR, INTEL_CMD_CONFIG_REG_CONFIRM);
}
#endif
ret = XFlash_Initialize(&xflash, base, busWidth, 0);
if (ret != XST_SUCCESS)
return false;
return XFlash_IsReady(&xflash);
}
bool EMC::read(uint32_t offset, uint32_t length, uint8_t *data)
{
int ret;
/* Reset the Flash Device. This clears the ret registers and puts
* the device in Read mode.
*/
ret = XFlash_Reset(&xflash);
if (ret != XST_SUCCESS)
return false;
// Perform the read operation.
ret = XFlash_Read(&xflash, offset, length, data);
if (ret != XST_SUCCESS)
return false;
return false;
}
// objcopy -I ihex -O binary somefile.mcs somefile.bin
bool EMC::flash(uint32_t offset, const std::string &filename)
{
bool result;
uint32_t length;
uint8_t *buffer;
std::ifstream is(filename, std::ios::binary);
// Get length of file:
is.seekg(0, std::ios::end);
length = is.tellg();
is.seekg (0, std::ios::beg);
// Allocate memory:
buffer = new uint8_t[length];
is.read(reinterpret_cast<char *>(buffer), length);
is.close();
result = flash(offset, length, buffer);
delete[] buffer;
return result;
}
// Based on xilflash_readwrite_example.c
bool EMC::flash(uint32_t offset, uint32_t length, uint8_t *data)
{
int ret = XST_FAILURE;
uint32_t start = offset;
/* Reset the Flash Device. This clears the ret registers and puts
* the device in Read mode. */
ret = XFlash_Reset(&xflash);
if (ret != XST_SUCCESS){
return false;
}
/* Perform an unlock operation before the erase operation for the Intel
* Flash. The erase operation will result in an error if the block is
* locked. */
if ((xflash.CommandSet == XFL_CMDSET_INTEL_STANDARD) ||
(xflash.CommandSet == XFL_CMDSET_INTEL_EXTENDED) ||
(xflash.CommandSet == XFL_CMDSET_INTEL_G18)) {
ret = XFlash_Unlock(&xflash, offset, 0);
if(ret != XST_SUCCESS){
return false;
}
}
// Perform the Erase operation.
ret = XFlash_Erase(&xflash, start, length);
if (ret != XST_SUCCESS){;
return false;
}
// Perform the Write operation.
ret = XFlash_Write(&xflash, start, length, data);
if (ret != XST_SUCCESS){
return false;
}
// Perform the read operation.
uint8_t *verify_data = new uint8_t[length];
ret = XFlash_Read(&xflash, start, length, verify_data);
if(ret != XST_SUCCESS) {
delete[] verify_data;
return false;
}
// Compare the data read against the data Written.
for (unsigned i = 0; i < length; i++) {
if (verify_data[i] != data[i]){
delete[] verify_data;
return false;
}
}
delete[] verify_data;
return true;
}
static char n[] = "emc";
static char d[] = "Xilinx's AXI External Memory Controller";
static char v[] = "xilinx.com:ip:axi_emc:";
static CorePlugin<EMC, n, d, v> f;

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/* FIFO related helper functions
*
* These functions present a simpler interface to Xilinx' FIFO driver (XLlFifo_*)
*
* Author: Steffen Vogel <post@steffenvogel.de>
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Steffen Vogel <post@steffenvogel.de>
* SPDX-License-Identifier: Apache-2.0
*/
#include <unistd.h>
#include <xilinx/xstatus.h>
#include <xilinx/xllfifo.h>
#include <villas/fpga/ips/fifo.hpp>
#include <villas/fpga/ips/intc.hpp>
using namespace villas::fpga::ip;
bool Fifo::init()
{
XLlFifo_Config fifo_cfg;
try {
// If this throws an exception, then there's no AXI4 data interface
fifo_cfg.Axi4BaseAddress = getBaseAddr(axi4Memory);
fifo_cfg.Datainterface = 1;
} catch (const std::out_of_range&) {
fifo_cfg.Datainterface = 0;
}
if (XLlFifo_CfgInitialize(&xFifo, &fifo_cfg, getBaseAddr(registerMemory)) != XST_SUCCESS)
return false;
if (irqs.find(irqName) == irqs.end()) {
logger->error("IRQ '{}' not found but required", irqName);
return false;
}
// Receive complete IRQ
XLlFifo_IntEnable(&xFifo, XLLF_INT_RC_MASK);
irqs[irqName].irqController->enableInterrupt(irqs[irqName], false);
return true;
}
bool Fifo::stop()
{
// Receive complete IRQ
XLlFifo_IntDisable(&xFifo, XLLF_INT_RC_MASK);
irqs[irqName].irqController->disableInterrupt(irqs[irqName]);
return true;
}
size_t Fifo::write(const void *buf, size_t len)
{
uint32_t tdfv;
tdfv = XLlFifo_TxVacancy(&xFifo);
if (tdfv < len)
return -1;
// Buf has to be re-casted because Xilinx driver doesn't use const
XLlFifo_Write(&xFifo, (void*) buf, len);
XLlFifo_TxSetLen(&xFifo, len);
return len;
}
size_t Fifo::read(void *buf, size_t len)
{
size_t nextlen = 0;
size_t rxlen;
while (!XLlFifo_IsRxDone(&xFifo))
irqs[irqName].irqController->waitForInterrupt(irqs[irqName]);
XLlFifo_IntClear(&xFifo, XLLF_INT_RC_MASK);
// Get length of next frame
rxlen = XLlFifo_RxGetLen(&xFifo);
nextlen = std::min(rxlen, len);
// Read from FIFO
XLlFifo_Read(&xFifo, buf, nextlen);
return nextlen;
}
static char n1[] = "fifo";
static char d1[] = "Xilinx's AXI4 FIFO data mover";
static char v1[] = "xilinx.com:ip:axi_fifo_mm_s:";
static NodePlugin<Fifo, n1, d1, v1> p1;
static char n2[] = "fifo_data";
static char d2[] = "Xilinx's AXI4 data stream FIFO";
static char v2[] = "xilinx.com:ip:axis_data_fifo:";
static NodePlugin<FifoData, n2, d2, v2> p2;

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/* AXI General Purpose IO (GPIO)
*
* Author: Steffen Vogel <post@steffenvogel.de>
* SPDX-FileCopyrightText: 2017 Steffen Vogel <post@steffenvogel.de>
* SPDX-License-Identifier: Apache-2.0
*/
#include <villas/plugin.hpp>
#include <villas/fpga/ips/gpio.hpp>
using namespace villas::fpga::ip;
bool
Gpio::init()
{
//const uintptr_t base = getBaseAddr(registerMemory);
return true;
}
static char n[] = "gpio";
static char d[] = "Xilinx's AXI4 general purpose IO";
static char v[] = "xilinx.com:ip:axi_gpio:";
static CorePlugin<Gpio, n, d, v> f;

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/* I2C driver
*
* Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
* SPDX-FileCopyrightText: 2023 Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
* SPDX-License-Identifier: Apache-2.0
*/
#include <sstream>
#include <string>
#include <xilinx/xiic.h>
#include <villas/fpga/ips/i2c.hpp>
#include <villas/fpga/ips/intc.hpp>
#include <villas/log.hpp>
using namespace villas::fpga::ip;
I2c::I2c()
: Node(), transmitIntrs(0), receiveIntrs(0), statusIntrs(0), xIic(),
xConfig(), hwLock(), configDone(false), initDone(false), polling(false),
switchInstance(nullptr) {}
I2c::~I2c() {}
static void SendHandler(I2c *i2c, __attribute__((unused)) int bytesSend) {
i2c->transmitIntrs++;
}
static void ReceiveHandler(I2c *i2c, __attribute__((unused)) int bytesSend) {
i2c->receiveIntrs++;
}
static void StatusHandler(I2c *i2c, __attribute__((unused)) int event) {
i2c->statusIntrs++;
}
bool I2c::init() {
int ret;
if (!configDone) {
throw RuntimeError("I2C configuration not done");
}
if (initDone) {
logger->warn("I2C already initialized");
return true;
}
xConfig.BaseAddress = getBaseAddr(registerMemory);
logger->debug("I2C base address: {:#x}", xConfig.BaseAddress);
hwLock.lock();
ret = XIic_CfgInitialize(&xIic, &xConfig, xConfig.BaseAddress);
if (ret != XST_SUCCESS) {
throw RuntimeError("Failed to initialize I2C");
}
XIic_SetSendHandler(&xIic, this, (XIic_Handler)SendHandler);
XIic_SetRecvHandler(&xIic, this, (XIic_Handler)ReceiveHandler);
XIic_SetStatusHandler(&xIic, this, (XIic_StatusHandler)StatusHandler);
irqs[i2cInterrupt].irqController->enableInterrupt(irqs[i2cInterrupt],
0); //polling);
hwLock.unlock();
initDone = true;
return true;
}
bool I2c::check() {
if (!initDone) {
throw RuntimeError("I2C not initialized");
}
return getSwitch().selfTest();
}
bool I2c::stop() { return reset(); }
bool I2c::reset() {
logger->debug("I2C reset");
// we cannot lock here because this may be called in a destructor
XIic_Reset(&xIic);
irqs[i2cInterrupt].irqController->disableInterrupt(irqs[i2cInterrupt]);
initDone = false;
return true;
}
void I2c::driverWriteBlocking(u8 *dataPtr, size_t size) {
int ret;
int intrRetries;
int sendRetries = 10;
int bbRetries;
transmitIntrs = 0;
// We retry the entire transmission a few times before giving up.
while (transmitIntrs == 0 && sendRetries > 0) {
xIic.Stats.TxErrors = 0;
bbRetries = 1;
intrRetries = 10;
// We retry once when the bus is busy.
do {
ret = XIic_MasterSend(&xIic, dataPtr, size);
if (ret == XST_IIC_BUS_BUSY) {
waitForBusNotBusy();
} else if (ret != XST_SUCCESS) {
throw RuntimeError("Failed to send I2C data. code: {}", ret);
}
} while (ret == XST_IIC_BUS_BUSY && --bbRetries >= 0);
// We need to wait for several interrupts as sending the stop condition involves generating
// multiple interrupts before the transmission is complete.
while (transmitIntrs == 0 && intrRetries > 0) {
ssize_t intrs = irqs[i2cInterrupt].irqController->waitForInterrupt(
irqs[i2cInterrupt].num);
if (intrs == -1) {
break;
}
// logger->trace("I2C write interrupt eventfd read: {}, ISR: {}", numIntr,
// irqStatus);
XIic_InterruptHandler(&xIic);
--intrRetries;
}
--sendRetries;
}
if (sendRetries == 0) {
throw RuntimeError(
"Failed to send I2C data: No transmit interrupt after 10 tries.");
}
if (xIic.Stats.TxErrors > 0) {
throw RuntimeError("Failed to send I2C data: {} TX errors",
xIic.Stats.TxErrors);
}
}
void I2c::driverReadBlocking(u8 *dataPtr, size_t max_read) {
int ret;
int intrRetries;
int readRetries = 10;
int bbRetries;
receiveIntrs = 0;
while (receiveIntrs == 0 && readRetries > 0) {
intrRetries = 10;
bbRetries = 1;
do {
ret = XIic_MasterRecv(&xIic, dataPtr, max_read);
if (ret == XST_IIC_BUS_BUSY) {
waitForBusNotBusy();
} else if (ret != XST_SUCCESS) {
throw RuntimeError("Failed to receive I2C data: code {}", ret);
}
} while (ret == XST_IIC_BUS_BUSY && --bbRetries >= 0);
while (receiveIntrs == 0 && intrRetries > 0) {
ssize_t intrs = irqs[i2cInterrupt].irqController->waitForInterrupt(
irqs[i2cInterrupt].num);
if (intrs == -1) {
break;
}
XIic_InterruptHandler(&xIic);
--intrRetries;
}
--readRetries;
}
if (readRetries == 0) {
throw RuntimeError(
"Failed to receive I2C data: No receive interrupt after 10 tries.");
}
}
void I2c::waitForBusNotBusy() {
int retries = 10;
uint32_t irqStatus;
do {
irqs[i2cInterrupt].irqController->waitForInterrupt(irqs[i2cInterrupt].num);
irqStatus =
XIic_ReadIisr(xIic.BaseAddress) & XIic_ReadIier(xIic.BaseAddress);
} while (!(irqStatus & XIIC_INTR_BNB_MASK) && --retries > 0);
// logger->trace("I2C bus not busy after {} interrupts", 10 - retries);
//Deactivate BusNotBusy interrupt
XIic_WriteIier(xIic.BaseAddress,
XIic_ReadIier(xIic.BaseAddress) & ~(XIIC_INTR_BNB_MASK));
uint32_t clear = XIIC_INTR_BNB_MASK;
XIic_WriteIisr(xIic.BaseAddress, clear);
if (retries == 0) {
throw RuntimeError("I2C bus stayed busy after 10 interrupts");
}
}
bool I2c::write(u8 address, std::vector<u8> &data) {
int ret;
if (!initDone) {
throw RuntimeError("I2C not initialized");
}
hwLock.lock();
ret =
XIic_SetAddress(&xIic, XII_ADDR_TO_SEND_TYPE, static_cast<int>(address));
if (ret != XST_SUCCESS) {
throw RuntimeError("Failed to set I2C address");
}
ret = XIic_Start(&xIic);
if (ret != XST_SUCCESS) {
throw RuntimeError("Failed to start I2C");
}
driverWriteBlocking(data.data(), data.size());
ret = XIic_Stop(&xIic);
if (ret != XST_SUCCESS) {
throw RuntimeError("Failed to stop I2C");
}
hwLock.unlock();
return true;
}
bool I2c::read(u8 address, std::vector<u8> &data, size_t max_read) {
int ret;
if (!initDone) {
throw RuntimeError("I2C not initialized");
}
data.resize(data.size() + max_read);
u8 *dataPtr = data.data() + data.size() - max_read;
hwLock.lock();
ret =
XIic_SetAddress(&xIic, XII_ADDR_TO_SEND_TYPE, static_cast<int>(address));
if (ret != XST_SUCCESS) {
throw RuntimeError("Failed to set I2C address");
}
ret = XIic_Start(&xIic);
if (ret != XST_SUCCESS) {
throw RuntimeError("Failed to start I2C");
}
driverReadBlocking(dataPtr, max_read);
ret = XIic_Stop(&xIic);
if (ret != XST_SUCCESS) {
throw RuntimeError("Failed to stop I2C");
}
hwLock.unlock();
return XST_SUCCESS;
}
bool I2c::readRegister(u8 address, u8 reg, std::vector<u8> &data,
size_t max_read) {
std::vector<u8> regData = {reg};
bool ret;
ret = write(address, regData);
ret &= read(address, data, max_read);
return ret;
}
static const uint8_t CHANNEL_MAP[] = I2C_SWITCH_CHANNEL_MAP;
void I2c::Switch::setChannel(uint8_t channel) {
if (channel >= sizeof(CHANNEL_MAP) / sizeof(CHANNEL_MAP[0])) {
throw RuntimeError("Invalid channel number {}", channel);
}
this->channel = channel;
readOnce = true;
std::vector<u8> data = {CHANNEL_MAP[channel]};
i2c->write(address, data);
}
uint8_t I2c::Switch::getChannel() {
std::vector<u8> data;
int retries = 10;
do {
i2c->read(address, data, 1);
} while (readOnce && data[0] != CHANNEL_MAP[channel] && --retries >= 0);
if (retries == 0) {
throw RuntimeError(
"Invalid channel readback after 10 retries: {:x} != {:x}", data[0],
CHANNEL_MAP[channel]);
}
if (!readOnce) {
for (size_t i = 0; i < sizeof(CHANNEL_MAP) / sizeof(CHANNEL_MAP[0]); ++i) {
if (data[0] == CHANNEL_MAP[i]) {
channel = i;
break;
}
}
readOnce = true;
}
return channel;
}
bool I2c::Switch::selfTest() {
uint8_t readback;
logger->debug("I2c::Switch self test. Testing {} channels of device {:#x}",
sizeof(CHANNEL_MAP) / sizeof(CHANNEL_MAP[0]), address);
for (size_t i = 0; i < sizeof(CHANNEL_MAP) / sizeof(CHANNEL_MAP[0]); ++i) {
logger->debug("Setting switch to channel {}, data byte {:#x}", i,
CHANNEL_MAP[i]);
setAndLockChannel(i);
try {
readback = getChannel();
logger->debug("Readback channel: {}", readback);
} catch (const RuntimeError &e) {
logger->debug("Encoutered error on readback: {}", e.what());
return false;
}
unlockChannel();
}
return true;
}
void I2cFactory::parse(Core &ip, json_t *cfg) {
NodeFactory::parse(ip, cfg);
auto &i2c = dynamic_cast<I2c &>(ip);
int i2c_frequency = 0;
char *component_name = nullptr;
json_error_t err;
int ret = json_unpack_ex(cfg, &err, 0, "{ s: { s?: i, s?: i, s?: i, s?: s} }",
"parameters", "c_iic_freq", &i2c_frequency,
"c_ten_bit_adr", &i2c.xConfig.Has10BitAddr,
"c_gpo_width", &i2c.xConfig.GpOutWidth,
"component_name", &component_name);
if (ret != 0) {
throw ConfigError(cfg, err, "", "Failed to parse DMA configuration for {}",
ip.getInstanceName());
}
if (component_name != nullptr) {
char last_letter = component_name[strlen(component_name) - 1];
if (last_letter >= '0' && last_letter <= '9') {
i2c.xConfig.DeviceId = last_letter - '0';
} else {
throw RuntimeError("Invalid device ID in component name {} for {}",
component_name, ip.getInstanceName());
}
}
i2c.configDone = true;
}
static I2cFactory f;

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/* AXI-PCIe Interrupt controller
*
* Author: Steffen Vogel <post@steffenvogel.de>
* SPDX-FileCopyrightText: 2017 Steffen Vogel <post@steffenvogel.de>
* SPDX-License-Identifier: Apache-2.0
*/
#include <unistd.h>
#include <errno.h>
#include <villas/config.hpp>
#include <villas/plugin.hpp>
#include <villas/kernel/kernel.hpp>
#include <villas/fpga/card.hpp>
#include <villas/fpga/ips/intc.hpp>
#include <villas/fpga/pcie_card.hpp>
using namespace villas::fpga::ip;
InterruptController::~InterruptController() {}
bool InterruptController::stop() {
return card->vfioDevice->pciMsiDeinit(this->efds) > 0;
}
bool
InterruptController::init()
{
const uintptr_t base = getBaseAddr(registerMemory);
num_irqs = card->vfioDevice->pciMsiInit(efds);
if (num_irqs < 0)
return false;
if (not card->vfioDevice->pciMsiFind(nos)) {
return false;
}
// For each IRQ
for (int i = 0; i < num_irqs; i++) {
// Try pinning to core
PCIeCard* pciecard = dynamic_cast<PCIeCard*>(card);
int ret = kernel::setIRQAffinity(nos[i], pciecard->affinity, nullptr);
switch(ret) {
case 0:
// Everything is fine
break;
case EACCES:
logger->warn("No permission to change affinity of VFIO-MSI interrupt, "
"performance may be degraded!");
break;
default:
logger->error("Failed to change affinity of VFIO-MSI interrupt");
return false;
}
// Setup vector
XIntc_Out32(base + XIN_IVAR_OFFSET + i * 4, i);
}
XIntc_Out32(base + XIN_IMR_OFFSET, 0x00000000); // Use manual acknowlegement for all IRQs
XIntc_Out32(base + XIN_IAR_OFFSET, 0xFFFFFFFF); // Acknowlege all pending IRQs manually
XIntc_Out32(base + XIN_IMR_OFFSET, 0xFFFFFFFF); // Use fast acknowlegement for all IRQs
XIntc_Out32(base + XIN_IER_OFFSET, 0x00000000); // Disable all IRQs by default
XIntc_Out32(base + XIN_MER_OFFSET, XIN_INT_HARDWARE_ENABLE_MASK | XIN_INT_MASTER_ENABLE_MASK);
logger->debug("enabled interrupts");
return true;
}
bool
InterruptController::enableInterrupt(InterruptController::IrqMaskType mask, bool polling)
{
const uintptr_t base = getBaseAddr(registerMemory);
// Current state of INTC
const uint32_t ier = XIntc_In32(base + XIN_IER_OFFSET);
const uint32_t imr = XIntc_In32(base + XIN_IMR_OFFSET);
// Clear pending IRQs
XIntc_Out32(base + XIN_IAR_OFFSET, mask);
for (int i = 0; i < num_irqs; i++) {
if (mask & (1 << i))
this->polling[i] = polling;
}
if (polling) {
XIntc_Out32(base + XIN_IMR_OFFSET, imr & ~mask);
XIntc_Out32(base + XIN_IER_OFFSET, ier & ~mask);
}
else {
XIntc_Out32(base + XIN_IER_OFFSET, ier | mask);
XIntc_Out32(base + XIN_IMR_OFFSET, imr | mask);
}
logger->debug("New ier = {:x}", XIntc_In32(base + XIN_IER_OFFSET));
logger->debug("New imr = {:x}", XIntc_In32(base + XIN_IMR_OFFSET));
logger->debug("New isr = {:x}", XIntc_In32(base + XIN_ISR_OFFSET));
logger->debug("Interupts enabled: mask={:x} polling={:d}", mask, polling);
return true;
}
bool
InterruptController::disableInterrupt(InterruptController::IrqMaskType mask)
{
const uintptr_t base = getBaseAddr(registerMemory);
uint32_t ier = XIntc_In32(base + XIN_IER_OFFSET);
XIntc_Out32(base + XIN_IER_OFFSET, ier & ~mask);
return true;
}
ssize_t InterruptController::waitForInterrupt(int irq) {
assert(irq < maxIrqs);
if (this->polling[irq]) {
const uintptr_t base = getBaseAddr(registerMemory);
uint32_t isr, mask = 1 << irq;
do {
// Poll status register
isr = XIntc_In32(base + XIN_ISR_OFFSET);
pthread_testcancel();
} while ((isr & mask) != mask);
// Acknowledge interrupt
XIntc_Out32(base + XIN_IAR_OFFSET, mask);
// We can only tell that there has been (at least) one interrupt
return 1;
} else {
uint64_t count;
int sret;
fd_set rfds;
struct timeval tv = {.tv_sec = 1, .tv_usec = 0};
FD_ZERO(&rfds);
FD_SET(efds[irq], &rfds);
sret = select(efds[irq] + 1, &rfds, NULL, NULL, &tv);
if (sret == -1) {
logger->error("select() failed: {}", strerror(errno));
return -1;
} else if (sret == 0) {
logger->warn("timeout waiting for interrupt {}", irq);
return -1;
}
// Block until there has been an interrupt, read number of interrupts
ssize_t ret = read(efds[irq], &count, sizeof(count));
if (ret != sizeof(count)) {
logger->error("Failed to read from eventfd: {}", strerror(errno));
return -1;
}
return count;
}
}
static char n[] = "intc";
static char d[] = "Xilinx's programmable interrupt controller";
static char v[] = "xilinx.com:module_ref:axi_pcie_intc:";
static CorePlugin<InterruptController, n, d, v> f;

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/* AXI PCIe bridge
*
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2018 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#include <limits>
#include <jansson.h>
#include <villas/exceptions.hpp>
#include <villas/memory.hpp>
#include <villas/fpga/card.hpp>
#include <villas/fpga/ips/pcie.hpp>
#include <villas/fpga/pcie_card.hpp>
using namespace villas::fpga::ip;
bool
AxiPciExpressBridge::init()
{
auto &mm = MemoryManager::get();
// Throw an exception if the is no bus master interface and thus no
// address space we can use for translation -> error
card->addrSpaceIdHostToDevice = busMasterInterfaces.at(axiInterface);
// Map PCIe BAR0 via VFIO
const void* bar0_mapped = card->vfioDevice->regionMap(VFIO_PCI_BAR0_REGION_INDEX);
if (bar0_mapped == MAP_FAILED) {
logger->error("Failed to mmap() BAR0");
return false;
}
// Determine size of BAR0 region
const size_t bar0_size = card->vfioDevice->regionGetSize(VFIO_PCI_BAR0_REGION_INDEX);
// Create a mapping from process address space to the FPGA card via vfio
mm.createMapping(reinterpret_cast<uintptr_t>(bar0_mapped),
0, bar0_size, "vfio-h2d",
mm.getProcessAddressSpace(),
card->addrSpaceIdHostToDevice);
// Make PCIe (IOVA) address space available to FPGA via BAR0
// IPs that can access this address space will know it via their memory view
const auto addrSpaceNameDeviceToHost =
mm.getSlaveAddrSpaceName(getInstanceName(), pcieMemory);
// Save ID in card so we can create mappings later when needed (e.g. when
// allocating DMA memory in host RAM)
card->addrSpaceIdDeviceToHost =
mm.getOrCreateAddressSpace(addrSpaceNameDeviceToHost);
auto pciAddrSpaceId = mm.getPciAddressSpace();
auto regions = dynamic_cast<PCIeCard*>(card)->pdev->getRegions();
int i = 0;
for (auto region : regions) {
const size_t region_size = region.end - region.start + 1;
char barName[] = "BARx";
barName[3] = '0' + region.num;
auto pciBar = pcieToAxiTranslations.at(barName);
logger->info("PCI-BAR{}: bus addr={:#x} size={:#x}",
region.num, region.start, region_size);
logger->info("PCI-BAR{}: AXI translation offset {:#x}",
i, pciBar.translation);
mm.createMapping(region.start, pciBar.translation, region_size,
std::string("PCI-") + barName,
pciAddrSpaceId, card->addrSpaceIdHostToDevice);
}
for (auto& [barName, axiBar] : axiToPcieTranslations) {
logger->info("AXI-{}: bus addr={:#x} size={:#x}",
barName, axiBar.base, axiBar.size);
logger->info("AXI-{}: PCI translation offset: {:#x}",
barName, axiBar.translation);
auto barXAddrSpaceName = mm.getSlaveAddrSpaceName(getInstanceName(), barName);
auto barXAddrSpaceId = mm.getOrCreateAddressSpace(barXAddrSpaceName);
// Base is already incorporated into mapping of each IP by Vivado, so
// the mapping src has to be 0
mm.createMapping(0, axiBar.translation, axiBar.size,
std::string("AXI-") + barName,
barXAddrSpaceId, pciAddrSpaceId);
i++;
}
return true;
}
void
AxiPciExpressBridgeFactory::parse(Core &ip, json_t *cfg)
{
CoreFactory::parse(ip, cfg);
auto logger = getLogger();
auto &pcie = dynamic_cast<AxiPciExpressBridge&>(ip);
for (auto barType : std::list<std::string>{
"axi_bars",
"pcie_bars"
}) {
json_t *json_bars = json_object_get(cfg, barType.c_str());
if (not json_is_object(json_bars))
throw ConfigError(cfg, "", "Missing BAR config: {}", barType);
json_t* json_bar;
const char* bar_name;
json_object_foreach(json_bars, bar_name, json_bar) {
unsigned int translation;
json_error_t err;
int ret = json_unpack_ex(json_bar, &err, 0, "{ s: i }",
"translation", &translation
);
if (ret != 0)
throw ConfigError(json_bar, err, "", "Cannot parse {}/{}", barType, bar_name);
if (barType == "axi_bars") {
json_int_t base, high, size;
int ret = json_unpack_ex(json_bar, &err, 0, "{ s: I, s: I, s: I }",
"baseaddr", &base,
"highaddr", &high,
"size", &size
);
if (ret != 0)
throw ConfigError(json_bar, err, "", "Cannot parse {}/{}", barType, bar_name);
pcie.axiToPcieTranslations[bar_name] = {
.base = static_cast<uintptr_t>(base),
.size = static_cast<size_t>(size),
.translation = translation
};
} else
pcie.pcieToAxiTranslations[bar_name] = {
.translation = translation
};
}
}
}
static AxiPciExpressBridgeFactory p;

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/* Driver for register interface 'registerif'
*
* Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
* SPDX-FileCopyrightText: 2024 Niklas Eiling
* SPDX-License-Identifier: Apache-2.0
*/
#include <xilinx/xil_io.h>
#include <villas/fpga/ips/register.hpp>
using namespace villas::fpga::ip;
#define REGISTER_RESET (512)
#define REGISTER_OUT(NUM) (4 * NUM)
Register::Register() : Node() {}
bool Register::init() { return true; }
bool Register::check() {
logger->debug("Checking register interface: Base address: 0x{:08x}",
getBaseAddr(registerMemory));
uint32_t buf;
// we shouldn't change the rate register, because this can lead to hardware fault, so start at 1
for (size_t i = 1; i < registerNum; i++) {
setRegister(i, static_cast<uint32_t>(i));
}
for (size_t i = 1; i < registerNum; i++) {
buf = getRegister(i);
if (buf != i) {
logger->error("Register {}: 0x{:08x} != 0x{:08x}", i, buf, i);
return false;
}
}
resetAllRegisters();
for (size_t i = 0; i < registerNum; i++) {
logger->debug("Register {}: 0x{:08x}", i, getRegister(i));
}
// This is Dino specific for now - we should possibly move this to Dino in the future
// setRegister(0, static_cast<uint32_t>(1000)); // set Dino to a rate of 20 kHz
setRegister(0, static_cast<uint32_t>(100000)); // set Dino to a rate of 20 kHz
setRegister(1, -0.001615254F);
setRegister(2, 10.8061F);
uint32_t rate = getRegister(0);
float scale = getRegisterFloat(1);
float offset = getRegisterFloat(2);
logger->info("Check: Register configuration: Rate: {}, Scale: {}, Offset: {}",
rate, scale, offset);
return true;
}
void Register::setRegister(size_t reg, uint32_t value) {
if (reg >= registerNum) {
logger->error("Register index out of range: {}/{}", reg, registerNum);
throw std::out_of_range("Register index out of range");
}
Xil_Out32(getBaseAddr(registerMemory) + REGISTER_OUT(reg), value);
}
void Register::setRegister(size_t reg, float value) {
if (reg >= registerNum) {
logger->error("Register index out of range: {}/{}", reg, registerNum);
throw std::out_of_range("Register index out of range");
}
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wstrict-aliasing"
Xil_Out32(getBaseAddr(registerMemory) + REGISTER_OUT(reg),
reinterpret_cast<uint32_t &>(value));
#pragma GCC diagnostic pop
}
uint32_t Register::getRegister(size_t reg) {
if (reg >= registerNum) {
logger->error("Register index out of range: {}/{}", reg, registerNum);
throw std::out_of_range("Register index out of range");
}
return Xil_In32(getBaseAddr(registerMemory) + REGISTER_OUT(reg));
}
float Register::getRegisterFloat(size_t reg) {
if (reg >= registerNum) {
logger->error("Register index out of range: {}/{}", reg, registerNum);
throw std::out_of_range("Register index out of range");
}
uint32_t value = Xil_In32(getBaseAddr(registerMemory) + REGISTER_OUT(reg));
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wstrict-aliasing"
return reinterpret_cast<float &>(value);
#pragma GCC diagnostic pop
}
void Register::resetRegister(size_t reg) {
if (reg >= registerNum) {
logger->error("Register index out of range: {}/{}", reg, registerNum);
throw std::out_of_range("Register index out of range");
}
Xil_Out32(getBaseAddr(registerMemory) + REGISTER_RESET, (1 << reg));
}
void Register::resetAllRegisters() {
Xil_Out32(getBaseAddr(registerMemory) + REGISTER_RESET, 0xFFFFFFFF);
}
Register::~Register() {}
static char n[] = "register";
static char d[] = "Register interface VHDL module 'registerif'";
static char v[] = "xilinx.com:module_ref:registerif:";
static CorePlugin<Register, n, d, v> f;

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/* Driver for AXI Stream wrapper around RTDS_InterfaceModule (rtds_axis )
*
* Author: Steffen Vogel <post@steffenvogel.de>
* SPDX-FileCopyrightText: 2017 Steffen Vogel <post@steffenvogel.de>
* SPDX-License-Identifier: Apache-2.0
*/
#include <cstdint>
#include <villas/utils.hpp>
#include <villas/fpga/ips/rtds.hpp>
#define RTDS_HZ 100000000 // 100 MHz
#define RTDS_AXIS_MAX_TX 64 // The amount of values which is supported by the VIILASfpga card
#define RTDS_AXIS_MAX_RX 64 // The amount of values which is supported by the VIILASfpga card
// Register offsets
#define RTDS_AXIS_SR_OFFSET 0x00 // Status Register (read-only). See RTDS_AXIS_SR_* constant.
#define RTDS_AXIS_CR_OFFSET 0x04 // Control Register (read/write)
#define RTDS_AXIS_TSCNT_LOW_OFFSET 0x08 // Lower 32 bits of timestep counter (read-only).
#define RTDS_AXIS_TSCNT_HIGH_OFFSET 0x0C // Higher 32 bits of timestep counter (read-only).
#define RTDS_AXIS_TS_PERIOD_OFFSET 0x10 // Period in clock cycles of previous timestep (read-only).
#define RTDS_AXIS_COALESC_OFFSET 0x14 // IRQ Coalescing register (read/write).
#define RTDS_AXIS_VERSION_OFFSET 0x18 // 16 bit version field passed back to the rack for version reporting (visible from “status” command, read/write).
#define RTDS_AXIS_MRATE 0x1C // Multi-rate register
// Status register bits
#define RTDS_AXIS_SR_CARDDETECTED (1 << 0) // ‘1’ when RTDS software has detected and configured card.
#define RTDS_AXIS_SR_LINKUP (1 << 1) // ‘1’ when RTDS communication link has been negotiated.
#define RTDS_AXIS_SR_TX_FULL (1 << 2) // Tx buffer is full, writes that happen when UserTxFull=’1’ will be dropped (Throttling / buffering is performed by hardware).
#define RTDS_AXIS_SR_TX_INPROGRESS (1 << 3) // Indicates when data is being put on link.
#define RTDS_AXIS_SR_CASE_RUNNING (1 << 4) // There is currently a simulation running.
// Control register bits
#define RTDS_AXIS_CR_DISABLE_LINK 0 // Disable SFP TX when set
using namespace villas::fpga::ip;
void RtdsGtfpga::dump()
{
// Check RTDS_Axis registers
const uint32_t sr = readMemory<uint32_t>(registerMemory, RTDS_AXIS_SR_OFFSET);
logger->info("RTDS AXI Stream interface details:");
logger->info("RTDS status: {:#x}", sr);
logger->info(" Card detected: {}", sr & RTDS_AXIS_SR_CARDDETECTED ? CLR_GRN("yes") : CLR_RED("no"));
logger->info(" Link up: {}", sr & RTDS_AXIS_SR_LINKUP ? CLR_GRN("yes") : CLR_RED("no"));
logger->info(" TX queue full: {}", sr & RTDS_AXIS_SR_TX_FULL ? CLR_RED("yes") : CLR_GRN("no"));
logger->info(" TX in progress: {}", sr & RTDS_AXIS_SR_TX_INPROGRESS ? CLR_YEL("yes") : "no");
logger->info(" Case running: {}", sr & RTDS_AXIS_SR_CASE_RUNNING ? CLR_GRN("yes") : CLR_RED("no"));
logger->info("RTDS control: {:#x}", readMemory<uint32_t>(registerMemory, RTDS_AXIS_CR_OFFSET));
logger->info("RTDS IRQ coalesc: {}", readMemory<uint32_t>(registerMemory, RTDS_AXIS_COALESC_OFFSET));
logger->info("RTDS IRQ version: {:#x}", readMemory<uint32_t>(registerMemory, RTDS_AXIS_VERSION_OFFSET));
logger->info("RTDS IRQ multi-rate: {}", readMemory<uint32_t>(registerMemory, RTDS_AXIS_MRATE));
const uint64_t timestepLow = readMemory<uint32_t>(registerMemory, RTDS_AXIS_TSCNT_LOW_OFFSET);
const uint64_t timestepHigh = readMemory<uint32_t>(registerMemory, RTDS_AXIS_TSCNT_HIGH_OFFSET);
const uint64_t timestep = (timestepHigh << 32) | timestepLow;
logger->info("RTDS timestep counter: {}", timestep);
logger->info("RTDS timestep period: {:.3f} us", getDt() * 1e6);
}
double RtdsGtfpga::getDt()
{
const auto dt = readMemory<uint16_t>(registerMemory, RTDS_AXIS_TS_PERIOD_OFFSET);
return (dt == 0xFFFF) ? 0.0 : (double) dt / RTDS_HZ;
}
static char n[] = "rtds_gtfpga";
static char d[] = "RTDS's AXI4-Stream - GTFPGA interface";
static char v[] = "acs.eonerc.rwth-aachen.de:user:rtds_axis:";
static NodePlugin<RtdsGtfpga, n, d, v> f;

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/* GPU2RTDS IP core
*
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Daniel Krebs <github@daniel-krebs.net>
* SPDX-License-Identifier: Apache-2.0
*/
#include <unistd.h>
#include <cstring>
#include <villas/log.hpp>
#include <villas/memory_manager.hpp>
#include <villas/fpga/ips/gpu2rtds.hpp>
using namespace villas::fpga::ip;
bool Gpu2Rtds::init()
{
Hls::init();
auto &registers = addressTranslations.at(registerMemory);
registerStatus = reinterpret_cast<StatusRegister*>(registers.getLocalAddr(registerStatusOffset));
registerStatusCtrl = reinterpret_cast<StatusControlRegister*>(registers.getLocalAddr(registerStatusCtrlOffset));
registerFrameSize = reinterpret_cast<uint32_t*>(registers.getLocalAddr(registerFrameSizeOffset));
registerFrames = reinterpret_cast<uint32_t*>(registers.getLocalAddr(registerFrameOffset));
maxFrameSize = getMaxFrameSize();
logger->info("Max. frame size supported: {}", maxFrameSize);
return true;
}
bool
Gpu2Rtds::startOnce(size_t frameSize)
{
*registerFrameSize = frameSize;
start();
return true;
}
void Gpu2Rtds::dump(spdlog::level::level_enum logLevel)
{
const auto frame_size = *registerFrameSize;
auto status = *registerStatus;
logger->log(logLevel, "Gpu2Rtds registers:");
logger->log(logLevel, " Frame size (words): {:#x}", frame_size);
logger->log(logLevel, " Status: {:#x}", status.value);
logger->log(logLevel, " Running: {}", (status.is_running ? "yes" : "no"));
logger->log(logLevel, " Frame too short: {}", (status.frame_too_short ? "yes" : "no"));
logger->log(logLevel, " Frame too long: {}", (status.frame_too_long ? "yes" : "no"));
logger->log(logLevel, " Frame size invalid: {}", (status.invalid_frame_size ? "yes" : "no"));
logger->log(logLevel, " Last count: {}", (int) status.last_count);
logger->log(logLevel, " Last seq. number: {}", (int) status.last_seq_nr);
logger->log(logLevel, " Max. frame size: {}", (int) status.max_frame_size);
}
//bool Gpu2Rtds::startOnce(const MemoryBlock &mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset)
//{
// auto &mm = MemoryManager::get();
// if (frameSize > maxFrameSize) {
// logger->error("Requested frame size of {} exceeds max. frame size of {}",
// frameSize, maxFrameSize);
// return false;
// }
// auto translationFromIp = mm.getTranslation(
// getMasterAddrSpaceByInterface(axiInterface),
// mem.getAddrSpaceId());
// // Set address of memory block in HLS IP
// XGpu2Rtds_Set_baseaddr(&xInstance, translationFromIp.getLocalAddr(0));
// XGpu2Rtds_Set_doorbell_offset(&xInstance, doorbellOffset);
// XGpu2Rtds_Set_data_offset(&xInstance, dataOffset);
// XGpu2Rtds_Set_frame_size(&xInstance, frameSize);
// // Prepare memory with all zeroes
// auto translationFromProcess = mm.getTranslationFromProcess(mem.getAddrSpaceId());
// auto memory = reinterpret_cast<void*>(translationFromProcess.getLocalAddr(0));
// memset(memory, 0, mem.getSize());
// // Start IP
// return start();
//}
//bool
//Gpu2Rtds::updateStatus()
//{
// if (not XGpu2Rtds_Get_status_vld(&xInstance))
// return false;
// status.value = XGpu2Rtds_Get_status(&xInstance);
// return true;
//}
size_t
Gpu2Rtds::getMaxFrameSize()
{
*registerFrameSize = 0;
start();
while (not isFinished());
while (not registerStatusCtrl->status_ap_vld);
axilite_reg_status_t status = *registerStatus;
// logger->debug("(*registerStatus).max_frame_size: {}", (*registerStatus).max_frame_size);
// logger->debug("status.max_frame_size: {}", status.max_frame_size);
// assert(status.max_frame_size == (*registerStatus).max_frame_size);
return status.max_frame_size;
}
//void
//Gpu2Rtds::dumpDoorbell(uint32_t doorbellRegister) const
//{
// auto &doorbell = reinterpret_cast<reg_doorbell_t&>(doorbellRegister);
// logger->info("Doorbell register: {:#08x}", doorbell.value);
// logger->info(" Valid: {}", (doorbell.is_valid ? "yes" : "no"));
// logger->info(" Count: {}", doorbell.count);
// logger->info(" Seq. number: {}", (int) doorbell.seq_nr);
//}
static char n[] = "gpu2rtds";
static char d[] = "HLS Gpu2Rtds IP";
static char v[] = "acs.eonerc.rwth-aachen.de:hls:gpu2rtds:";
static NodePlugin<Gpu2Rtds, n, d, v> p;

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/* GPU2RTDS IP core
*
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Daniel Krebs <github@daniel-krebs.net>
* SPDX-License-Identifier: Apache-2.0
*/
#include <unistd.h>
#include <cstring>
#include <villas/log.hpp>
#include <villas/memory_manager.hpp>
#include <villas/fpga/ips/rtds2gpu.hpp>
using namespace villas::fpga::ip;
bool Rtds2Gpu::init()
{
Hls::init();
xInstance.IsReady = XIL_COMPONENT_IS_READY;
xInstance.Ctrl_BaseAddress = getBaseAddr(registerMemory);
status.value = 0;
started = false;
// maxFrameSize = getMaxFrameSize();
maxFrameSize = 16;
logger->info("Max. frame size supported: {}", maxFrameSize);
return true;
}
void Rtds2Gpu::dump(spdlog::level::level_enum logLevel)
{
const auto baseaddr = XRtds2gpu_Get_baseaddr(&xInstance);
const auto data_offset = XRtds2gpu_Get_data_offset(&xInstance);
const auto doorbell_offset = XRtds2gpu_Get_doorbell_offset(&xInstance);
const auto frame_size = XRtds2gpu_Get_frame_size(&xInstance);
logger->log(logLevel, "Rtds2Gpu registers (IP base {:#x}):", xInstance.Ctrl_BaseAddress);
logger->log(logLevel, " Base address (bytes): {:#x}", baseaddr);
logger->log(logLevel, " Doorbell offset (bytes): {:#x}", doorbell_offset);
logger->log(logLevel, " Data offset (bytes): {:#x}", data_offset);
logger->log(logLevel, " Frame size (words): {:#x}", frame_size);
logger->log(logLevel, " Status: {:#x}", status.value);
logger->log(logLevel, " Running: {}", (status.is_running ? "yes" : "no"));
logger->log(logLevel, " Frame too short: {}", (status.frame_too_short ? "yes" : "no"));
logger->log(logLevel, " Frame too long: {}", (status.frame_too_long ? "yes" : "no"));
logger->log(logLevel, " Frame size invalid: {}", (status.invalid_frame_size ? "yes" : "no"));
logger->log(logLevel, " Last count: {}", (int) status.last_count);
logger->log(logLevel, " Last seq. number: {}", (int) status.last_seq_nr);
logger->log(logLevel, " Max. frame size: {}", (int) status.max_frame_size);
}
bool Rtds2Gpu::startOnce(const MemoryBlock &mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset)
{
auto &mm = MemoryManager::get();
if (frameSize > maxFrameSize) {
logger->error("Requested frame size of {} exceeds max. frame size of {}",
frameSize, maxFrameSize);
return false;
}
auto translationFromIp = mm.getTranslation(
getMasterAddrSpaceByInterface(axiInterface),
mem.getAddrSpaceId());
// Set address of memory block in HLS IP
XRtds2gpu_Set_baseaddr(&xInstance, translationFromIp.getLocalAddr(0));
XRtds2gpu_Set_doorbell_offset(&xInstance, doorbellOffset);
XRtds2gpu_Set_data_offset(&xInstance, dataOffset);
XRtds2gpu_Set_frame_size(&xInstance, frameSize);
// Prepare memory with all zeroes
auto translationFromProcess = mm.getTranslationFromProcess(mem.getAddrSpaceId());
auto memory = reinterpret_cast<void*>(translationFromProcess.getLocalAddr(0));
memset(memory, 0, mem.getSize());
// Start IP
return start();
}
bool Rtds2Gpu::updateStatus()
{
if (not XRtds2gpu_Get_status_vld(&xInstance))
return false;
status.value = XRtds2gpu_Get_status(&xInstance);
return true;
}
size_t Rtds2Gpu::getMaxFrameSize()
{
XRtds2gpu_Set_frame_size(&xInstance, 0);
start();
while (not isFinished());
updateStatus();
return status.max_frame_size;
}
void Rtds2Gpu::dumpDoorbell(uint32_t doorbellRegister) const
{
auto &doorbell = reinterpret_cast<reg_doorbell_t&>(doorbellRegister);
logger->info("Doorbell register: {:#08x}", doorbell.value);
logger->info(" Valid: {}", doorbell.is_valid ? "yes" : "no");
logger->info(" Count: {}", (int) doorbell.count);
logger->info(" Seq. number: {}", (int) doorbell.seq_nr);
}
static char n[] = "Rtds2Gpu";
static char d[] = "HLS RTDS2GPU IP";
static char v[] = "acs.eonerc.rwth-aachen.de:hls:rtds2gpu:";
static NodePlugin<Rtds2Gpu, n, d, v> f;

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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.3
// SPDX-FileCopyrightText: 1986 Xilinx, Inc. All Rights Reserved.
// SPDX-License-Identifier: Apache-2.0
// ==============================================================
/***************************** Include Files *********************************/
#include <villas/fpga/ips/rtds2gpu/xrtds2gpu.h>
/************************** Function Implementation *************************/
#ifndef __linux__
int XRtds2gpu_CfgInitialize(XRtds2gpu *InstancePtr, XRtds2gpu_Config *ConfigPtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
InstancePtr->Ctrl_BaseAddress = ConfigPtr->Ctrl_BaseAddress;
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
return XST_SUCCESS;
}
#endif
void XRtds2gpu_Start(XRtds2gpu *InstancePtr) {
u32 Data;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_AP_CTRL) & 0x80;
XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_AP_CTRL, Data | 0x01);
}
u32 XRtds2gpu_IsDone(XRtds2gpu *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_AP_CTRL);
return (Data >> 1) & 0x1;
}
u32 XRtds2gpu_IsIdle(XRtds2gpu *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_AP_CTRL);
return (Data >> 2) & 0x1;
}
u32 XRtds2gpu_IsReady(XRtds2gpu *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_AP_CTRL);
// Check ap_start to see if the pcore is ready for next input
return !(Data & 0x1);
}
void XRtds2gpu_EnableAutoRestart(XRtds2gpu *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_AP_CTRL, 0x80);
}
void XRtds2gpu_DisableAutoRestart(XRtds2gpu *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_AP_CTRL, 0);
}
void XRtds2gpu_Set_baseaddr(XRtds2gpu *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_BASEADDR_DATA, Data);
}
u32 XRtds2gpu_Get_baseaddr(XRtds2gpu *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_BASEADDR_DATA);
return Data;
}
void XRtds2gpu_Set_data_offset(XRtds2gpu *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_DATA_OFFSET_DATA, Data);
}
u32 XRtds2gpu_Get_data_offset(XRtds2gpu *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_DATA_OFFSET_DATA);
return Data;
}
void XRtds2gpu_Set_doorbell_offset(XRtds2gpu *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_DOORBELL_OFFSET_DATA, Data);
}
u32 XRtds2gpu_Get_doorbell_offset(XRtds2gpu *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_DOORBELL_OFFSET_DATA);
return Data;
}
void XRtds2gpu_Set_frame_size(XRtds2gpu *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_FRAME_SIZE_DATA, Data);
}
u32 XRtds2gpu_Get_frame_size(XRtds2gpu *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_FRAME_SIZE_DATA);
return Data;
}
u32 XRtds2gpu_Get_status(XRtds2gpu *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_STATUS_DATA);
return Data;
}
u32 XRtds2gpu_Get_status_vld(XRtds2gpu *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_STATUS_CTRL);
return Data & 0x1;
}
void XRtds2gpu_InterruptGlobalEnable(XRtds2gpu *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_GIE, 1);
}
void XRtds2gpu_InterruptGlobalDisable(XRtds2gpu *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_GIE, 0);
}
void XRtds2gpu_InterruptEnable(XRtds2gpu *InstancePtr, u32 Mask) {
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Register = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_IER);
XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_IER, Register | Mask);
}
void XRtds2gpu_InterruptDisable(XRtds2gpu *InstancePtr, u32 Mask) {
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Register = XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_IER);
XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_IER, Register & (~Mask));
}
void XRtds2gpu_InterruptClear(XRtds2gpu *InstancePtr, u32 Mask) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XRtds2gpu_WriteReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_ISR, Mask);
}
u32 XRtds2gpu_InterruptGetEnabled(XRtds2gpu *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_IER);
}
u32 XRtds2gpu_InterruptGetStatus(XRtds2gpu *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return XRtds2gpu_ReadReg(InstancePtr->Ctrl_BaseAddress, XRTDS2GPU_CTRL_ADDR_ISR);
}

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/* AXI Stream interconnect related helper functions
*
* These functions present a simpler interface to Xilinx' AXI Stream switch driver (XAxis_Switch_*)
*
* Author: Steffen Vogel <post@steffenvogel.de>
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Steffen Vogel <post@steffenvogel.de>
* SPDX-License-Identifier: Apache-2.0
*/
#include <jansson.h>
#include <xilinx/xaxis_switch.h>
#include <villas/exceptions.hpp>
#include <villas/fpga/ips/switch.hpp>
namespace villas {
namespace fpga {
namespace ip {
bool AxiStreamSwitch::init()
{
if (XAxisScr_CfgInitialize(&xSwitch, &xConfig, getBaseAddr(registerMemory)) != XST_SUCCESS) {
logger->error("Cannot initialize switch");
return false;
}
// Disable all masters
XAxisScr_RegUpdateDisable(&xSwitch);
XAxisScr_MiPortDisableAll(&xSwitch);
XAxisScr_RegUpdateEnable(&xSwitch);
for (auto& [masterName, masterPort] : portsMaster) {
// Initialize internal mapping
portMapping[masterName] = PORT_DISABLED;
// Each slave port may be internally routed to a master port
for (auto& [slaveName, slavePort] : portsSlave) {
(void) slaveName;
streamGraph.addDefaultEdge(slavePort->getIdentifier(),
masterPort->getIdentifier());
}
}
return true;
}
void AxiStreamSwitch::printConfig() const {
u32 MiPortAddr;
u32 RegValue;
u8 Enable;
logger->info(
"Switch configuration: {} Master Interfaces, {} Slave Interfaces",
xConfig.MaxNumMI, xConfig.MaxNumSI);
for (int i = 0; i < xConfig.MaxNumMI; i++) {
/* Calculate MI port address to be enabled */
MiPortAddr = XAXIS_SCR_MI_MUX_START_OFFSET + 4 * i;
/* Read MI port data */
RegValue = XAxisScr_ReadReg(xSwitch.Config.BaseAddress, MiPortAddr);
/* Fetch enable bit */
Enable = RegValue >> XAXIS_SCR_MI_X_DISABLE_SHIFT;
/* Fetch SI value */
RegValue &= XAXIS_SCR_MI_X_MUX_MASK;
logger->info("Master Interface {}: {} (enabled: {})", i, RegValue, Enable);
}
}
bool AxiStreamSwitch::connectInternal(const std::string &portSlave,
const std::string &portMaster)
{
// Check if slave port exists
try {
getSlavePort(portSlave);
} catch (const std::out_of_range&) {
logger->error("Switch doesn't have a slave port named '{}'", portSlave);
return false;
}
// Check if master port exists
try {
getMasterPort(portMaster);
} catch (const std::out_of_range&) {
logger->error("Switch doesn't have a master port named '{}'", portMaster);
return false;
}
if (portSlave.substr(0, 1) != "S" or
portMaster.substr(0, 1) != "M") {
logger->error("sanity check failed: master {} slave {}",
portMaster, portSlave);
return false;
}
if (portMapping[portMaster] == portSlave) {
logger->debug("Ports already connected (slave {} to master {}",
portSlave, portMaster);
return true;
}
for (auto [master, slave] : portMapping) {
if (slave == portSlave) {
logger->warn("Slave {} has already been connected to master {}. "
"Disabling master {}.",
slave, master, master);
XAxisScr_RegUpdateDisable(&xSwitch);
XAxisScr_MiPortDisable(&xSwitch, portNameToNum(master));
XAxisScr_RegUpdateEnable(&xSwitch);
portMapping[master] = PORT_DISABLED;
}
}
// Reconfigure switch
XAxisScr_RegUpdateDisable(&xSwitch);
XAxisScr_MiPortEnable(&xSwitch, portNameToNum(portMaster), portNameToNum(portSlave));
XAxisScr_RegUpdateEnable(&xSwitch);
portMapping[portMaster] = portSlave;
logger->debug("Connect slave {} to master {}", portSlave, portMaster);
return true;
}
int AxiStreamSwitch::portNameToNum(const std::string &portName)
{
const std::string number = portName.substr(1, 2);
return std::stoi(number);
}
void AxiStreamSwitchFactory::parse(Core &ip, json_t *cfg)
{
NodeFactory::parse(ip, cfg);
auto logger = getLogger();
auto &axiSwitch = dynamic_cast<AxiStreamSwitch&>(ip);
int num_si, num_mi;
json_error_t err;
auto ret = json_unpack_ex(cfg, &err, 0, "{ s: { s: i, s: i } }",
"parameters",
"num_si", &num_si,
"num_mi", &num_mi
);
if (ret != 0)
throw ConfigError(cfg, err, "", "Cannot parse switch config");
axiSwitch.xConfig.MaxNumMI = num_mi;
axiSwitch.xConfig.MaxNumSI = num_si;
}
static AxiStreamSwitchFactory f;
} // namespace ip
} // namespace fpga
} // namespace villas

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/* Timer related helper functions
*
* These functions present a simpler interface to Xilinx' Timer Counter driver (XTmrCtr_*)
*
* Author: Steffen Vogel <post@steffenvogel.de>
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Steffen Vogel <post@steffenvogel.de>
* SPDX-License-Identifier: Apache-2.0
*/
#include <cstdint>
#include <xilinx/xtmrctr.h>
#include <villas/fpga/ips/timer.hpp>
#include <villas/fpga/ips/intc.hpp>
using namespace villas::fpga::ip;
bool Timer::init()
{
XTmrCtr_Config xtmr_cfg;
xtmr_cfg.SysClockFreqHz = getFrequency();
XTmrCtr_CfgInitialize(&xTmr, &xtmr_cfg, getBaseAddr(registerMemory));
XTmrCtr_InitHw(&xTmr);
if (irqs.find(irqName) == irqs.end()) {
logger->error("IRQ '{}' not found but required", irqName);
return false;
}
// Disable so we don't receive any stray interrupts
irqs[irqName].irqController->disableInterrupt(irqs[irqName]);
return true;
}
bool Timer::start(uint32_t ticks)
{
irqs[irqName].irqController->enableInterrupt(irqs[irqName], false);
XTmrCtr_SetOptions(&xTmr, 0, XTC_EXT_COMPARE_OPTION | XTC_DOWN_COUNT_OPTION);
XTmrCtr_SetResetValue(&xTmr, 0, ticks);
XTmrCtr_Start(&xTmr, 0);
return true;
}
bool Timer::wait()
{
int count = irqs[irqName].irqController->waitForInterrupt(irqs[irqName]);
irqs[irqName].irqController->disableInterrupt(irqs[irqName]);
return (count == 1);
}
uint32_t Timer::remaining()
{
return XTmrCtr_GetValue(&xTmr, 0);
}
static char n[] = "timer";
static char d[] = "Xilinx's programmable timer / counter";
static char v[] = "xilinx.com:ip:axi_timer:";
static CorePlugin<Timer, n, d, v> f;

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/* Memory managment.
*
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#include <sys/mman.h>
#include <unistd.h>
#include <villas/memory.hpp>
using namespace villas;
bool
HostRam::free(void* addr, size_t length)
{
return munmap(addr, length) == 0;
}
void*
HostRam::allocate(size_t length, int flags)
{
const int mmap_flags = flags | MAP_PRIVATE | MAP_ANONYMOUS | MAP_32BIT;
const int mmap_protection = PROT_READ | PROT_WRITE;
return mmap(nullptr, length, mmap_protection, mmap_flags, 0, 0);
}

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/* An IP node.
*
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#include <jansson.h>
#include <map>
#include <stdexcept>
#include <villas/exceptions.hpp>
#include <villas/utils.hpp>
#include <villas/fpga/card.hpp>
#include <villas/fpga/ips/switch.hpp>
#include <villas/fpga/node.hpp>
using namespace villas::fpga::ip;
StreamGraph Node::streamGraph;
void NodeFactory::parse(Core &ip, json_t *cfg) {
CoreFactory::parse(ip, cfg);
auto &Node = dynamic_cast<ip::Node &>(ip);
auto logger = getLogger();
json_t *json_ports = json_object_get(cfg, "ports");
if (json_ports && json_is_array(json_ports)) {
size_t index;
json_t *json_port;
json_array_foreach(json_ports, index, json_port) {
if (not json_is_object(json_port))
throw ConfigError(json_port, "", "Port {} is not an object", index);
const char *role_raw, *target_raw, *name_raw;
json_error_t err;
int ret =
json_unpack_ex(json_port, &err, 0, "{ s: s, s: s, s: s }", "role",
&role_raw, "target", &target_raw, "name", &name_raw);
if (ret != 0)
throw ConfigError(json_port, err, "", "Cannot parse port {}", index);
const auto tokens = utils::tokenize(target_raw, ":");
if (tokens.size() != 2)
throw ConfigError(json_port, err, "",
"Cannot parse 'target' of port {}", index);
const std::string role(role_raw);
const bool isMaster = (role == "master" or role == "initiator");
auto thisVertex = Node::streamGraph.getOrCreateStreamVertex(
ip.getInstanceName(), name_raw, isMaster);
auto connectedVertex = Node::streamGraph.getOrCreateStreamVertex(
tokens[0], tokens[1], not isMaster);
if (isMaster) {
Node::streamGraph.addDefaultEdge(thisVertex->getIdentifier(),
connectedVertex->getIdentifier());
Node.portsMaster[name_raw] = thisVertex;
} else // Slave
Node.portsSlave[name_raw] = thisVertex;
}
} else if (json_ports) {
throw ConfigError(json_ports, "", "IP port list of {} must be an array",
ip.getInstanceName());
}
}
std::pair<std::string, std::string> Node::getLoopbackPorts() const {
for (auto &[masterName, masterVertex] : portsMaster) {
for (auto &[slaveName, slaveVertex] : portsSlave) {
StreamGraph::Path path;
if (streamGraph.getPath(masterVertex->getIdentifier(),
slaveVertex->getIdentifier(), path)) {
return {masterName, slaveName};
}
}
}
return {"", ""};
}
bool Node::connect(const StreamVertex &from, const StreamVertex &to) {
if (from.nodeName != getInstanceName()) {
logger->error("Cannot connect from a foreign StreamVertex: {}", from);
return false;
}
StreamGraph::Path path;
if (not streamGraph.getPath(from.getIdentifier(), to.getIdentifier(), path)) {
logger->error("No path from {} to {}", from, to);
return false;
}
if (path.size() == 0) {
return true;
}
auto currentEdge = path.begin();
auto firstEdge = streamGraph.getEdge(*currentEdge);
auto firstHopNode = streamGraph.getVertex(firstEdge->getVertexTo());
auto nextHopNode = firstHopNode;
// Check if next hop is an internal connection
if (firstHopNode->nodeName == getInstanceName()) {
if (not connectInternal(from.portName, firstHopNode->portName)) {
logger->error("Making internal connection from {} to {} failed", from,
*firstHopNode);
return false;
}
// We have to advance to next hop
if (++currentEdge == path.end())
return true; // Arrived at the end of path
auto secondEdge = streamGraph.getEdge(*currentEdge);
auto secondHopNode = streamGraph.getVertex(secondEdge->getVertexTo());
nextHopNode = secondHopNode;
}
auto nextHopNodeIp =
std::dynamic_pointer_cast<Node>(card->lookupIp(nextHopNode->nodeName));
if (nextHopNodeIp == nullptr) {
logger->error("Cannot find IP {}, this shouldn't happen!",
nextHopNode->nodeName);
return false;
}
return nextHopNodeIp->connect(*nextHopNode, to);
}
const StreamVertex &Node::getDefaultSlavePort() const {
logger->error("No default slave port available");
throw std::exception();
}
const StreamVertex &Node::getDefaultMasterPort() const {
logger->error("No default master port available");
throw std::exception();
}
bool Node::loopbackPossible() const {
auto ports = getLoopbackPorts();
return (not ports.first.empty()) and (not ports.second.empty());
}
bool Node::connectInternal(const std::string &slavePort,
const std::string &masterPort) {
(void)slavePort;
(void)masterPort;
logger->warn("This IP doesn't implement an internal connection");
return false;
}
bool Node::connectLoopback() {
auto ports = getLoopbackPorts();
const auto &portMaster = portsMaster[ports.first];
const auto &portSlave = portsSlave[ports.second];
logger->debug("master port: {}", ports.first);
logger->debug("slave port: {}", ports.second);
return connect(*portMaster, *portSlave);
}

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/* FPGA pciecard.
*
* Author: Steffen Vogel <post@steffenvogel.de>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#include <string>
#include <memory>
#include <utility>
#include <fmt/ostream.h>
#include <villas/exceptions.hpp>
#include <villas/memory.hpp>
#include <villas/kernel/pci.hpp>
#include <villas/kernel/vfio_container.hpp>
#include <villas/fpga/core.hpp>
#include <villas/fpga/node.hpp>
#include <villas/fpga/pcie_card.hpp>
using namespace villas;
using namespace villas::fpga;
// Instantiate factory to register
static PCIeCardFactory PCIeCardFactoryInstance;
static const kernel::pci::Device defaultFilter((kernel::pci::Id(FPGA_PCI_VID_XILINX, FPGA_PCI_PID_VFPGA)));
std::shared_ptr<PCIeCard>
PCIeCardFactory::make(json_t *json_card, std::string card_name,
std::shared_ptr<kernel::vfio::Container> vc,
const std::filesystem::path &searchPath) {
auto logger = getStaticLogger();
json_t *json_ips = nullptr;
json_t *json_paths = nullptr;
const char *pci_slot = nullptr;
const char *pci_id = nullptr;
int do_reset = 0;
int affinity = 0;
int polling = 0;
json_error_t err;
int ret = json_unpack_ex(
json_card, &err, 0, "{ s: o, s?: i, s?: b, s?: s, s?: s, s?: b, s?: o }",
"ips", &json_ips, "affinity", &affinity, "do_reset", &do_reset, "slot",
&pci_slot, "id", &pci_id, "polling", &polling, "paths", &json_paths);
if (ret != 0)
throw ConfigError(json_card, err, "", "Failed to parse card");
auto card = std::shared_ptr<PCIeCard>(make());
// Populate generic properties
card->name = std::string(card_name);
card->vfioContainer = vc;
card->affinity = affinity;
card->doReset = do_reset != 0;
card->polling = (polling != 0);
kernel::pci::Device filter = defaultFilter;
if (pci_id)
filter.id = kernel::pci::Id(pci_id);
if (pci_slot)
filter.slot = kernel::pci::Slot(pci_slot);
// Search for FPGA card
card->pdev = kernel::pci::DeviceList::getInstance()->lookupDevice(filter);
if (!card->pdev) {
logger->warn("Failed to find PCI device");
return nullptr;
}
if (not card->init()) {
logger->warn("Cannot start FPGA card {}", card_name);
return nullptr;
}
// Load IPs from a separate json file
if (!json_is_string(json_ips)) {
logger->debug("FPGA IP cores config item is not a string.");
throw ConfigError(json_ips, "node-config-fpga-ips",
"FPGA IP cores config item is not a string.");
}
if (!searchPath.empty()) {
std::filesystem::path json_ips_path =
searchPath / json_string_value(json_ips);
logger->debug("searching for FPGA IP cors config at {}",
json_ips_path.string());
json_ips = json_load_file(json_ips_path.c_str(), 0, nullptr);
}
if (json_ips == nullptr) {
json_ips = json_load_file(json_string_value(json_ips), 0, nullptr);
logger->debug("searching for FPGA IP cors config at {}",
json_string_value(json_ips));
if (json_ips == nullptr) {
throw ConfigError(json_ips, "node-config-fpga-ips",
"Failed to find FPGA IP cores config");
}
}
if (not json_is_object(json_ips))
throw ConfigError(json_ips, "node-config-fpga-ips",
"FPGA IP core list must be an object!");
ip::CoreFactory::make(card.get(), json_ips);
if (card->ips.empty())
throw ConfigError(json_ips, "node-config-fpga-ips",
"Cannot initialize IPs of FPGA card {}", card_name);
if (not card->check())
throw RuntimeError("Checking of FPGA card {} failed", card_name);
// Additional static paths for AXI-Steram switch
if (json_paths != nullptr) {
if (not json_is_array(json_paths))
throw ConfigError(json_paths, err, "",
"Switch path configuration must be an array");
size_t i;
json_t *json_path;
json_array_foreach(json_paths, i, json_path) {
const char *from, *to;
int reverse = 0;
ret = json_unpack_ex(json_path, &err, 0, "{ s: s, s: s, s?: b }", "from",
&from, "to", &to, "reverse", &reverse);
if (ret != 0)
throw ConfigError(json_path, err, "",
"Cannot parse switch path config");
auto masterIpCore = card->lookupIp(from);
if (!masterIpCore)
throw ConfigError(json_path, "", "Unknown IP {}", from);
auto slaveIpCore = card->lookupIp(to);
if (!slaveIpCore)
throw ConfigError(json_path, "", "Unknown IP {}", to);
auto masterIpNode = std::dynamic_pointer_cast<ip::Node>(masterIpCore);
if (!masterIpNode)
throw ConfigError(json_path, "", "IP {} is not a streaming node", from);
auto slaveIpNode = std::dynamic_pointer_cast<ip::Node>(slaveIpCore);
if (!slaveIpNode)
throw ConfigError(json_path, "", "IP {} is not a streaming node", to);
if (not masterIpNode->connect(*slaveIpNode, reverse != 0))
throw ConfigError(json_path, "", "Failed to connect node {} to {}",
from, to);
}
}
// Deallocate JSON config
json_decref(json_ips);
return card;
}
PCIeCard::~PCIeCard()
{
}
bool PCIeCard::init()
{
logger = getLogger();
logger->info("Initializing FPGA card {}", name);
// Attach PCIe card to VFIO container
vfioDevice = vfioContainer->attachDevice(*pdev);
// Enable memory access and PCI bus mastering for DMA
if (not vfioDevice->pciEnable()) {
logger->error("Failed to enable PCI device");
return false;
}
// Reset system?
if (doReset) {
// Reset / detect PCI device
if (not vfioDevice->pciHotReset()) {
logger->error("Failed to reset PCI device");
return false;
}
if (not reset()) {
logger->error("Failed to reset FGPA card");
return false;
}
}
return true;
}

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/* Helper function for directly using VILLASfpga outside of VILLASnode
*
* Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
* SPDX-FileCopyrightText: 2022-2023 Steffen Vogel <post@steffenvogel.de>
* SPDX-FileCopyrightText: 2022-2023 Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
* SPDX-License-Identifier: Apache-2.0
*/
#include <csignal>
#include <iostream>
#include <vector>
#include <string>
#include <algorithm>
#include <jansson.h>
#include <regex>
#include <filesystem>
#include <CLI11.hpp>
#include <rang.hpp>
#include <villas/exceptions.hpp>
#include <villas/log.hpp>
#include <villas/utils.hpp>
#include <villas/utils.hpp>
#include <villas/fpga/card.hpp>
#include <villas/fpga/core.hpp>
#include <villas/fpga/ips/aurora_xilinx.hpp>
#include <villas/fpga/ips/dino.hpp>
#include <villas/fpga/ips/dma.hpp>
#include <villas/fpga/ips/rtds.hpp>
#include <villas/fpga/utils.hpp>
#include <villas/fpga/vlnv.hpp>
using namespace villas;
static auto logger = villas::logging.get("streamer");
std::shared_ptr<std::vector<std::shared_ptr<fpga::ip::Node>>>
fpga::getAuroraChannels(std::shared_ptr<fpga::Card> card) {
auto aurora_channels =
std::make_shared<std::vector<std::shared_ptr<fpga::ip::Node>>>();
for (int i = 0; i < 4; i++) {
auto name = fmt::format("aurora_aurora_8b10b_ch{}", i);
auto id = fpga::ip::IpIdentifier("xilinx.com:ip:aurora_8b10b:", name);
auto aurora = std::dynamic_pointer_cast<fpga::ip::Node>(card->lookupIp(id));
if (aurora == nullptr) {
logger->error("No Aurora interface found on FPGA");
throw std::runtime_error("No Aurora interface found on FPGA");
}
aurora_channels->push_back(aurora);
}
return aurora_channels;
}
fpga::ConnectString::ConnectString(std::string &connectString, int maxPortNum)
: log(villas::logging.get("ConnectString")), maxPortNum(maxPortNum),
bidirectional(false), invert(false), srcType(ConnectType::LOOPBACK),
dstType(ConnectType::LOOPBACK), srcAsInt(-1), dstAsInt(-1) {
parseString(connectString);
}
void fpga::ConnectString::parseString(std::string& connectString)
{
if (connectString.empty())
return;
if (connectString == "loopback") {
logger->info("Connecting loopback");
srcType = ConnectType::LOOPBACK;
dstType = ConnectType::LOOPBACK;
bidirectional = true;
return;
}
static const std::regex regex("([0-9]+|stdin|stdout|pipe|dma|dino)([<\\->]+)("
"[0-9]+|stdin|stdout|pipe|dma|dino)");
std::smatch match;
if (!std::regex_match(connectString, match, regex) || match.size() != 4) {
logger->error("Invalid connect string: {}", connectString);
throw std::runtime_error("Invalid connect string");
}
if (match[2] == "<->") {
bidirectional = true;
} else if (match[2] == "<-") {
invert = true;
}
std::string srcStr = (invert ? match[3] : match[1]);
std::string dstStr = (invert ? match[1] : match[3]);
srcAsInt = portStringToInt(srcStr);
dstAsInt = portStringToInt(dstStr);
if (srcAsInt == -1) {
if (srcStr == "dino") {
srcType = ConnectType::DINO;
} else if (srcStr == "dma" || srcStr == "pipe" || srcStr == "stdin" ||
srcStr == "stdout") {
srcType = ConnectType::DMA;
} else {
throw std::runtime_error("Invalid source type");
}
} else {
srcType = ConnectType::AURORA;
}
if (dstAsInt == -1) {
if (dstStr == "dino") {
dstType = ConnectType::DINO;
} else if (dstStr == "dma" || dstStr == "pipe" || dstStr == "stdin" ||
dstStr == "stdout") {
dstType = ConnectType::DMA;
} else {
throw std::runtime_error("Invalid destination type");
}
} else {
dstType = ConnectType::AURORA;
}
}
int fpga::ConnectString::portStringToInt(std::string &str) const
{
if (str == "stdin" || str == "stdout" || str == "pipe" || str == "dma" ||
str == "dino") {
return -1;
} else {
const int port = std::stoi(str);
if (port > maxPortNum || port < 0)
throw std::runtime_error("Invalid port number");
return port;
}
}
// parses a string like "1->2" or "1<->stdout" and configures the crossbar accordingly
void fpga::ConnectString::configCrossBar(
std::shared_ptr<villas::fpga::Card> card) const {
auto dma = std::dynamic_pointer_cast<fpga::ip::Dma>(
card->lookupIp(fpga::Vlnv("xilinx.com:ip:axi_dma:")));
if (dma == nullptr) {
logger->error("No DMA found on FPGA ");
throw std::runtime_error("No DMA found on FPGA");
}
if (isDmaLoopback()) {
log->info("Configuring DMA loopback");
dma->connectLoopback();
return;
}
auto aurora_channels = getAuroraChannels(card);
auto dinoDac = std::dynamic_pointer_cast<fpga::ip::DinoDac>(
card->lookupIp(fpga::Vlnv("xilinx.com:module_ref:dinoif_dac:")));
if (dinoDac == nullptr) {
logger->error("No Dino DAC found on FPGA ");
throw std::runtime_error("No Dino DAC found on FPGA");
}
auto dinoAdc = std::dynamic_pointer_cast<fpga::ip::DinoAdc>(
card->lookupIp(fpga::Vlnv("xilinx.com:module_ref:dinoif_fast:")));
if (dinoAdc == nullptr) {
logger->error("No Dino ADC found on FPGA ");
throw std::runtime_error("No Dino ADC found on FPGA");
}
log->info("Connecting {} to {}, {}directional",
(srcAsInt == -1 ? connectTypeToString(srcType)
: std::to_string(srcAsInt)),
(dstAsInt == -1 ? connectTypeToString(dstType)
: std::to_string(dstAsInt)),
(bidirectional ? "bi" : "uni"));
std::shared_ptr<fpga::ip::Node> src;
std::shared_ptr<fpga::ip::Node> dest;
if (srcType == ConnectType::DINO) {
src = dinoAdc;
} else if (srcType == ConnectType::DMA) {
src = dma;
} else {
src = (*aurora_channels)[srcAsInt];
}
if (dstType == ConnectType::DINO) {
dest = dinoDac;
} else if (dstType == ConnectType::DMA) {
dest = dma;
} else {
dest = (*aurora_channels)[dstAsInt];
}
src->connect(src->getDefaultMasterPort(), dest->getDefaultSlavePort());
if (bidirectional) {
if (srcType == ConnectType::DINO) {
src = dinoDac;
}
if (dstType == ConnectType::DINO) {
dest = dinoAdc;
}
dest->connect(dest->getDefaultMasterPort(), src->getDefaultSlavePort());
}
}
void fpga::setupColorHandling()
{
// Handle Control-C nicely
struct sigaction sigIntHandler;
sigIntHandler.sa_handler = [](int){
std::cout << std::endl << rang::style::reset << rang::fgB::red;
std::cout << "Control-C detected, exiting..." << rang::style::reset << std::endl;
std::exit(1); // Will call the correct exit func, no unwinding of the stack though
};
sigemptyset(&sigIntHandler.sa_mask);
sigIntHandler.sa_flags = 0;
sigaction(SIGINT, &sigIntHandler, nullptr);
// Reset color if exiting not by signal
std::atexit([](){
std::cout << rang::style::reset;
});
}
std::shared_ptr<fpga::Card>
fpga::createCard(json_t *config, const std::filesystem::path &searchPath,
std::shared_ptr<kernel::vfio::Container> vfioContainer,
std::string card_name) {
auto configDir = std::filesystem::path().parent_path();
const char *interfaceName;
json_error_t err;
logger->info("Found config for FPGA card {}", card_name);
int ret =
json_unpack_ex(config, &err, 0, "{s: s}", "interface", &interfaceName);
if (ret) {
throw ConfigError(config, err, "interface",
"Failed to parse interface name for card {}", card_name);
}
std::string interfaceNameStr(interfaceName);
if (interfaceNameStr == "pcie") {
auto card = fpga::PCIeCardFactory::make(config, std::string(card_name),
vfioContainer, searchPath);
if (card) {
return card;
}
return nullptr;
} else if (interfaceNameStr == "platform") {
throw RuntimeError("Platform interface not implemented yet");
} else {
throw RuntimeError("Unknown interface type {}", interfaceNameStr);
}
}
int fpga::createCards(json_t *config,
std::list<std::shared_ptr<fpga::Card>> &cards,
const std::filesystem::path &searchPath,
std::shared_ptr<kernel::vfio::Container> vfioContainer) {
int numFpgas = 0;
if (vfioContainer == nullptr) {
vfioContainer = std::make_shared<kernel::vfio::Container>();
}
auto configDir = std::filesystem::path().parent_path();
json_t *fpgas = json_object_get(config, "fpgas");
if (fpgas == nullptr) {
logger->error("No section 'fpgas' found in config");
exit(1);
}
const char *card_name;
json_t *json_card;
std::shared_ptr<fpga::Card> card;
json_object_foreach(fpgas, card_name, json_card) {
card = createCard(json_card, searchPath, vfioContainer, card_name);
if (card != nullptr) {
cards.push_back(card);
numFpgas++;
}
}
return numFpgas;
}
int fpga::createCards(json_t *config,
std::list<std::shared_ptr<fpga::Card>> &cards,
const std::string &searchPath,
std::shared_ptr<kernel::vfio::Container> vfioContainer) {
const auto fsPath = std::filesystem::path(searchPath);
return createCards(config, cards, fsPath, vfioContainer);
}
std::shared_ptr<fpga::Card> fpga::setupFpgaCard(const std::string &configFile,
const std::string &fpgaName) {
auto configDir = std::filesystem::path(configFile).parent_path();
// Parse FPGA configuration
FILE *f = fopen(configFile.c_str(), "r");
if (!f)
throw RuntimeError("Cannot open config file: {}", configFile);
json_t *json = json_loadf(f, 0, nullptr);
if (!json) {
logger->error("Cannot parse JSON config");
fclose(f);
throw RuntimeError("Cannot parse JSON config");
}
fclose(f);
// Create all FPGA card instances using the corresponding plugin
auto cards = std::list<std::shared_ptr<fpga::Card>>();
createCards(json, cards, configDir);
std::shared_ptr<fpga::Card> card = nullptr;
for (auto &fpgaCard : cards) {
if (fpgaCard->name == fpgaName) {
card = fpgaCard;
break;
}
}
// Deallocate JSON config
json_decref(json);
if (!card)
throw RuntimeError("FPGA card {} not found in config or not working",
fpgaName);
return card;
}
std::unique_ptr<fpga::BufferedSampleFormatter> fpga::getBufferedSampleFormatter(
const std::string &format,
size_t bufSizeInSamples)
{
if (format == "long") {
return std::make_unique<fpga::BufferedSampleFormatterLong>(bufSizeInSamples);
} else if (format == "short") {
return std::make_unique<fpga::BufferedSampleFormatterShort>(bufSizeInSamples);
} else {
throw RuntimeError("Unknown output format '{}'", format);
}
}

60
fpga/lib/vlnv.cpp Normal file
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/* Vendor, Library, Name, Version (VLNV) tag
*
* Author: Steffen Vogel <post@steffenvogel.de>
* SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#include <string>
#include <sstream>
#include <villas/fpga/vlnv.hpp>
using namespace villas::fpga;
bool
Vlnv::operator==(const Vlnv &other) const
{
// If a field is empty, it means wildcard matching everything
const bool vendorWildcard = vendor.empty() or other.vendor.empty();
const bool libraryWildcard = library.empty() or other.library.empty();
const bool nameWildcard = name.empty() or other.name.empty();
const bool versionWildcard = version.empty() or other.version.empty();
const bool vendorMatch = vendorWildcard or vendor == other.vendor;
const bool libraryMatch = libraryWildcard or library == other.library;
const bool nameMatch = nameWildcard or name == other.name;
const bool versionMatch = versionWildcard or version == other.version;
return vendorMatch and libraryMatch and nameMatch and versionMatch;
}
void
Vlnv::parseFromString(std::string vlnv)
{
// Tokenize by delimiter
std::stringstream sstream(vlnv);
std::getline(sstream, vendor, delimiter);
std::getline(sstream, library, delimiter);
std::getline(sstream, name, delimiter);
std::getline(sstream, version, delimiter);
// Represent wildcard internally as empty string
if (vendor == "*") vendor = "";
if (library == "*") library = "";
if (name == "*") name = "";
if (version == "*") version = "";
}
std::string
Vlnv::toString() const
{
std::stringstream stream;
std::string string;
stream << *this;
stream >> string;
return string;
}

13
fpga/libvillas-fpga.pc.in Normal file
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# SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0
prefix=@CMAKE_INSTALL_PREFIX@
exec_prefix=${prefix}
includedir=${prefix}/include
libdir=${exec_prefix}/lib
Name: @PROJECT_NAME@
Description: @CPACK_PACKAGE_DESCRIPTION_SUMMARY@
URL: @PROJECT_URL@
Version: @PROJECT_VERSION_MAJOR@.@PROJECT_VERSION_MINOR@.@PROJECT_VERSION_PATCH@
Cflags: -I${includedir}

196
fpga/past-commits.txt Normal file
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SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
SPDX-License-Identifier: Apache-2.0
I, Niklas Eiling hereby sign-off-by all of my past commits to this repo subject to the Developer Certificate of Origin (DCO), Version 1.1. In the past I have used emails: niklas.eiling@eonerc.rwth-aachen.de
b22a741785f38ee5f86d46c287e523ddd8f94a46 update contact and copyright notice
9f43181c688bac915f6c10a3318c6bedb455b8fb add villas-fpga-xbar-select; improve DMA parameters in ips/dma
092ccfe8b232a6e41dee7e3a0faba38aff58ab2d fix villas-fpga-cat interpreting floats wrong
4b8cca9420b7dda0f7d8f9c24bff4a9ab07db0cf clean up and comment ips/dma.cpp
749406976f595d8f25ab862d44dfa18126b18c86 villas-fpga-cat: fix double value being constructed wrong
edc36f793afe3152a754b707e3f4531b0172cbfc ips/dma: comment debug outputs to improve villas-fpga-cat performance fix rebase artifacts
abf63eefa972606f55291b12767fa2fe07711572 add villas-fpga-cat app that outputs a stream of data
833acb8fab609e71570a62899b78d994b722dfc2 move helper functions from villas-fpga-pipe into separate file
ceddd1ce96fabcc8d6b14ab5e780d31631ca283f Merge branch 'fix-gitlabyml' into 'master'
b2746556210784fc06f65858b169816d1e0db748 fix image reference in gitlab.yml
ca970e8c33c013f7416cc3ee8c1ce9a6482f5c7b migrate dockerfile to rocky9
75d80447afb10f01dc90b9afa518425f4c25f8b8 ips/dma: fix hasScatterGather using wrong member variable; Throw error used on unconfigured Dma
8db35907dd306422bcda5ec395a383b04e9c83b7 ips: fix some formatting issues
a16468c61c83a20bd223a05eeb3187954e35b98d ips/dma: use NodeFactory's configureJson to setup memory graph
1ae00c1f59413a6c726b7c34d839c56fdc13e281 ips/dma: use json_unpack
da10c4db59344c9ac1a387cb408d4bc57f36ec46 add card config option "polling" to configure polling mode in IP cores; add json parsing of hwdef to dma IP core to replace hardcoded DMA settings.
4db2153330af2c830b258152f3badbd4ecc51b61 ip/dma: fix spelling
a4120eda2d327aa537fa874885c200c858202fcc ips/dma: acknowledge interrupts in DMA controller and correctly set coalescing parameter.
277858f881499821334f0f27303fea8380b549d6 make dma.cpp use interrupts instead of polling
---
I, Steffen Vogel hereby sign-off-by all of my past commits to this repo subject to the Developer Certificate of Origin (DCO), Version 1.1. In the past I have used emails: post@steffenvogel.de, post@steffenvogel.de
e256a94957294714d6bf645fa9c9f17253fa154e Merge branch 'fix-dockerfile' into 'master'
44fcb85aebeedc531b061d41c847eabbc8cee478 minor code-style fixes
c8b20ec18863091fe92d1913a329b0d54a03434f move VILLASnode configs to VILLASnode repo
69f63d9ef61f37628a11f6c4ff62675a2aa2d487 update VILLAScommon submodule
b13589aa55c0ad4e497daaaf122142b99095b966 add libxil as a submodule
1e9e46b35a872332d92b16ce6fe276655f8d2fc6 updated VILLAScommon submodule
f4e7fcdac329600de2a3838ab8d773c3a6910932 core: avoid reversing initialization order list
15a9ae0806a7618b80f635f1563e90a1c547aa94 dma: first successful test with scatter gather
9e8c4ef132d005d025a5d960531635a869eba8c1 adapt villas-fpga-pipe to new DMA code
ecb9fac96fb3bd24d59163c7a9c67f4a98dce019 update IPs config for new bitstream using MSI IRQs
c1749d052ab96c99d33efa6231c8c30f698120c3 dma: added second version of scatter-gather support
0b4bc73b0a897a8bbee501f977bfbe661a92ed31 update gitignore
1ef3952d62cd47177a9527ca6c67a0e3aad430be minor code style and comment fixes
d6ee75febcc7c41525c0a7722b160383a6988147 dma: throw exception in makeAccesibleFromVA instead of returning bool
09106c3a9c8b67d8b72a3680263ceab1fbc0780b fix script to reset PCIe card
dd03a196008cb7276de2bab4289320d12e6b3e97 remove useless includes
72d92a5223ec4ee95ac25169356894c0bfe92ef2 intc: fix VLNV for Niklas' new bistream
1a47f70281db2108629777c4d92d731802388fe9 aurora: fix names of AXI-S interfaces
b91e6d102dc68f491885bc37e925ed9ae3976bc0 fix coding style
3661b25532e0f10e4a24a66b9e54e743b4f92b65 remove old C code
a5a2dcf992ce9fa7b3f73a9ba585f010feb1b456 dma: start implementing scatter-gather support
b4d39159d5b28b59662efbb1a4976ab307af4783 add example config for VILLASnode integration
ae681cc3073ce90b459428ad5ed0bf06931aa756 remove broken symlink
afb45d88d15c63d5910de0c0864dc7d7fbffabdd add latest vc707 config
bfffd71b71a2b21ec88cad766baaa254d13a3273 remove last pieces of hardware submodule
3ccb99b9ecd5046765041bc4cfa8b1a4f8a02da5 bump libxil version requirement
3e61b1ef0d2abfe332bc3fa490afe91ec46d19b5 villas-fpga-pipe: whitespaces and syntax fixes
2ed26572eb202d3fb1f9272ad8263f6c3db524fc adjust DMA IP core to new DMA parameters of Niklas' bitstream
3612b9a203d5b679b2e6f5bded9d8a5d435da4c2 update VILLAScommon submodule
17d03d6d7cc4144ffecc3ce3f7a9efd6fd0cfb05 add missing parentheses
d887eb56836a0f224606a59b86d8cce6aeb45a09 update year in copyright notices
bd2844d5400d3a7077c9d1f3ab6af265c8720060 fixes for villas-fpga-pipe
fbb0a7c8b6f0352b35a1fdb6722caa2fd8355bac cleanup of comments
0b197052daff92a8b388eaa10b084ac98c40ff6e add new IP core for standard Xilinx Aurora cores
501f12762503308026c7724fccba2ccbd197bcd7 card: allow loading IPs devicetree from extra file
033f8ef9fced5b6483dcd300d2be42b232d176a1 update gitignore
7bdd26371fb2e00158c965f3cb00e069dd8a83ec add VSCode configuration for GDB debugging as root
ec8dc2c5e44dda0146b8b7fe7664caa7c347f618 harmonize logger names
02635501d44dfbf31b959141995dea65f3d0adb3 update code to latest common submodule
f2ef1dfaf2e96c623512e73b78b5db40bdbd5ca6 remove old configs
7ea5d43b162247c81b2ee6a106dd36807b6a626f update hardware submodule
16d856753ffb49a3cac4690faf31bc6b55dc1b1c update gitignore
1202b4edb1d47c77d06488ffd741e88dac4fab1f fix CI
aabe56f5dcacfc40dba169f5502eb6738031f525 fix format strings
0a7e12b357fc6b662c35922027a961a9887f8a8b update config include
b5a9c11a9118d096b25a76d1d7b547d5abb7d861 adapt to new plugin registry
3ccb25a2118b6ad211255215e08ed30168049b56 remove obsolete htdocs setting
bda5171c23404deedf2fbfc16b0ccefcc1311698 remove hardware submodule
66aaf9e062efdedb857968acf50625907ee522c8 Merge branch 'fix-cmake' into 'master'
8172f3868657cdb1930f9eb9419a68320761a722 cmake: allow linking libxil from non-standard location
34874fb2ff78ae5a9c02eb4015d4730017a2868d Merge branch 'cppcheck' into 'master'
e61bb67c91bdd7142dc8ae492bf85ab4b8f6adad ci: add cppcheck
7e0ca3ecdfb7acb10db79c28ebc8409ba979a9ef remove unused submodules
6bb3567acddb015f51a44c094f8dd46c321549d3 Merge branch 'fix-codestyle' into 'master'
c89145731b176b5fcb081bc6d9ffe933ae3a7c9c fix code-style
e73d84f1d4a3778aef71e025f494f96229620761 emc: add initial code to flash FPGA bitstream via PCIe
e54aabff4da52c26df8606b88457b60b15008be2 update submodules
7e1c6bd9898ab1e4a57c472c44d1f5b506bb67d9 emc: add stub IP
db59fdb5022f4d1192aef5fb0f677ff8d9cf9850 fix naming of factories
472f66993e0e8a05364958372211ea79fbb245aa update hardware submodule and move hwdef-parse script into hardware repo
0796f835af6be0235835df581541b5d386ea7453 update libxil submodule
53ea7b2289b427977c901b88113f5e073be6e3e8 cmake: make unit-tests optional
21340e7bc56417b9967f5a066f93ac2f99777ab1 Merge branch 'refactoring' into 'master'
86959cedb3b3bd604e98b1cafdc3fc809d8cd1a1 ci: update CI config
71c0f8984ce8292462ae5450bb89def54ce0f89c docker: add missing deps
43f94f4509362539e52802c5e64384ac6f79c490 docker: add mising ssl headers
2bc1b5c771d372fcee5af067396d7adcd4c4be6f docker: fix location of FEIN e.V. repo
5b5da9f2cdd44f1ca233a65f649b3ee8644dc7a3 node: add connect() with reverse path
2fa22b797166046993d9344b658d9c8836bdef1e update VILLAScommon submodule
692d9721fbb6e9c05c2b68215338ec43eab46839 refactor: more code-style improvements
01dcab9e493a121d3cea5da61ace5c9070cc33c1 refactor: no namespace scopes in source files
393c5f3564387dba1af107516320bb69e68d4252 cmake: fixups for inclusion into VILLASnode
ff07bc3946157422c06628ccf8c5c58be067add3 refactor: no namespace scoeps in source files
1eb8f5233981732b7c649fad30a87adc5530da16 refactor: whitespaces for references
1f6a181af64d806df12611ab0c5d0db33aa53cc8 update VILLAScommon submodule
972377d03dfa8c1f820b0eb5f2fbbb37cdd75255 refactor IpNode and IpCore class names
8a13d8ad9b5ec4456f49ab4dca2020858bfea1a7 several cleanups and bugfixes
2affde11e1061d6a7ca978099da9603a7a4a56fc use new getter for graph
2a62ea92721fb55d2bcbdcdc7ca04b2c3d383d1a pipe: use correct DMA instance
4ab00cdc4ef8284ae1fb5a32cc811401d7280ce3 harmonize codestyle
c5cdee6a4517267a4c93c64243ac43a5a9feec0a use new vlnv id for aurora_axis
111199c5f628914c1044fa5c590d7a7e5ef6b9da use new plugin mechanism
5f3dd901a566ad087180b59541098bd740ffb9a3 unit-tests: allow FPGA configuration to provided via env var
183c47d0db4d84f48a33ee0bc571a6b4efc12210 plugin: fix lookup
a6202d3d56871315c9d52001cf09dd2eb1c662f6 gpio: add new IP for AXI programmable GPIO
e524ec9be43110237e7e4fcef44bc87363b42698 intc: fix name of register space
127419d8fa5a4cdd85ee4924a55d0fe6c2eaf0e6 harmonize code-style with VILLAScommon/node
143b950aaf7948712f927d21d405e0be0dd9c8e9 update to latest VILLAScommon submodule
506f319014128e5c9a2b0336274edcb42266a558 aurora_axis: add two functions to reset counters and configure loopback mode
f608e83991b5ca1c558c6b9bf0b10da50e3b3fc4 aurora_axis: dump frame counters
9fd833cb27a54d60ec2b1a6416cee75e19222c25 aurora_axis: harmonize with HDL changes
1571a4ef3288b7fa7e615dbbb5ac31d8efcbe8b4 update submodule urls
981c0eadee39209b287f050f7502ace5e62c1479 add a writeMemory function to IpCore class
77eee178e652218919735aae5455158ef303fa80 update bitstream configs
0b589626a0de626240cdb9d7f867159c35209a77 update common submodule
a2a66c9539f28181b8714fbc64c1bd246c2ddaf5 several fixes for villas-fpga-pipe
6b893d2fbc35c3f2c259fa85b09eefa0148b988b dma: add dump() method
8f8bd1af121bfcc7e7529d59beb2a4a1c8de8c4e add note to cite our publication
09b0a852725cae3bd4fdb1917f5feaf8ddfae05e move gpu module to top level directory
545d47f030edc20ac75329b4340f0f5ca2fb7ca8 ci: some tweaks to fix unit-tests
fc7c1e08957064320e163104635a91cd8c71efd0 do not call copy-ctor of villas::HostRamAllocator
74b3d58781ebb4eef3348a3e0682a1392d9f18d9 fix include paths
5fc8d527c0b55f4ab214341a21db76a23e5ec052 tests: remove obsolete unit tests which have been moved to VILLAScommon
a87df1b576586fa244b1aa4418db21a5fe70ea93 Merge branch 'feature/hls-rtds2gpu' into develop
86fab24844d86c42a21d78a7699986c1aed3bb1f pipe: rename streamer to pipe (closes #19)
fdf1b64f7120c9b91c4378e86f6f8789aa0dca59 fix gdrcopy submodule
e51c98223f26deef5dd7f54babaa2215675255e5 gpu: fix include paths and some linker settings
437380ff773c62334a9876eec37519211720106b move more code to VILLAScommon repo
4a05d63e02d5775d225d353855c364207f1838b3 ci: use Centos 7 based Docker Image with CUDA dev env from Nvidia
b165227fe11524efcfe587243f9f0c8a1b0979db ci: use relative path in gitmodules for proper access rights
db9dd3b6633ee6b5822c7112277fd4b6cf3d661c update common submodule
fa0b0dcc272c011e7da51d8ef1168e6d5131288a streamer: use new memory api
a4c1ad57c5fe644cf3fff34ac799ac16c37dfade fix include paths
3657778896bce9922927e515e6983de6334dbdf1 move common code to VILLAScommon submodule
5c02b41fab1eb088382b2c869001bbc31f580688 remove some obsolete C code files
dca0951f4503f8af5a80c1ba8fa9023d0f6caa63 add more copyright / license headers
30325d42a6662fe86bcedb6c95805f05a7ac677a add Daniel to README
a0eb211d6ada6b9dde40cb9d8e0494ededac03d9 added submodule to VILLASfpga-hardware repo
5a6aa1855e03bcd6394f55b5ee9ae57a6c2d3dcd update Fedora version in Dockerfile
d44c06227760cbf91f2d1d2fd8fc4db36f946bdb add pcimem.c
bed6dd5e4435f095f2a66835449a6921d9f491a8 update copyright years
1a05612237d2677ff9a13c8f3bf0cdff1079c28c do not store bitstreams here
4cbba96972d5764c0a33cfd8ac9299322e7d3cc3 Merge branch 'feature/gpu' into 'develop'
9439b26ce42c2d60355fa4c1e5200c9b40852f22 Merge branch 'feature/villas-common' into 'develop'
bbeb017a14387918528c25b445c446759fd94410 Merge branch 'feature/blockram' into 'develop'
a481afc7f0300e3d98db41f9619d5c5293dcacf3 Merge branch 'feature/packaging' into 'develop'
ad47e712dcacf553b46666a32a16ed97814a93a0 Merge branch 'develop' into 'feature/packaging'
48d2f6d7d8f0ca3f450a138259d94a256a0c1848 Merge branch 'feature/dma-and-memory' into 'develop'
3504340b15d93880b2dbec5e1d078b900af59c72 cpack: fix name of source tarbar
f545e6ab3316948a5a680e3e008e2c49e9b79893 added pkg-config file and CMake configuration for building RPM packages
82d92d926026f5fa4228952afb9d2c48c2363043 Merge branch 'feature/memory-manager-rebased' into 'develop'
487da0794b54664ef40642479ecd94238f0b7eb4 Merge branch 'fix/directed_graph_loop_detection_bug' into 'develop'
18552b03eb37c13a6ad74ef44b37094f8e0de37d Merge branch 'feature/cpp_warnings' into 'develop'
1ee36fac3f78f0b2280dd917dd66f9853f8e0f5b Merge branch 'feature/criterion-spdlog' into develop
ee440f1de2d1294e35034e218ccdb8a224cf0161 Merge branch 'develop' of git.rwth-aachen.de:acs/public/villas/VILLASfpga-code into develop
fa1348a2e7039f11efed493b03550e246d3d5411 logging: use similar log style in all modules
e2ab3d43e0d8d05bc20f9ddd9716c9a588749aef tests: override some criteriod_log() functions in order to use spdlog style log output
c08050d1c51d141077fe916264cef8fdfface0ad tests: some cleanups
51124b8fd8d64ea7cc8b196d115376a4fb6c1566 tests: readd missing graph test suite
35fa5afa08c06ed8bc39adcc7ef21071b1bc2f05 tests: automatically detect whether or not we can run tests in parallel
2de9aa97b23d59fd8372f16a5c515df58f0920c7 tests: moved initialization of FPGA stuff to fpga.cpp
8f76da0f41e0250e0e6126a417c9555630da0a92 Merge branch 'feature/hw-testing' into feature/cpp (closes #14 and #15)
5004a8fb971ab3cffff4d781a05cc555a8d06d2d do parallel build
3f0049567601ab1b1762d5aaf250db4147843850 cleanup build dir before building
0f8c498b7d15a6d41eeff9b97032fbf479710472 tiny change
e3b10c1e79855e21ea6d251c5b0501d606500f03 FPGA tests fail if we attempt to run them in parallel
507f6d77d16f8d35afa9bda9516aeb49039ad436 Merge branch 'feature/non-root' into feature/hw-testing
3ae1290ddc2e6194f68948dee235cb6243e25c79 add script to configure system for non-root access to FPGA
8dad0435be9905c80acaccb5a045d9d20ac737f9 vfio: only rebind pci device to VFIO driver if not already bound
49c7dfb81b6e9e5e6fc5e9bc87cfadff7fe6706d pci: add function to get currently loaded kernel driver
3495777a7aae14bb2afcf7555bc5fa4352b081e0 install libraries to fix loading of libvillas-fpga.so
20d0efcf2216b05143ec31061f248b879dd4789a execute FPGA unit on acs-villas
fcf45a95ca7f9f045725188c1f5da073665aed63 fix wrong tag in gitlab-ci.yml
499d92db66a95f12c0ebe6b400f545c64259b0cd use official Fedora image as base
410210c421c834456a525c28f7ef9b9ffd00aabd enable unit tests on CI
d63d9e83378de00fd84e307b8149b3ca29238970 docker: fix invalid tag name
b42f181094625fe4e6921fe35438efc7f948fd2f fix path of submodule
5733c8f02597495b96a99676631f0d09ff61714c fix CI
3874cadcec0f035055d7ebc089246937a07c507f add LAPACK dependency to Dockerfile
d3822919261974215e31804d83bd3b32546ea6e1 fix CI
b1c61eb26ba42a9e8d4fa04aad0b6f687f761109 use https submodules
cff953d82c6f8872d48e012ad9c1fea53bc99cd0 add missing benchmarks
e986dc94bf82883c5b96e75feda20d807384c77f added gitignore
9d31c0058348eed286bcf56c15c3c4da389613e1 added fodler for bitstreams
8f78034705b0797c5591e33add60330eb8715d91 imported source code from VILLASfpga repo and made it compile
c8db2e0b54b4436fb663ea2f35de4352495db51b added simple Dockerfile for development
15bb988510a3d4d896dd583179922760a78081a5 created new repo for VILLASfpga

10
fpga/scripts/gdb_sudo.sh Executable file
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#!/bin/bash
#
# Run GDB as sudo for VS Code debugger
# See: .vscode directory
#
# Author: Steffen Vogel <post@steffenvogel.de>
# SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0
sudo pkexec /usr/bin/gdb "$@"

324
fpga/scripts/hwdef-parse.py Executable file
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#!/usr/bin/env python3
"""
HWH File Parser
Author: Steffen Vogel <post@steffenvogel.de>
Author: Daniel Krebs <github@daniel-krebs.net>
Author: Hatim Kanchwala <hatim@hatimak.me>
Author: Pascal Bauer <pascal.bauer@rwth-aachen.de>
SPDX-FileCopyrightText: 2017-2022 Steffen Vogel <post@steffenvogel.de>
SPDX-FileCopyrightText: 2017-2022 Daniel Krebs <github@daniel-krebs.net>
SPDX-FileCopyrightText: 2017-2022 Hatim Kanchwala <hatim@hatimak.me>
SPDX-FileCopyrightText: 2023 Pascal Bauer <pascal.bauer@rwth-aachen.de>
SPDX-License-Identifier: GPL-3.0-or-later
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
"""
from multiprocessing.sharedctypes import Value
from lxml import etree
import zipfile
import sys
import re
import json
whitelist = [
[ 'xilinx.com', 'ip', 'zynq_ultra_ps_e' ],
[ 'xilinx.com', 'ip', 'axi_timer' ],
[ 'xilinx.com', 'ip', 'axis_switch' ],
[ 'xilinx.com', 'ip', 'axi_fifo_mm_s' ],
[ 'xilinx.com', 'ip', 'axi_dma' ],
[ 'xilinx.com', 'ip', 'aurora_8b10b' ],
[ 'xilinx.com', 'ip', 'axi_gpio' ],
[ 'xilinx.com', 'ip', 'axi_bram_ctrl' ],
[ 'xilinx.com', 'ip', 'axi_pcie' ],
[ 'xilinx.com', 'ip', 'axi_iic' ],
[ 'xilinx.com', 'module_ref', 'dinoif_fast' ],
[ 'xilinx.com', 'module_ref', 'dinoif_dac' ],
[ 'xilinx.com', 'module_ref', 'axi_pcie_intc' ],
[ 'xilinx.com', 'module_ref', 'registerif' ],
[ 'xilinx.com', 'hls', 'rtds2gpu' ],
[ 'xilinx.com', 'hls', 'mem' ],
[ 'acs.eonerc.rwth-aachen.de', 'user', 'axi_pcie_intc' ],
[ 'acs.eonerc.rwth-aachen.de', 'user', 'rtds_axis' ],
[ 'acs.eonerc.rwth-aachen.de', 'user', 'aurora_axis' ],
[ 'acs.eonerc.rwth-aachen.de', 'hls' ],
[ 'acs.eonerc.rwth-aachen.de', 'sysgen' ]
]
# List of VLNI ids of AXI4-Stream infrastructure IP cores which do not alter data
# see PG085 (AXI4-Stream Infrastructure IP Suite v2.2)
axi_converter_whitelist = [
[ 'xilinx.com', 'ip', 'axis_subset_converter' ],
[ 'xilinx.com', 'ip', 'axis_clock_converter' ],
[ 'xilinx.com', 'ip', 'axis_register_slice' ],
[ 'xilinx.com', 'ip', 'axis_dwidth_converter' ],
[ 'xilinx.com', 'ip', 'axis_register_slice' ],
[ 'xilinx.com', 'ip', 'axis_data_fifo' ],
[ 'xilinx.com', 'ip', 'floating_point' ]
]
opponent = {
'MASTER' : ('SLAVE', 'TARGET'),
'SLAVE' : ('MASTER', 'INITIATOR'),
'INITIATOR' : ('TARGET', 'SLAVE'),
'TARGET' : ('INITIATOR', 'MASTER')
}
def bus_trace(root, busname, type, whitelist):
module = root.xpath('.//MODULE[.//BUSINTERFACE[@BUSNAME="{}" and (@TYPE="{}" or @TYPE="{}")]]'.format(busname, type[0], type[1]))
vlnv = module[0].get('VLNV')
instance = module[0].get('INSTANCE')
if vlnv_match(vlnv, whitelist):
return instance, busname
elif vlnv_match(vlnv, axi_converter_whitelist):
next_bus = module[0].xpath('.//BUSINTERFACE[@TYPE="{}" or @TYPE="{}"]'.format(opponent[type[0]][0], opponent[type[0]][1]))
next_busname = next_bus[0].get('BUSNAME')
return bus_trace(root, next_busname, type, whitelist)
else:
raise TypeError('Unsupported AXI4-Stream IP core: %s (%s)' % (instance, vlnv))
def vlnv_match(vlnv, whitelist):
c = vlnv.split(':')
for w in whitelist:
if c[:len(w)] == w:
return True
return False
def remove_prefix(text, prefix):
return text[text.startswith(prefix) and len(prefix):]
def sanitize_name(name):
name = remove_prefix(name, 'S_')
name = remove_prefix(name, 'M_')
name = remove_prefix(name, 'AXI_')
name = remove_prefix(name, 'AXIS_')
return name
if len(sys.argv) < 2:
print('Usage: {} path/to/*.hwdef'.format(sys.argv[0]))
print(' {} path/to/*.hwh'.format(sys.argv[0]))
sys.exit(1)
try:
# read .hwdef which is actually a zip-file
zip = zipfile.ZipFile(sys.argv[1], 'r')
hwh = zip.read('top.hwh')
except:
f = open(sys.argv[1], 'r')
hwh = f.read()
# parse .hwh file which is actually XML
try:
root = etree.XML(hwh)
except:
print('Bad format of "{}"! Did you choose the right file?'.format(sys.argv[1]))
sys.exit(1)
ips = {}
# find all whitelisted modules
modules = root.find('.//MODULES')
for module in modules:
instance = module.get('INSTANCE')
vlnv = module.get('VLNV')
# Ignroing unkown
if not vlnv_match(vlnv, whitelist):
continue
ips[instance] = {
'vlnv' : vlnv
}
# populate parameters
params = module.find('.//PARAMETERS')
if params is not None and instance != "zynq_ultra_ps_e_0": #! Parameters of "zynq" ignored
p = ips[instance].setdefault('parameters', {})
for param in params:
name = param.get('NAME').lower()
value = param.get('VALUE')
try:
value = int(value, 0)
except ValueError:
pass
p[name] = value
# populate memory view
mmap = module.find('.//MEMORYMAP')
if mmap is None:
continue
mem = ips[instance].setdefault('memory-view', {})
for mrange in mmap:
mem_interface = mrange.get('MASTERBUSINTERFACE')
mem_instance = mrange.get('INSTANCE')
mem_block = mrange.get('ADDRESSBLOCK')
_interface = mem.setdefault(mem_interface, {})
_instance = _interface.setdefault(mem_instance, {})
_block = _instance.setdefault(mem_block, {})
_block['baseaddr'] = int(mrange.get('BASEVALUE'), 16)
_block['highaddr'] = int(mrange.get('HIGHVALUE'), 16)
_block['size'] = _block['highaddr'] - _block['baseaddr'] + 1
# find AXI-Stream switch port mapping
switch = root.find('.//MODULE[@MODTYPE="axis_switch"]')
busifs = switch.find('.//BUSINTERFACES')
switch_ports = 0
for busif in busifs:
if busif.get('VLNV') != 'xilinx.com:interface:axis:1.0':
continue
switch_ports += 1
busname = busif.get('BUSNAME')
name = busif.get('NAME')
type = busif.get('TYPE')
r = re.compile('(M|S)([0-9]+)_AXIS')
m = r.search(name)
port = int(m.group(2))
switch_ip_ports = ips[switch.get('INSTANCE')].setdefault('ports', [])
ep, busname_ep = bus_trace(root, busname, opponent[type], whitelist)
if ep in ips:
ports = ips[ep].setdefault('ports', [])
ports.append({
'role': opponent[type][0].lower(),
'target': '{}:{}'.format(switch.get('INSTANCE'), name)
})
module_ep = root.find('.//MODULE[@INSTANCE="{}"]'.format(ep))
busif_ep = module_ep.find('.//BUSINTERFACE[@BUSNAME="{}"]'.format(busname_ep))
if busif_ep is None:
print("cannot find businterface: {}".format(busname_ep))
sys.exit(1)
busif_name = ports[-1]['name'] = sanitize_name(busif_ep.get('NAME'))
ports[-1]['name'] = busif_name
switch_ip_ports.append({
'role': type.lower(),
'target': '{}:{}'.format(ep, busif_name),
'name': name
})
# set number of master/slave port pairs for switch
ips[switch.get('INSTANCE')]['num_ports'] = int(switch_ports / 2)
# find interrupt assignments
intc = root.find('.//MODULE[@MODTYPE="axi_pcie_intc"]')
if intc is not None:
intr = intc.xpath('.//PORT[@NAME="intr" and @DIR="I"]')[0]
concat = root.xpath('.//MODULE[@MODTYPE="xlconcat" and .//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(intr.get('SIGNAME')))[0]
ports = concat.xpath('.//PORT[@DIR="I"]')
for port in ports:
name = port.get('NAME')
signame = port.get('SIGNAME')
# Skip unconnected IRQs
if not signame:
continue
r = re.compile('In([0-9+])')
m = r.search(name)
irq = int(m.group(1))
ip = root.xpath('.//MODULE[.//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(signame))[0]
instance = ip.get('INSTANCE')
vlnv = ip.get('VLNV')
modtype = ip.get('MODTYPE')
originators = []
# follow one level of OR gates merging interrupts (may be generalized later)
if modtype == 'util_vector_logic':
logic_op = ip.xpath('.//PARAMETER[@NAME="C_OPERATION"]')[0]
if logic_op.get('VALUE') == 'or':
# hardware interrupts sharing the same IRQ at the controller
ports = ip.xpath('.//PORT[@DIR="I"]')
for port in ports:
signame = port.get('SIGNAME')
ip = root.xpath('.//MODULE[.//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(signame))[0]
instance = ip.get('INSTANCE')
originators.append((instance, signame))
else:
# consider this instance as originator
originators.append((instance, signame))
for instance, signame in originators:
ip = root.xpath('.//MODULE[.//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(signame))[0]
port = ip.xpath('.//PORT[@SIGNAME="{}" and @DIR="O"]'.format(signame))[0]
irqname = port.get('NAME')
if instance in ips:
irqs = ips[instance].setdefault('irqs', {})
irqs[irqname] = '{}:{}'.format(intc.get('INSTANCE'), irq)
# Find BRAM storage depths (size)
brams = root.xpath('.//MODULE[@MODTYPE="axi_bram_ctrl"]')
for bram in brams:
instance = bram.get('INSTANCE')
width = bram.find('.//PARAMETER[@NAME="DATA_WIDTH"]').get('VALUE')
depth = bram.find('.//PARAMETER[@NAME="MEM_DEPTH"]').get('VALUE')
size = int(width) * int(depth) / 8
if instance in ips:
ips[instance]['size'] = int(size)
pcies = root.xpath('.//MODULE[@MODTYPE="axi_pcie"]')
for pcie in pcies:
instance = pcie.get('INSTANCE')
axi_bars = ips[instance].setdefault('axi_bars', {})
pcie_bars = ips[instance].setdefault('pcie_bars', {})
for from_bar, to_bar, from_bars in (('AXIBAR', 'PCIEBAR', axi_bars), ('PCIEBAR', 'AXIBAR', pcie_bars)):
from_bar_num = int(pcie.find('.//PARAMETER[@NAME="C_{}_NUM"]'.format(from_bar)).get('VALUE'))
for i in range(0, from_bar_num):
from_bar_to_bar_offset = int(pcie.find('.//PARAMETER[@NAME="C_{}2{}_{}"]'.format(from_bar, to_bar, i)).get('VALUE'), 16)
from_bars['BAR{}'.format(i)] = { 'translation': from_bar_to_bar_offset }
if from_bar == 'AXIBAR':
axi_bar_lo = int(pcie.find('.//PARAMETER[@NAME="C_{}_{}"]'.format(from_bar, i)).get('VALUE'), 16)
axi_bar_hi = int(pcie.find('.//PARAMETER[@NAME="C_{}_HIGHADDR_{}"]'.format(from_bar, i)).get('VALUE'), 16)
axi_bar_size = axi_bar_hi - axi_bar_lo + 1
axi_bar = from_bars['BAR{}'.format(i)]
axi_bar['baseaddr'] = axi_bar_lo
axi_bar['highaddr'] = axi_bar_hi
axi_bar['size'] = axi_bar_size
print(json.dumps(ips, indent=2))

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fpga/scripts/non_root.sh Executable file
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#!/bin/bash
#
# Setup VFIO for non-root users
#
# Author: Steffen Vogel <post@steffenvogel.de>
# SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0
# PCI-e parameters of FPGA card
PCI_BDF="0000:03:00.0"
PCI_VID="10ee"
PCI_PID="7022"
modprobe vfio
modprobe vfio_pci
modprobe vfio_iommu_type1
IOMMU_GROUP=`basename $(readlink /sys/bus/pci/devices/${PCI_BDF}/iommu_group)`
# bind to vfio driver
echo "${PCI_VID} ${PCI_PID}" > /sys/bus/pci/drivers/vfio-pci/new_id
echo "${PCI_BDF}" > /sys/bus/pci/drivers/vfio-pci/bind
groupadd -f fpga
usermod -G fpga -a svg
usermod -G fpga -a dkr
chgrp fpga /dev/vfio/${IOMMU_GROUP}
chmod g+rw /dev/vfio/${IOMMU_GROUP}

31
fpga/scripts/rebind_device.sh Executable file
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@ -0,0 +1,31 @@
#!/bin/bash
#
# Detach and rebind a PCI device to a PCI kernel driver
#
# Author: Steffen Vogel <post@steffenvogel.de>
# SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0
if [ "$#" -ne 2 ]; then
echo "usage: $0 BUS:DEV:FNC DRIVER"
exit 1
fi
BDF=$1
DRIVER=$2
VENDOR=$(cut -b3- /sys/bus/pci/devices/${BDF}/vendor)
DEVICE=$(cut -b3- /sys/bus/pci/devices/${BDF}/device)
SYSFS_DEVICE=/sys/bus/pci/devices/${BDF}
SYSFS_DRIVER=/sys/bus/pci/drivers/${DRIVER}
echo "Device: $VENDOR $DEVICE $BDF"
if [ -L "${SYSFS_DEVICE}/driver" ] && [ -d "${SYSFS_DEVICE}/driver" ]; then
echo ${BDF} > ${SYSFS_DEVICE}/driver/unbind
fi
echo "${VENDOR} ${DEVICE}" > ${SYSFS_DRIVER}/new_id
echo "${BDF}" > ${SYSFS_DRIVER}/bind
echo "${VENDOR} ${DEVICE}" > ${SYSFS_DRIVER}/remove_id

18
fpga/scripts/reset_pci_device.sh Executable file
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#!/bin/bash
#
# Reset PCI devices like FPGAs after a reflash
#
# Author: Steffen Vogel <post@steffenvogel.de>
# SPDX-FileCopyrightText: 2017 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0
if [ "$#" -ne 1 ]; then
echo "usage: $0 BUS:DEV.FNC"
exit 1
fi
BDF=$1
echo "1" > /sys/bus/pci/devices/${BDF}/remove
echo "1" > /sys/bus/pci/rescan
echo "1" > /sys/bus/pci/devices/${BDF}/reset

9
fpga/scripts/villas-fpga-cat.sh Executable file
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#!/bin/bash
#
# Author: Niklas Eiling <niklas.eiling@rwth-aachen.de>
# SPDX-FileCopyrightText: 2023 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0
CWD=$(dirname -- "$0")
${CWD}/villas-fpga-ctrl -c ${CWD}/../../etc/fpgas.json --connect "2<->stdout"

10
fpga/scripts/villas-fpga-xbar-select.sh Normal file
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#!/bin/bash
#
# Author: Niklas Eiling <niklas.eiling@rwth-aachen.de>
# SPDX-FileCopyrightText: 2023 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0
CWD=$(dirname -- "$0")
# currently connects RTDS and OPAL-RT
${CWD}/villas-fpga-ctrl -c ${CWD}/../../etc/fpgas.json --connect "0<->1" --no-dma

20
fpga/src/CMakeLists.txt Normal file
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## CMakeLists.txt
#
# Author: Daniel Krebs <github@daniel-krebs.net>
# SPDX-FileCopyrightText: 2018 Institute for Automation of Complex Power Systems, RWTH Aachen University
# SPDX-License-Identifier: Apache-2.0
add_executable(villas-fpga-ctrl villas-fpga-ctrl.cpp)
target_link_libraries(villas-fpga-ctrl PUBLIC
villas-fpga
)
add_executable(villas-fpga-pipe villas-fpga-pipe.cpp)
target_link_libraries(villas-fpga-pipe PUBLIC
villas-fpga
)
add_executable(pcimem pcimem.c)

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