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This edits the headers in every file so the copyright notice mentions RWTH Aachen University. We also update some copyright years and fix various comments so the header is the same across all of VILLASframework. * Harmonize comment and code-style Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com> * Harmonize comment and code-style Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com> --------- Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
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VILLASfpga
VILLASfpga provides a flexbible, real-time capable interconnect between FPGAs and Linux, e.g., to connect simulators and devices for hardware-in-the loop simulations. VILLASfpga can guarantee fixed latencies in the nanosecond range. VILLASfpga supports Xilinx FPGAs connected to a Linux system via PCI-Express or via a platform bus as found on MPSoC devices.
Documentation
User documentation is available here: https://villas.fein-aachen.org/doc/fpga.html
License
This project is released under the terms of the Apache 2.0 license:
- SPDX-FileCopyrightText: 2022-2023 Niklas Eiling niklas.eiling@eonerc.rwth-aachen.de
- SPDX-FileCopyrightText: 2018-2023 Steffen Vogel post@steffenvogel.de
- SPDX-FileCopyrightText: 2018 Daniel Krebs dkrebs@eonerc.rwth-aachen.de
- SPDX-License-Identifier: Apache-2.0
We kindly ask all academic publications employing components of VILLASframework to cite one of the following papers:
- A. Monti et al., "A Global Real-Time Superlab: Enabling High Penetration of Power Electronics in the Electric Grid," in IEEE Power Electronics Magazine, vol. 5, no. 3, pp. 35-44, Sept. 2018.
- S. Vogel, M. Mirz, L. Razik and A. Monti, "An open solution for next-generation real-time power system simulation," 2017 IEEE Conference on Energy Internet and Energy System Integration (EI2), Beijing, 2017, pp. 1-6.
Related Projects
Contact
- Niklas Eiling niklas.eiling@eonerc.rwth-aachen.de
- Steffen Vogel post@steffenvogel.de
- Daniel Krebs dkrebs@eonerc.rwth-aachen.de
Institute for Automation of Complex Power Systems (ACS) RWTH University Aachen, Germany