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fpga: fix includes and various comments

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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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Niklas Eiling 2024-04-18 14:32:52 +02:00 • committed by pipeacosta
parent 0ae08e8434
commit 28c24ea22a
3 changed files with 12 additions and 11 deletions
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2
fpga/include/villas/fpga/ips/dma.hpp
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@ -10,10 +10,12 @@
#pragma once
#include <fmt/ostream.h>
#include <villas/config.hpp>
#include <villas/exceptions.hpp>
#include <villas/fpga/node.hpp>
#include <villas/memory.hpp>
#include <xilinx/xaxidma.h>
namespace villas {

19
fpga/lib/ips/dma.cpp
View file

@ -1,24 +1,23 @@
/* DMA driver
*
* Author: Daniel Krebs <github@daniel-krebs.net>
* Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
* SPDX-FileCopyrightText: 2018 Institute for Automation of Complex Power Systems, RWTH Aachen University
* Author: Daniel Krebs <github@daniel-krebs.net>
* SPDX-FileCopyrightText: 2018-2024 Institute for Automation of Complex Power Systems, RWTH Aachen University
* SPDX-License-Identifier: Apache-2.0
*/
#include <sstream>
#include <string>
#include "xilinx/xaxidma_bd.h"
#include "xilinx/xaxidma_hw.h"
#include <sys/types.h>
#include <xilinx/xaxidma.h>
#include <villas/memory.hpp>
#include <villas/fpga/card.hpp>
#include <villas/fpga/ips/dma.hpp>
#include <villas/fpga/ips/intc.hpp>
#include <villas/memory.hpp>
#include <xilinx/xaxidma.h>
#include <xilinx/xaxidma_bd.h>
#include <xilinx/xaxidma_hw.h>
// Max. size of a DMA transfer in simple mode
#define FPGA_DMA_BOUNDARY 0x1000
@ -116,7 +115,7 @@ void Dma::setupScatterGatherRingRx(uintptr_t physAddr, uintptr_t virtAddr) {
throw RuntimeError("Failed to clone BD template: {}", ret);
if (cyclic) {
/* Enable Cyclic DMA mode */
// Enable Cyclic DMA mode
XAxiDma_BdRingEnableCyclicDMA(rxRingPtr);
XAxiDma_SelectCyclicMode(&xDma, XAXIDMA_DEVICE_TO_DMA, 1);
}
@ -212,7 +211,7 @@ Dma::~Dma() {
free(rxRingPtr->CyclicBd);
rxRingPtr->CyclicBd = nullptr;
}
// unampe SG memory Blocks
// Unmap SG memory Blocks
if (sgRing) {
card->unmapMemoryBlock(*sgRing);
}

2
include/villas/nodes/fpga.hpp
View file

@ -32,7 +32,7 @@ protected:
std::string cardName;
std::list<std::string> connectStrings;
// This setting improves latency by remove various checks.
// This setting improves latency by removing various checks.
// Use with caution! Requires read cache in FPGA design!
// The common use case in VILLASfpga is that we have exactly
// one write for every read and the number of exchanged signals