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fpga: fix includes and various comments
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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3 changed files with 12 additions and 11 deletions
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@ -10,10 +10,12 @@
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#pragma once
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#include <fmt/ostream.h>
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#include <villas/config.hpp>
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#include <villas/exceptions.hpp>
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#include <villas/fpga/node.hpp>
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#include <villas/memory.hpp>
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#include <xilinx/xaxidma.h>
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namespace villas {
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@ -1,24 +1,23 @@
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/* DMA driver
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*
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* Author: Daniel Krebs <github@daniel-krebs.net>
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* Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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* SPDX-FileCopyrightText: 2018 Institute for Automation of Complex Power Systems, RWTH Aachen University
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* Author: Daniel Krebs <github@daniel-krebs.net>
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* SPDX-FileCopyrightText: 2018-2024 Institute for Automation of Complex Power Systems, RWTH Aachen University
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <sstream>
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#include <string>
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#include "xilinx/xaxidma_bd.h"
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#include "xilinx/xaxidma_hw.h"
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#include <sys/types.h>
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#include <xilinx/xaxidma.h>
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#include <villas/memory.hpp>
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#include <villas/fpga/card.hpp>
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#include <villas/fpga/ips/dma.hpp>
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#include <villas/fpga/ips/intc.hpp>
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#include <villas/memory.hpp>
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#include <xilinx/xaxidma.h>
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#include <xilinx/xaxidma_bd.h>
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#include <xilinx/xaxidma_hw.h>
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// Max. size of a DMA transfer in simple mode
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#define FPGA_DMA_BOUNDARY 0x1000
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@ -116,7 +115,7 @@ void Dma::setupScatterGatherRingRx(uintptr_t physAddr, uintptr_t virtAddr) {
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throw RuntimeError("Failed to clone BD template: {}", ret);
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if (cyclic) {
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/* Enable Cyclic DMA mode */
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// Enable Cyclic DMA mode
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XAxiDma_BdRingEnableCyclicDMA(rxRingPtr);
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XAxiDma_SelectCyclicMode(&xDma, XAXIDMA_DEVICE_TO_DMA, 1);
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}
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@ -212,7 +211,7 @@ Dma::~Dma() {
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free(rxRingPtr->CyclicBd);
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rxRingPtr->CyclicBd = nullptr;
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}
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// unampe SG memory Blocks
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// Unmap SG memory Blocks
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if (sgRing) {
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card->unmapMemoryBlock(*sgRing);
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}
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@ -32,7 +32,7 @@ protected:
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std::string cardName;
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std::list<std::string> connectStrings;
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// This setting improves latency by remove various checks.
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// This setting improves latency by removing various checks.
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// Use with caution! Requires read cache in FPGA design!
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// The common use case in VILLASfpga is that we have exactly
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// one write for every read and the number of exchanged signals
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