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hwdef-parse.py: add interrupt controller added as module_ref to

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whitelist

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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Niklas Eiling 2023-12-19 11:06:19 +01:00 • committed by Niklas Eiling
parent 7e07da6e60
commit 3e64e5d238
1 changed files with 4 additions and 3 deletions
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7
fpga/scripts/hwdef-parse.py
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@ -46,6 +46,7 @@ whitelist = [
[ 'xilinx.com', 'ip', 'axi_iic' ],
[ 'xilinx.com', 'module_ref', 'dinoif_fast' ],
[ 'xilinx.com', 'module_ref', 'dinoif_dac' ],
[ 'xilinx.com', 'module_ref', 'axi_pcie_intc' ],
[ 'xilinx.com', 'hls', 'rtds2gpu' ],
[ 'xilinx.com', 'hls', 'mem' ],
[ 'acs.eonerc.rwth-aachen.de', 'user', 'axi_pcie_intc' ],
@ -149,7 +150,7 @@ for module in modules:
params = module.find('.//PARAMETERS')
if params is not None and instance != "zynq_ultra_ps_e_0": #! Parameters of "zynq" ignored
p = ips[instance].setdefault('parameters', {})
for param in params:
name = param.get('NAME').lower()
value = param.get('VALUE')
@ -288,9 +289,9 @@ for bram in brams:
width = bram.find('.//PARAMETER[@NAME="DATA_WIDTH"]').get('VALUE')
depth = bram.find('.//PARAMETER[@NAME="MEM_DEPTH"]').get('VALUE')
size = int(width) * int(depth) / 8
if instance in ips:
ips[instance]['size'] = int(size)