mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
synced 2025-03-09 00:00:00 +01:00
Merge branch 'master' into node-test_rtt
This commit is contained in:
al3xa23
GitHub
commit
4fb469954a
21 changed files with 3293 additions and 474 deletions
|
|
@ -292,10 +292,10 @@ deploy:docker-dev-vscode:
|
|||
before_script:
|
||||
- docker login -u ${CI_REGISTRY_USER} -p ${CI_REGISTRY_PASSWORD} ${CI_REGISTRY}
|
||||
script:
|
||||
- docker manifest rm ${DOCKER_IMAGE}:latest || true
|
||||
- docker manifest create ${DOCKER_IMAGE}:latest
|
||||
${DOCKER_IMAGE}:${DOCKER_TAG}-x86_64
|
||||
${DOCKER_IMAGE}:${DOCKER_TAG}-arm64
|
||||
${DOCKER_IMAGE}:${DOCKER_TAG}-armhf
|
||||
- docker manifest push ${DOCKER_IMAGE}:latest
|
||||
tags:
|
||||
- docker
|
||||
|
|
|
|||
|
|
@ -1,26 +1,8 @@
|
|||
# Contribution guidelines
|
||||
|
||||
<!--
|
||||
SPDX-FileCopyrightText: 2014-2023 Institute for Automation of Complex Power Systems, RWTH Aachen University
|
||||
SPDX-FileCopyrightText: 2014-2024 Institute for Automation of Complex Power Systems, RWTH Aachen University
|
||||
SPDX-License-Identifier: Apache-2.0
|
||||
-->
|
||||
|
||||
## Coding standards
|
||||
|
||||
We are following the [LLVM C++ Coding Standards](https://llvm.org/docs/CodingStandards.html).
|
||||
|
||||
## Always work on feature branches
|
||||
|
||||
Please branch from `master` to create a new _feature_ branch.
|
||||
|
||||
Please create a new _feature_ branch for every new feature or fix.
|
||||
|
||||
## Do not commit directly to `master`.
|
||||
|
||||
Use your _feature_ branch.
|
||||
|
||||
Please rebase your work against the `develop` before submitting a merge reqeuest.
|
||||
|
||||
## Make the CI happy :-)
|
||||
|
||||
Only branches which pass the CI can be merged.
|
||||
Visit the [contribution guidelines](https://villas.fein-aachen.org/docs/node/development/contributing/) in our documentation to understand how you can contribute to VILLASnode.
|
||||
|
|
|
|||
13
README.md
13
README.md
|
|
@ -36,6 +36,11 @@ User documentation is available here: <https://villas.fein-aachen.org/docs/>
|
|||
- [MIOB](https://github.com/RWTH-ACS/miob)
|
||||
- [DINO](https://github.com/RWTH-ACS/dino)
|
||||
|
||||
## Contributing
|
||||
|
||||
All contributions are welcome!
|
||||
If you want to contribute to VILLASnode, please visit the [contribution guidelines](https://villas.fein-aachen.org/docs/node/development/contributing/) in our documentation.
|
||||
|
||||
## License
|
||||
|
||||
This project is released under the terms of the [Apache 2.0 license](LICENSE).
|
||||
|
|
@ -47,10 +52,10 @@ We kindly ask all academic publications employing components of VILLASframework
|
|||
|
||||
For other licensing options please consult [Prof. Antonello Monti](mailto:amonti@eonerc.rwth-aachen.de).
|
||||
|
||||
- SPDX-FileCopyrightText: 2014-2023 Institute for Automation of Complex Power Systems, RWTH Aachen University
|
||||
- SPDX-FileCopyrightText: 2023 OPAL-RT Germany GmbH
|
||||
- SPDX-FileCopyrightText: 2022-2023 Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
|
||||
- SPDX-FileCopyrightText: 2018-2023 Steffen Vogel <post@steffenvogel.de>
|
||||
- SPDX-FileCopyrightText: 2014-2024 Institute for Automation of Complex Power Systems, RWTH Aachen University
|
||||
- SPDX-FileCopyrightText: 2023-2024 OPAL-RT Germany GmbH
|
||||
- SPDX-FileCopyrightText: 2022-2024 Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
|
||||
- SPDX-FileCopyrightText: 2018-2024 Steffen Vogel <post@steffenvogel.de>
|
||||
- SPDX-FileCopyrightText: 2018 Daniel Krebs <dkrebs@eonerc.rwth-aachen.de>
|
||||
- SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ fpgas = {
|
|||
id = "10ee:7021"
|
||||
slot = "0000:88:00.0"
|
||||
do_reset = true
|
||||
ips = "../../fpga/etc/vc707-xbar-pcie/vc707-xbar-pcie-dino-v2.json"
|
||||
ips = "../../fpga/etc/vc707-xbar-pcie/vc707-xbar-pcie-dino.json"
|
||||
polling = false
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -229,7 +229,7 @@
|
|||
"c_use_chipscope": "false",
|
||||
"c_drp_if": "false",
|
||||
"transceivercontrol": "false",
|
||||
"c_use_crc": "false",
|
||||
"c_use_crc": "true",
|
||||
"supportlevel": 0,
|
||||
"c_use_byteswap": "false",
|
||||
"c_cpll_fbdiv": 2,
|
||||
|
|
@ -367,7 +367,7 @@
|
|||
"c_use_chipscope": "false",
|
||||
"c_drp_if": "false",
|
||||
"transceivercontrol": "false",
|
||||
"c_use_crc": "false",
|
||||
"c_use_crc": "true",
|
||||
"supportlevel": 0,
|
||||
"c_use_byteswap": "false",
|
||||
"c_cpll_fbdiv": 2,
|
||||
|
|
@ -505,7 +505,7 @@
|
|||
"c_use_chipscope": "false",
|
||||
"c_drp_if": "false",
|
||||
"transceivercontrol": "false",
|
||||
"c_use_crc": "false",
|
||||
"c_use_crc": "true",
|
||||
"supportlevel": 0,
|
||||
"c_use_byteswap": "false",
|
||||
"c_cpll_fbdiv": 2,
|
||||
|
|
@ -913,8 +913,8 @@
|
|||
"m15_s15_connectivity": 1,
|
||||
"component_name": "design_1_xbar_0",
|
||||
"edk_iptype": "PERIPHERAL",
|
||||
"c_baseaddr": 0,
|
||||
"c_highaddr": 1023
|
||||
"c_baseaddr": 4096,
|
||||
"c_highaddr": 5119
|
||||
},
|
||||
"ports": [
|
||||
{
|
||||
|
|
@ -969,7 +969,7 @@
|
|||
},
|
||||
{
|
||||
"role": "slave",
|
||||
"target": "dino_dinoif_fast_0:M00_AXIS",
|
||||
"target": "dino_dinoif_adc_0:M00_AXIS",
|
||||
"name": "S05_AXIS"
|
||||
},
|
||||
{
|
||||
|
|
@ -1015,6 +1015,21 @@
|
|||
"dino_dinoif_dac_0": {
|
||||
"vlnv": "xilinx.com:module_ref:dinoif_dac:1.0",
|
||||
"i2c_channel": 1,
|
||||
"parameters": {
|
||||
"component_name": "design_1_dinoif_adc_0_0",
|
||||
"edk_iptype": "PERIPHERAL"
|
||||
},
|
||||
"ports": [
|
||||
{
|
||||
"role": "master",
|
||||
"target": "crossbar_axis_interconnect_0_xbar:S05_AXIS",
|
||||
"name": "M00_AXIS"
|
||||
}
|
||||
]
|
||||
},
|
||||
"dino_dinoif_fast_nologic_0": {
|
||||
"vlnv": "xilinx.com:module_ref:dinoif_fast:1.0",
|
||||
"i2c_channel": 0,
|
||||
"parameters": {
|
||||
"component_name": "design_1_dinoif_dac_0_0",
|
||||
"edk_iptype": "PERIPHERAL"
|
||||
|
|
@ -1027,20 +1042,17 @@
|
|||
}
|
||||
]
|
||||
},
|
||||
"dino_dinoif_fast_0": {
|
||||
"vlnv": "xilinx.com:module_ref:dinoif_fast:1.0",
|
||||
"i2c_channel": 0,
|
||||
"dino_registerif_0": {
|
||||
"vlnv": "xilinx.com:module_ref:registerif:1.0",
|
||||
"parameters": {
|
||||
"component_name": "design_1_dinoif_fast_0_0",
|
||||
"edk_iptype": "PERIPHERAL"
|
||||
},
|
||||
"ports": [
|
||||
{
|
||||
"role": "master",
|
||||
"target": "crossbar_axis_interconnect_0_xbar:S05_AXIS",
|
||||
"name": "M00_AXIS"
|
||||
}
|
||||
]
|
||||
"c_axi_data_width": 32,
|
||||
"c_axi_addr_width": 32,
|
||||
"reg_addr_width": 10,
|
||||
"component_name": "design_1_registerif_0_0",
|
||||
"edk_iptype": "PERIPHERAL",
|
||||
"c_baseaddr": 20480,
|
||||
"c_highaddr": 21503
|
||||
}
|
||||
},
|
||||
"dma_pcie_axi_dma_0": {
|
||||
"vlnv": "xilinx.com:ip:axi_dma:7.1",
|
||||
|
|
@ -1130,6 +1142,29 @@
|
|||
"s2mm_introut": "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:1"
|
||||
}
|
||||
},
|
||||
"dma_pcie_axi_read_cache_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axi_read_cache:1.0",
|
||||
"parameters": {
|
||||
"c_axi_data_width": 32,
|
||||
"c_axi_addr_width": 32,
|
||||
"word_num": 16,
|
||||
"component_name": "design_1_axi_read_cache_0_0",
|
||||
"edk_iptype": "PERIPHERAL",
|
||||
"c_baseaddr": 24576,
|
||||
"c_highaddr": 25599
|
||||
},
|
||||
"memory-view": {
|
||||
"M_AXI": {
|
||||
"dma_pcie_pcie_axi_pcie_0": {
|
||||
"BAR0": {
|
||||
"baseaddr": 0,
|
||||
"highaddr": 4294967295,
|
||||
"size": 4294967296
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"dma_pcie_pcie_axi_pcie_0": {
|
||||
"vlnv": "xilinx.com:ip:axi_pcie:2.9",
|
||||
"parameters": {
|
||||
|
|
@ -1158,7 +1193,7 @@
|
|||
"c_interrupt_pin": 0,
|
||||
"c_comp_timeout": 0,
|
||||
"c_include_rc": 0,
|
||||
"c_s_axi_supports_narrow_burst": 0,
|
||||
"c_s_axi_supports_narrow_burst": 1,
|
||||
"c_include_baroffset_reg": 1,
|
||||
"c_axibar_num": 1,
|
||||
"c_axibar2pciebar_0": 0,
|
||||
|
|
@ -1281,7 +1316,7 @@
|
|||
"s_axi_data_width": 64,
|
||||
"m_axi_addr_width": 32,
|
||||
"m_axi_data_width": 64,
|
||||
"s_axi_supports_narrow_burst": "false",
|
||||
"s_axi_supports_narrow_burst": "true",
|
||||
"bar_64bit": "false",
|
||||
"xlnx_ref_board": "VC707",
|
||||
"pcie_blk_locn": "X1Y0",
|
||||
|
|
@ -1332,6 +1367,20 @@
|
|||
"highaddr": 17407,
|
||||
"size": 1024
|
||||
}
|
||||
},
|
||||
"dino_registerif_0": {
|
||||
"reg0": {
|
||||
"baseaddr": 20480,
|
||||
"highaddr": 21503,
|
||||
"size": 1024
|
||||
}
|
||||
},
|
||||
"dma_pcie_axi_read_cache_0": {
|
||||
"reg0": {
|
||||
"baseaddr": 24576,
|
||||
"highaddr": 25599,
|
||||
"size": 1024
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
{
|
||||
"aurora_8b10b_ch0": {
|
||||
"aurora_aurora_8b10b_ch0": {
|
||||
"vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
|
||||
"parameters": {
|
||||
"component_name": "design_1_aurora_8b10b_0_0",
|
||||
|
|
@ -127,17 +127,17 @@
|
|||
"ports": [
|
||||
{
|
||||
"role": "master",
|
||||
"target": "axis_interconnect_0_xbar:S00_AXIS",
|
||||
"target": "crossbar_axis_interconnect_0_xbar:S00_AXIS",
|
||||
"name": "USER_DATA_M_AXI_RX"
|
||||
},
|
||||
{
|
||||
"role": "slave",
|
||||
"target": "axis_interconnect_0_xbar:M00_AXIS",
|
||||
"target": "crossbar_axis_interconnect_0_xbar:M00_AXIS",
|
||||
"name": "USER_DATA_S_AXI_TX"
|
||||
}
|
||||
]
|
||||
},
|
||||
"aurora_8b10b_ch1": {
|
||||
"aurora_aurora_8b10b_ch1": {
|
||||
"vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
|
||||
"parameters": {
|
||||
"component_name": "design_1_aurora_8b10b_1_0",
|
||||
|
|
@ -229,7 +229,7 @@
|
|||
"c_use_chipscope": "false",
|
||||
"c_drp_if": "false",
|
||||
"transceivercontrol": "false",
|
||||
"c_use_crc": "false",
|
||||
"c_use_crc": "true",
|
||||
"supportlevel": 0,
|
||||
"c_use_byteswap": "false",
|
||||
"c_cpll_fbdiv": 2,
|
||||
|
|
@ -265,17 +265,17 @@
|
|||
"ports": [
|
||||
{
|
||||
"role": "master",
|
||||
"target": "axis_interconnect_0_xbar:S01_AXIS",
|
||||
"target": "crossbar_axis_interconnect_0_xbar:S01_AXIS",
|
||||
"name": "USER_DATA_M_AXI_RX"
|
||||
},
|
||||
{
|
||||
"role": "slave",
|
||||
"target": "axis_interconnect_0_xbar:M01_AXIS",
|
||||
"target": "crossbar_axis_interconnect_0_xbar:M01_AXIS",
|
||||
"name": "USER_DATA_S_AXI_TX"
|
||||
}
|
||||
]
|
||||
},
|
||||
"aurora_8b10b_ch2": {
|
||||
"aurora_aurora_8b10b_ch2": {
|
||||
"vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
|
||||
"parameters": {
|
||||
"component_name": "design_1_aurora_8b10b_3_0",
|
||||
|
|
@ -367,7 +367,7 @@
|
|||
"c_use_chipscope": "false",
|
||||
"c_drp_if": "false",
|
||||
"transceivercontrol": "false",
|
||||
"c_use_crc": "false",
|
||||
"c_use_crc": "true",
|
||||
"supportlevel": 0,
|
||||
"c_use_byteswap": "false",
|
||||
"c_cpll_fbdiv": 2,
|
||||
|
|
@ -403,17 +403,17 @@
|
|||
"ports": [
|
||||
{
|
||||
"role": "master",
|
||||
"target": "axis_interconnect_0_xbar:S02_AXIS",
|
||||
"target": "crossbar_axis_interconnect_0_xbar:S02_AXIS",
|
||||
"name": "USER_DATA_M_AXI_RX"
|
||||
},
|
||||
{
|
||||
"role": "slave",
|
||||
"target": "axis_interconnect_0_xbar:M02_AXIS",
|
||||
"target": "crossbar_axis_interconnect_0_xbar:M02_AXIS",
|
||||
"name": "USER_DATA_S_AXI_TX"
|
||||
}
|
||||
]
|
||||
},
|
||||
"aurora_8b10b_ch3": {
|
||||
"aurora_aurora_8b10b_ch3": {
|
||||
"vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
|
||||
"parameters": {
|
||||
"component_name": "design_1_aurora_8b10b_2_0",
|
||||
|
|
@ -505,7 +505,7 @@
|
|||
"c_use_chipscope": "false",
|
||||
"c_drp_if": "false",
|
||||
"transceivercontrol": "false",
|
||||
"c_use_crc": "false",
|
||||
"c_use_crc": "true",
|
||||
"supportlevel": 0,
|
||||
"c_use_byteswap": "false",
|
||||
"c_cpll_fbdiv": 2,
|
||||
|
|
@ -541,104 +541,16 @@
|
|||
"ports": [
|
||||
{
|
||||
"role": "master",
|
||||
"target": "axis_interconnect_0_xbar:S03_AXIS",
|
||||
"target": "crossbar_axis_interconnect_0_xbar:S03_AXIS",
|
||||
"name": "USER_DATA_M_AXI_RX"
|
||||
},
|
||||
{
|
||||
"role": "slave",
|
||||
"target": "axis_interconnect_0_xbar:M03_AXIS",
|
||||
"target": "crossbar_axis_interconnect_0_xbar:M03_AXIS",
|
||||
"name": "USER_DATA_S_AXI_TX"
|
||||
}
|
||||
]
|
||||
},
|
||||
"axi_dma_0": {
|
||||
"vlnv": "xilinx.com:ip:axi_dma:7.1",
|
||||
"parameters": {
|
||||
"c_s_axi_lite_addr_width": 10,
|
||||
"c_s_axi_lite_data_width": 32,
|
||||
"c_dlytmr_resolution": 125,
|
||||
"c_prmry_is_aclk_async": 0,
|
||||
"c_enable_multi_channel": 0,
|
||||
"c_num_mm2s_channels": 1,
|
||||
"c_num_s2mm_channels": 1,
|
||||
"c_include_sg": 1,
|
||||
"c_sg_include_stscntrl_strm": 0,
|
||||
"c_sg_use_stsapp_length": 0,
|
||||
"c_sg_length_width": 14,
|
||||
"c_m_axi_sg_addr_width": 32,
|
||||
"c_m_axi_sg_data_width": 32,
|
||||
"c_m_axis_mm2s_cntrl_tdata_width": 32,
|
||||
"c_s_axis_s2mm_sts_tdata_width": 32,
|
||||
"c_micro_dma": 0,
|
||||
"c_include_mm2s": 1,
|
||||
"c_include_mm2s_sf": 1,
|
||||
"c_mm2s_burst_size": 16,
|
||||
"c_m_axi_mm2s_addr_width": 32,
|
||||
"c_m_axi_mm2s_data_width": 32,
|
||||
"c_m_axis_mm2s_tdata_width": 32,
|
||||
"c_include_mm2s_dre": 0,
|
||||
"c_include_s2mm": 1,
|
||||
"c_include_s2mm_sf": 1,
|
||||
"c_s2mm_burst_size": 16,
|
||||
"c_m_axi_s2mm_addr_width": 32,
|
||||
"c_m_axi_s2mm_data_width": 32,
|
||||
"c_s_axis_s2mm_tdata_width": 32,
|
||||
"c_include_s2mm_dre": 0,
|
||||
"c_increase_throughput": 0,
|
||||
"c_family": "virtex7",
|
||||
"component_name": "design_1_axi_dma_0_0",
|
||||
"c_addr_width": 32,
|
||||
"c_single_interface": 0,
|
||||
"edk_iptype": "PERIPHERAL",
|
||||
"c_baseaddr": 12288,
|
||||
"c_highaddr": 13311
|
||||
},
|
||||
"memory-view": {
|
||||
"M_AXI_SG": {
|
||||
"axi_pcie_0": {
|
||||
"BAR0": {
|
||||
"baseaddr": 0,
|
||||
"highaddr": 4294967295,
|
||||
"size": 4294967296
|
||||
}
|
||||
}
|
||||
},
|
||||
"M_AXI_MM2S": {
|
||||
"axi_pcie_0": {
|
||||
"BAR0": {
|
||||
"baseaddr": 0,
|
||||
"highaddr": 4294967295,
|
||||
"size": 4294967296
|
||||
}
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM": {
|
||||
"axi_pcie_0": {
|
||||
"BAR0": {
|
||||
"baseaddr": 0,
|
||||
"highaddr": 4294967295,
|
||||
"size": 4294967296
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": [
|
||||
{
|
||||
"role": "master",
|
||||
"target": "axis_interconnect_0_xbar:S04_AXIS",
|
||||
"name": "MM2S"
|
||||
},
|
||||
{
|
||||
"role": "slave",
|
||||
"target": "axis_interconnect_0_xbar:M04_AXIS",
|
||||
"name": "S2MM"
|
||||
}
|
||||
],
|
||||
"irqs": {
|
||||
"mm2s_introut": "axi_pcie_intc_0:0",
|
||||
"s2mm_introut": "axi_pcie_intc_0:1"
|
||||
}
|
||||
},
|
||||
"axi_gpio_0": {
|
||||
"vlnv": "xilinx.com:ip:axi_gpio:2.0",
|
||||
"parameters": {
|
||||
|
|
@ -666,234 +578,13 @@
|
|||
"c_highaddr": 127
|
||||
}
|
||||
},
|
||||
"axi_pcie_0": {
|
||||
"vlnv": "xilinx.com:ip:axi_pcie:2.9",
|
||||
"parameters": {
|
||||
"c_family": "virtex7",
|
||||
"c_instance": "design_1_axi_pcie_0_1",
|
||||
"c_s_axi_id_width": 2,
|
||||
"c_s_axi_addr_width": 32,
|
||||
"c_s_axi_data_width": 64,
|
||||
"c_m_axi_addr_width": 32,
|
||||
"c_m_axi_data_width": 64,
|
||||
"c_no_of_lanes": 1,
|
||||
"c_max_link_speed": 1,
|
||||
"c_pcie_use_mode": "3.0",
|
||||
"c_device_id": 28705,
|
||||
"c_vendor_id": 4334,
|
||||
"c_class_code": 360448,
|
||||
"c_ref_clk_freq": 0,
|
||||
"c_rev_id": 0,
|
||||
"c_subsystem_id": 7,
|
||||
"c_subsystem_vendor_id": 4334,
|
||||
"c_pcie_cap_slot_implemented": 0,
|
||||
"c_slot_clock_config": "TRUE",
|
||||
"c_msi_decode_enable": "TRUE",
|
||||
"c_int_fifo_depth": 0,
|
||||
"c_num_msi_req": 5,
|
||||
"c_interrupt_pin": 0,
|
||||
"c_comp_timeout": 0,
|
||||
"c_include_rc": 0,
|
||||
"c_s_axi_supports_narrow_burst": 0,
|
||||
"c_include_baroffset_reg": 1,
|
||||
"c_axibar_num": 1,
|
||||
"c_axibar2pciebar_0": 0,
|
||||
"c_axibar2pciebar_1": 0,
|
||||
"c_axibar2pciebar_2": 0,
|
||||
"c_axibar2pciebar_3": 0,
|
||||
"c_axibar2pciebar_4": 0,
|
||||
"c_axibar2pciebar_5": 0,
|
||||
"c_axibar_as_0": 0,
|
||||
"c_axibar_as_1": 0,
|
||||
"c_axibar_as_2": 0,
|
||||
"c_axibar_as_3": 0,
|
||||
"c_axibar_as_4": 0,
|
||||
"c_axibar_as_5": 0,
|
||||
"c_axibar_0": 0,
|
||||
"c_axibar_highaddr_0": 4294967295,
|
||||
"c_axibar_1": 4294967295,
|
||||
"c_axibar_highaddr_1": 0,
|
||||
"c_axibar_2": 4294967295,
|
||||
"c_axibar_highaddr_2": 0,
|
||||
"c_axibar_3": 4294967295,
|
||||
"c_axibar_highaddr_3": 0,
|
||||
"c_axibar_4": 4294967295,
|
||||
"c_axibar_highaddr_4": 0,
|
||||
"c_axibar_5": 4294967295,
|
||||
"c_axibar_highaddr_5": 0,
|
||||
"c_pciebar_num": 1,
|
||||
"c_pciebar_as": 0,
|
||||
"c_pciebar_len_0": 20,
|
||||
"c_pciebar2axibar_0": 0,
|
||||
"c_pciebar2axibar_0_sec": 1,
|
||||
"c_pciebar_len_1": 16,
|
||||
"c_pciebar2axibar_1": 4294967295,
|
||||
"c_pciebar2axibar_1_sec": 1,
|
||||
"c_pciebar_len_2": 16,
|
||||
"c_pciebar2axibar_2": 4294967295,
|
||||
"c_pciebar2axibar_2_sec": 1,
|
||||
"c_pcie_blk_locn": 3,
|
||||
"c_xlnx_ref_board": "VC707",
|
||||
"pcie_ext_clk": "FALSE",
|
||||
"pcie_ext_gt_common": "FALSE",
|
||||
"ext_ch_gt_drp": "FALSE",
|
||||
"shared_logic_in_core": "false",
|
||||
"transceiver_ctrl_status_ports": "FALSE",
|
||||
"ext_pipe_interface": "FALSE",
|
||||
"c_device": "xc7vx485t",
|
||||
"c_speed": -2,
|
||||
"axi_aclk_loopback": "false",
|
||||
"no_slv_err": "false",
|
||||
"c_rp_bar_hide": "FALSE",
|
||||
"enable_jtag_dbg": "false",
|
||||
"c_axibar_chk_slv_err": "false",
|
||||
"reduce_oob_freq": "false",
|
||||
"component_name": "design_1_axi_pcie_0_1",
|
||||
"include_rc": "PCI_Express_Endpoint_device",
|
||||
"ref_clk_freq": "100_MHz",
|
||||
"slot_clock_config": "true",
|
||||
"pcie_use_mode": "GES_and_Production",
|
||||
"no_of_lanes": "X1",
|
||||
"max_link_speed": "5.0_GT/s",
|
||||
"vendor_id": 4334,
|
||||
"device_id": 28705,
|
||||
"rev_id": 0,
|
||||
"subsystem_vendor_id": 4334,
|
||||
"subsystem_id": 7,
|
||||
"enable_class_code": "true",
|
||||
"class_code": 360448,
|
||||
"base_class_menu": "Memory_controller",
|
||||
"sub_class_interface_menu": "Other_memory_controller",
|
||||
"bar0_enabled": "true",
|
||||
"bar1_enabled": "false",
|
||||
"bar2_enabled": "false",
|
||||
"bar0_type": "Memory",
|
||||
"bar1_type": "N/A",
|
||||
"bar2_type": "N/A",
|
||||
"bar0_scale": "Megabytes",
|
||||
"bar1_scale": "N/A",
|
||||
"bar2_scale": "N/A",
|
||||
"bar0_size": 1,
|
||||
"bar1_size": 8,
|
||||
"bar2_size": 8,
|
||||
"pciebar2axibar_0": 0,
|
||||
"pciebar2axibar_1": 4294967295,
|
||||
"pciebar2axibar_2": 4294967295,
|
||||
"pciebar2axibar_1_sec": 1,
|
||||
"pciebar2axibar_0_sec": 1,
|
||||
"pciebar2axibar_2_sec": 1,
|
||||
"interrupt_pin": "false",
|
||||
"msi_decode_enabled": "true",
|
||||
"num_msi_req": 5,
|
||||
"int_fifo_depth": 16,
|
||||
"comp_timeout": "50us",
|
||||
"include_baroffset_reg": "true",
|
||||
"axibar_as_0": "false",
|
||||
"axibar_as_1": "false",
|
||||
"axibar_as_2": "false",
|
||||
"axibar_as_3": "false",
|
||||
"axibar_as_4": "false",
|
||||
"axibar_as_5": "false",
|
||||
"axibar_1": 4294967295,
|
||||
"axibar_2": 4294967295,
|
||||
"axibar_3": 4294967295,
|
||||
"axibar_4": 4294967295,
|
||||
"axibar_5": 4294967295,
|
||||
"axibar_highaddr_1": 0,
|
||||
"axibar_highaddr_2": 0,
|
||||
"axibar_highaddr_3": 0,
|
||||
"axibar_highaddr_4": 0,
|
||||
"axibar_highaddr_5": 0,
|
||||
"axibar2pciebar_0": 0,
|
||||
"axibar2pciebar_1": 0,
|
||||
"axibar2pciebar_2": 0,
|
||||
"axibar2pciebar_3": 0,
|
||||
"axibar2pciebar_4": 0,
|
||||
"axibar2pciebar_5": 0,
|
||||
"baseaddr": 4096,
|
||||
"highaddr": 8191,
|
||||
"s_axi_id_width": 2,
|
||||
"s_axi_addr_width": 32,
|
||||
"s_axi_data_width": 64,
|
||||
"m_axi_addr_width": 32,
|
||||
"m_axi_data_width": 64,
|
||||
"s_axi_supports_narrow_burst": "false",
|
||||
"bar_64bit": "false",
|
||||
"xlnx_ref_board": "VC707",
|
||||
"pcie_blk_locn": "X1Y0",
|
||||
"axibar_num": 1,
|
||||
"en_ext_clk": "false",
|
||||
"en_ext_gt_common": "false",
|
||||
"en_ext_ch_gt_drp": "false",
|
||||
"en_transceiver_status_ports": "false",
|
||||
"en_ext_pipe_interface": "false",
|
||||
"rp_bar_hide": "false",
|
||||
"edk_iptype": "PERIPHERAL",
|
||||
"axibar_0": 0,
|
||||
"axibar_highaddr_0": 4294967295
|
||||
},
|
||||
"memory-view": {
|
||||
"M_AXI": {
|
||||
"axi_gpio_0": {
|
||||
"Reg": {
|
||||
"baseaddr": 0,
|
||||
"highaddr": 127,
|
||||
"size": 128
|
||||
}
|
||||
},
|
||||
"axis_interconnect_0_xbar": {
|
||||
"Reg": {
|
||||
"baseaddr": 4096,
|
||||
"highaddr": 5119,
|
||||
"size": 1024
|
||||
}
|
||||
},
|
||||
"axi_pcie_intc_0": {
|
||||
"reg0": {
|
||||
"baseaddr": 8192,
|
||||
"highaddr": 9215,
|
||||
"size": 1024
|
||||
}
|
||||
},
|
||||
"axi_dma_0": {
|
||||
"Reg": {
|
||||
"baseaddr": 12288,
|
||||
"highaddr": 13311,
|
||||
"size": 1024
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"axi_bars": {
|
||||
"BAR0": {
|
||||
"translation": 0,
|
||||
"baseaddr": 0,
|
||||
"highaddr": 4294967295,
|
||||
"size": 4294967296
|
||||
}
|
||||
},
|
||||
"pcie_bars": {
|
||||
"BAR0": {
|
||||
"translation": 0
|
||||
}
|
||||
}
|
||||
},
|
||||
"axi_pcie_intc_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axi_pcie_intc:1.0",
|
||||
"parameters": {
|
||||
"component_name": "design_1_axi_pcie_intc_0_0",
|
||||
"edk_iptype": "PERIPHERAL",
|
||||
"c_baseaddr": 8192,
|
||||
"c_highaddr": 9215
|
||||
}
|
||||
},
|
||||
"axis_interconnect_0_xbar": {
|
||||
"crossbar_axis_interconnect_0_xbar": {
|
||||
"vlnv": "xilinx.com:ip:axis_switch:1.1",
|
||||
"parameters": {
|
||||
"c_family": "virtex7",
|
||||
"c_num_si_slots": 5,
|
||||
"c_num_si_slots": 6,
|
||||
"c_log_si_slots": 3,
|
||||
"c_num_mi_slots": 5,
|
||||
"c_num_mi_slots": 6,
|
||||
"c_axis_tdata_width": 32,
|
||||
"c_axis_tid_width": 1,
|
||||
"c_axis_tdest_width": 1,
|
||||
|
|
@ -906,15 +597,15 @@
|
|||
"c_arb_algorithm": 0,
|
||||
"c_output_reg": 0,
|
||||
"c_decoder_reg": 1,
|
||||
"c_m_axis_connectivity_array": 33554431,
|
||||
"c_m_axis_basetdest_array": 10,
|
||||
"c_m_axis_hightdest_array": 10,
|
||||
"c_m_axis_connectivity_array": 68719476735,
|
||||
"c_m_axis_basetdest_array": 42,
|
||||
"c_m_axis_hightdest_array": 42,
|
||||
"c_routing_mode": 1,
|
||||
"c_s_axi_ctrl_addr_width": 7,
|
||||
"c_s_axi_ctrl_data_width": 32,
|
||||
"c_common_clock": 0,
|
||||
"num_si": 5,
|
||||
"num_mi": 5,
|
||||
"num_si": 6,
|
||||
"num_mi": 6,
|
||||
"routing_mode": 1,
|
||||
"has_tready": 1,
|
||||
"tdata_num_bytes": 4,
|
||||
|
|
@ -1222,60 +913,468 @@
|
|||
"m15_s15_connectivity": 1,
|
||||
"component_name": "design_1_xbar_0",
|
||||
"edk_iptype": "PERIPHERAL",
|
||||
"c_baseaddr": 0,
|
||||
"c_highaddr": 1023
|
||||
"c_baseaddr": 4096,
|
||||
"c_highaddr": 5119
|
||||
},
|
||||
"ports": [
|
||||
{
|
||||
"role": "slave",
|
||||
"target": "aurora_8b10b_ch0:USER_DATA_M_AXI_RX",
|
||||
"target": "aurora_aurora_8b10b_ch0:USER_DATA_M_AXI_RX",
|
||||
"name": "S00_AXIS"
|
||||
},
|
||||
{
|
||||
"role": "master",
|
||||
"target": "aurora_8b10b_ch0:USER_DATA_S_AXI_TX",
|
||||
"target": "aurora_aurora_8b10b_ch0:USER_DATA_S_AXI_TX",
|
||||
"name": "M00_AXIS"
|
||||
},
|
||||
{
|
||||
"role": "slave",
|
||||
"target": "aurora_8b10b_ch1:USER_DATA_M_AXI_RX",
|
||||
"target": "aurora_aurora_8b10b_ch1:USER_DATA_M_AXI_RX",
|
||||
"name": "S01_AXIS"
|
||||
},
|
||||
{
|
||||
"role": "master",
|
||||
"target": "aurora_8b10b_ch1:USER_DATA_S_AXI_TX",
|
||||
"target": "aurora_aurora_8b10b_ch1:USER_DATA_S_AXI_TX",
|
||||
"name": "M01_AXIS"
|
||||
},
|
||||
{
|
||||
"role": "slave",
|
||||
"target": "aurora_8b10b_ch2:USER_DATA_M_AXI_RX",
|
||||
"target": "aurora_aurora_8b10b_ch2:USER_DATA_M_AXI_RX",
|
||||
"name": "S02_AXIS"
|
||||
},
|
||||
{
|
||||
"role": "master",
|
||||
"target": "aurora_8b10b_ch2:USER_DATA_S_AXI_TX",
|
||||
"target": "aurora_aurora_8b10b_ch2:USER_DATA_S_AXI_TX",
|
||||
"name": "M02_AXIS"
|
||||
},
|
||||
{
|
||||
"role": "slave",
|
||||
"target": "aurora_8b10b_ch3:USER_DATA_M_AXI_RX",
|
||||
"target": "aurora_aurora_8b10b_ch3:USER_DATA_M_AXI_RX",
|
||||
"name": "S03_AXIS"
|
||||
},
|
||||
{
|
||||
"role": "master",
|
||||
"target": "aurora_8b10b_ch3:USER_DATA_S_AXI_TX",
|
||||
"target": "aurora_aurora_8b10b_ch3:USER_DATA_S_AXI_TX",
|
||||
"name": "M03_AXIS"
|
||||
},
|
||||
{
|
||||
"role": "slave",
|
||||
"target": "axi_dma_0:MM2S",
|
||||
"target": "dma_pcie_axi_dma_0:MM2S",
|
||||
"name": "S04_AXIS"
|
||||
},
|
||||
{
|
||||
"role": "master",
|
||||
"target": "axi_dma_0:S2MM",
|
||||
"target": "dma_pcie_axi_dma_0:S2MM",
|
||||
"name": "M04_AXIS"
|
||||
},
|
||||
{
|
||||
"role": "slave",
|
||||
"target": "dino_dinoif_adc_0:M00_AXIS",
|
||||
"name": "S05_AXIS"
|
||||
},
|
||||
{
|
||||
"role": "master",
|
||||
"target": "dino_dinoif_dac_0:S00_AXIS",
|
||||
"name": "M05_AXIS"
|
||||
}
|
||||
]
|
||||
],
|
||||
"num_ports": 6
|
||||
},
|
||||
"dino_axi_iic_0": {
|
||||
"vlnv": "xilinx.com:ip:axi_iic:2.1",
|
||||
"parameters": {
|
||||
"c_family": "virtex7",
|
||||
"c_s_axi_addr_width": 9,
|
||||
"c_s_axi_data_width": 32,
|
||||
"c_iic_freq": 100000,
|
||||
"c_ten_bit_adr": 0,
|
||||
"c_gpo_width": 1,
|
||||
"c_s_axi_aclk_freq_hz": 125000000,
|
||||
"c_scl_inertial_delay": 0,
|
||||
"c_sda_inertial_delay": 0,
|
||||
"c_sda_level": 1,
|
||||
"c_smbus_pmbus_host": 0,
|
||||
"c_disable_setup_violation_check": 0,
|
||||
"c_static_timing_reg_width": 0,
|
||||
"c_timing_reg_width": 32,
|
||||
"c_default_value": 0,
|
||||
"component_name": "design_1_axi_iic_0_0",
|
||||
"ten_bit_adr": "7_bit",
|
||||
"axi_aclk_freq_mhz": "125.0",
|
||||
"iic_freq_khz": 100,
|
||||
"use_board_flow": "false",
|
||||
"iic_board_interface": "Custom",
|
||||
"edk_iptype": "PERIPHERAL",
|
||||
"c_baseaddr": 16384,
|
||||
"c_highaddr": 17407
|
||||
},
|
||||
"irqs": {
|
||||
"iic2intc_irpt": "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:2"
|
||||
}
|
||||
},
|
||||
"dino_registerif_0": {
|
||||
"vlnv": "xilinx.com:module_ref:registerif:1.0",
|
||||
"parameters": {
|
||||
"c_axi_data_width": 32,
|
||||
"c_axi_addr_width": 32,
|
||||
"reg_addr_width": 10,
|
||||
"component_name": "design_1_registerif_0_0",
|
||||
"edk_iptype": "PERIPHERAL",
|
||||
"c_baseaddr": 20480,
|
||||
"c_highaddr": 21503
|
||||
}
|
||||
},
|
||||
"dma_pcie_axi_dma_0": {
|
||||
"vlnv": "xilinx.com:ip:axi_dma:7.1",
|
||||
"parameters": {
|
||||
"c_s_axi_lite_addr_width": 10,
|
||||
"c_s_axi_lite_data_width": 32,
|
||||
"c_dlytmr_resolution": 125,
|
||||
"c_prmry_is_aclk_async": 0,
|
||||
"c_enable_multi_channel": 0,
|
||||
"c_num_mm2s_channels": 1,
|
||||
"c_num_s2mm_channels": 1,
|
||||
"c_include_sg": 1,
|
||||
"c_sg_include_stscntrl_strm": 0,
|
||||
"c_sg_use_stsapp_length": 0,
|
||||
"c_sg_length_width": 14,
|
||||
"c_m_axi_sg_addr_width": 32,
|
||||
"c_m_axi_sg_data_width": 32,
|
||||
"c_m_axis_mm2s_cntrl_tdata_width": 32,
|
||||
"c_s_axis_s2mm_sts_tdata_width": 32,
|
||||
"c_micro_dma": 0,
|
||||
"c_include_mm2s": 1,
|
||||
"c_include_mm2s_sf": 1,
|
||||
"c_mm2s_burst_size": 16,
|
||||
"c_m_axi_mm2s_addr_width": 32,
|
||||
"c_m_axi_mm2s_data_width": 32,
|
||||
"c_m_axis_mm2s_tdata_width": 32,
|
||||
"c_include_mm2s_dre": 0,
|
||||
"c_include_s2mm": 1,
|
||||
"c_include_s2mm_sf": 1,
|
||||
"c_s2mm_burst_size": 16,
|
||||
"c_m_axi_s2mm_addr_width": 32,
|
||||
"c_m_axi_s2mm_data_width": 32,
|
||||
"c_s_axis_s2mm_tdata_width": 32,
|
||||
"c_include_s2mm_dre": 0,
|
||||
"c_increase_throughput": 0,
|
||||
"c_family": "virtex7",
|
||||
"component_name": "design_1_axi_dma_0_0",
|
||||
"c_addr_width": 32,
|
||||
"c_single_interface": 0,
|
||||
"edk_iptype": "PERIPHERAL",
|
||||
"c_baseaddr": 12288,
|
||||
"c_highaddr": 13311
|
||||
},
|
||||
"memory-view": {
|
||||
"M_AXI_SG": {
|
||||
"dma_pcie_pcie_axi_pcie_0": {
|
||||
"BAR0": {
|
||||
"baseaddr": 0,
|
||||
"highaddr": 4294967295,
|
||||
"size": 4294967296
|
||||
}
|
||||
}
|
||||
},
|
||||
"M_AXI_MM2S": {
|
||||
"dma_pcie_pcie_axi_pcie_0": {
|
||||
"BAR0": {
|
||||
"baseaddr": 0,
|
||||
"highaddr": 4294967295,
|
||||
"size": 4294967296
|
||||
}
|
||||
}
|
||||
},
|
||||
"M_AXI_S2MM": {
|
||||
"dma_pcie_pcie_axi_pcie_0": {
|
||||
"BAR0": {
|
||||
"baseaddr": 0,
|
||||
"highaddr": 4294967295,
|
||||
"size": 4294967296
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": [
|
||||
{
|
||||
"role": "master",
|
||||
"target": "crossbar_axis_interconnect_0_xbar:S04_AXIS",
|
||||
"name": "MM2S"
|
||||
},
|
||||
{
|
||||
"role": "slave",
|
||||
"target": "crossbar_axis_interconnect_0_xbar:M04_AXIS",
|
||||
"name": "S2MM"
|
||||
}
|
||||
],
|
||||
"irqs": {
|
||||
"mm2s_introut": "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:0",
|
||||
"s2mm_introut": "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:1"
|
||||
}
|
||||
},
|
||||
"dma_pcie_axi_read_cache_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axi_read_cache:1.0",
|
||||
"parameters": {
|
||||
"c_axi_data_width": 32,
|
||||
"c_axi_addr_width": 32,
|
||||
"word_num": 16,
|
||||
"component_name": "design_1_axi_read_cache_0_0",
|
||||
"edk_iptype": "PERIPHERAL",
|
||||
"c_baseaddr": 24576,
|
||||
"c_highaddr": 25599
|
||||
},
|
||||
"memory-view": {
|
||||
"M_AXI": {
|
||||
"dma_pcie_pcie_axi_pcie_0": {
|
||||
"BAR0": {
|
||||
"baseaddr": 0,
|
||||
"highaddr": 4294967295,
|
||||
"size": 4294967296
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"dma_pcie_pcie_axi_pcie_0": {
|
||||
"vlnv": "xilinx.com:ip:axi_pcie:2.9",
|
||||
"parameters": {
|
||||
"c_family": "virtex7",
|
||||
"c_instance": "design_1_axi_pcie_0_1",
|
||||
"c_s_axi_id_width": 2,
|
||||
"c_s_axi_addr_width": 32,
|
||||
"c_s_axi_data_width": 64,
|
||||
"c_m_axi_addr_width": 32,
|
||||
"c_m_axi_data_width": 64,
|
||||
"c_no_of_lanes": 1,
|
||||
"c_max_link_speed": 1,
|
||||
"c_pcie_use_mode": "3.0",
|
||||
"c_device_id": 28705,
|
||||
"c_vendor_id": 4334,
|
||||
"c_class_code": 360448,
|
||||
"c_ref_clk_freq": 0,
|
||||
"c_rev_id": 0,
|
||||
"c_subsystem_id": 7,
|
||||
"c_subsystem_vendor_id": 4334,
|
||||
"c_pcie_cap_slot_implemented": 0,
|
||||
"c_slot_clock_config": "TRUE",
|
||||
"c_msi_decode_enable": "TRUE",
|
||||
"c_int_fifo_depth": 0,
|
||||
"c_num_msi_req": 4,
|
||||
"c_interrupt_pin": 0,
|
||||
"c_comp_timeout": 0,
|
||||
"c_include_rc": 0,
|
||||
"c_s_axi_supports_narrow_burst": 1,
|
||||
"c_include_baroffset_reg": 1,
|
||||
"c_axibar_num": 1,
|
||||
"c_axibar2pciebar_0": 0,
|
||||
"c_axibar2pciebar_1": 0,
|
||||
"c_axibar2pciebar_2": 0,
|
||||
"c_axibar2pciebar_3": 0,
|
||||
"c_axibar2pciebar_4": 0,
|
||||
"c_axibar2pciebar_5": 0,
|
||||
"c_axibar_as_0": 0,
|
||||
"c_axibar_as_1": 0,
|
||||
"c_axibar_as_2": 0,
|
||||
"c_axibar_as_3": 0,
|
||||
"c_axibar_as_4": 0,
|
||||
"c_axibar_as_5": 0,
|
||||
"c_axibar_0": 0,
|
||||
"c_axibar_highaddr_0": 4294967295,
|
||||
"c_axibar_1": 4294967295,
|
||||
"c_axibar_highaddr_1": 0,
|
||||
"c_axibar_2": 4294967295,
|
||||
"c_axibar_highaddr_2": 0,
|
||||
"c_axibar_3": 4294967295,
|
||||
"c_axibar_highaddr_3": 0,
|
||||
"c_axibar_4": 4294967295,
|
||||
"c_axibar_highaddr_4": 0,
|
||||
"c_axibar_5": 4294967295,
|
||||
"c_axibar_highaddr_5": 0,
|
||||
"c_pciebar_num": 1,
|
||||
"c_pciebar_as": 0,
|
||||
"c_pciebar_len_0": 20,
|
||||
"c_pciebar2axibar_0": 0,
|
||||
"c_pciebar2axibar_0_sec": 1,
|
||||
"c_pciebar_len_1": 16,
|
||||
"c_pciebar2axibar_1": 4294967295,
|
||||
"c_pciebar2axibar_1_sec": 1,
|
||||
"c_pciebar_len_2": 16,
|
||||
"c_pciebar2axibar_2": 4294967295,
|
||||
"c_pciebar2axibar_2_sec": 1,
|
||||
"c_pcie_blk_locn": 3,
|
||||
"c_xlnx_ref_board": "VC707",
|
||||
"pcie_ext_clk": "FALSE",
|
||||
"pcie_ext_gt_common": "FALSE",
|
||||
"ext_ch_gt_drp": "FALSE",
|
||||
"shared_logic_in_core": "false",
|
||||
"transceiver_ctrl_status_ports": "FALSE",
|
||||
"ext_pipe_interface": "FALSE",
|
||||
"c_device": "xc7vx485t",
|
||||
"c_speed": -2,
|
||||
"axi_aclk_loopback": "false",
|
||||
"no_slv_err": "false",
|
||||
"c_rp_bar_hide": "FALSE",
|
||||
"enable_jtag_dbg": "false",
|
||||
"c_axibar_chk_slv_err": "false",
|
||||
"reduce_oob_freq": "false",
|
||||
"component_name": "design_1_axi_pcie_0_1",
|
||||
"include_rc": "PCI_Express_Endpoint_device",
|
||||
"ref_clk_freq": "100_MHz",
|
||||
"slot_clock_config": "true",
|
||||
"pcie_use_mode": "GES_and_Production",
|
||||
"no_of_lanes": "X1",
|
||||
"max_link_speed": "5.0_GT/s",
|
||||
"vendor_id": 4334,
|
||||
"device_id": 28705,
|
||||
"rev_id": 0,
|
||||
"subsystem_vendor_id": 4334,
|
||||
"subsystem_id": 7,
|
||||
"enable_class_code": "true",
|
||||
"class_code": 360448,
|
||||
"base_class_menu": "Memory_controller",
|
||||
"sub_class_interface_menu": "Other_memory_controller",
|
||||
"bar0_enabled": "true",
|
||||
"bar1_enabled": "false",
|
||||
"bar2_enabled": "false",
|
||||
"bar0_type": "Memory",
|
||||
"bar1_type": "N/A",
|
||||
"bar2_type": "N/A",
|
||||
"bar0_scale": "Megabytes",
|
||||
"bar1_scale": "N/A",
|
||||
"bar2_scale": "N/A",
|
||||
"bar0_size": 1,
|
||||
"bar1_size": 8,
|
||||
"bar2_size": 8,
|
||||
"pciebar2axibar_0": 0,
|
||||
"pciebar2axibar_1": 4294967295,
|
||||
"pciebar2axibar_2": 4294967295,
|
||||
"pciebar2axibar_1_sec": 1,
|
||||
"pciebar2axibar_0_sec": 1,
|
||||
"pciebar2axibar_2_sec": 1,
|
||||
"interrupt_pin": "false",
|
||||
"msi_decode_enabled": "true",
|
||||
"num_msi_req": 4,
|
||||
"int_fifo_depth": 16,
|
||||
"comp_timeout": "50us",
|
||||
"include_baroffset_reg": "true",
|
||||
"axibar_as_0": "false",
|
||||
"axibar_as_1": "false",
|
||||
"axibar_as_2": "false",
|
||||
"axibar_as_3": "false",
|
||||
"axibar_as_4": "false",
|
||||
"axibar_as_5": "false",
|
||||
"axibar_1": 4294967295,
|
||||
"axibar_2": 4294967295,
|
||||
"axibar_3": 4294967295,
|
||||
"axibar_4": 4294967295,
|
||||
"axibar_5": 4294967295,
|
||||
"axibar_highaddr_1": 0,
|
||||
"axibar_highaddr_2": 0,
|
||||
"axibar_highaddr_3": 0,
|
||||
"axibar_highaddr_4": 0,
|
||||
"axibar_highaddr_5": 0,
|
||||
"axibar2pciebar_0": 0,
|
||||
"axibar2pciebar_1": 0,
|
||||
"axibar2pciebar_2": 0,
|
||||
"axibar2pciebar_3": 0,
|
||||
"axibar2pciebar_4": 0,
|
||||
"axibar2pciebar_5": 0,
|
||||
"baseaddr": 4096,
|
||||
"highaddr": 8191,
|
||||
"s_axi_id_width": 2,
|
||||
"s_axi_addr_width": 32,
|
||||
"s_axi_data_width": 64,
|
||||
"m_axi_addr_width": 32,
|
||||
"m_axi_data_width": 64,
|
||||
"s_axi_supports_narrow_burst": "true",
|
||||
"bar_64bit": "false",
|
||||
"xlnx_ref_board": "VC707",
|
||||
"pcie_blk_locn": "X1Y0",
|
||||
"axibar_num": 1,
|
||||
"en_ext_clk": "false",
|
||||
"en_ext_gt_common": "false",
|
||||
"en_ext_ch_gt_drp": "false",
|
||||
"en_transceiver_status_ports": "false",
|
||||
"en_ext_pipe_interface": "false",
|
||||
"rp_bar_hide": "false",
|
||||
"edk_iptype": "PERIPHERAL",
|
||||
"axibar_0": 0,
|
||||
"axibar_highaddr_0": 4294967295
|
||||
},
|
||||
"memory-view": {
|
||||
"M_AXI": {
|
||||
"axi_gpio_0": {
|
||||
"Reg": {
|
||||
"baseaddr": 0,
|
||||
"highaddr": 127,
|
||||
"size": 128
|
||||
}
|
||||
},
|
||||
"crossbar_axis_interconnect_0_xbar": {
|
||||
"Reg": {
|
||||
"baseaddr": 4096,
|
||||
"highaddr": 5119,
|
||||
"size": 1024
|
||||
}
|
||||
},
|
||||
"dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0": {
|
||||
"reg0": {
|
||||
"baseaddr": 8192,
|
||||
"highaddr": 9215,
|
||||
"size": 1024
|
||||
}
|
||||
},
|
||||
"dma_pcie_axi_dma_0": {
|
||||
"Reg": {
|
||||
"baseaddr": 12288,
|
||||
"highaddr": 13311,
|
||||
"size": 1024
|
||||
}
|
||||
},
|
||||
"dino_axi_iic_0": {
|
||||
"Reg": {
|
||||
"baseaddr": 16384,
|
||||
"highaddr": 17407,
|
||||
"size": 1024
|
||||
}
|
||||
},
|
||||
"dino_registerif_0": {
|
||||
"reg0": {
|
||||
"baseaddr": 20480,
|
||||
"highaddr": 21503,
|
||||
"size": 1024
|
||||
}
|
||||
},
|
||||
"dma_pcie_axi_read_cache_0": {
|
||||
"reg0": {
|
||||
"baseaddr": 24576,
|
||||
"highaddr": 25599,
|
||||
"size": 1024
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"axi_bars": {
|
||||
"BAR0": {
|
||||
"translation": 0,
|
||||
"baseaddr": 0,
|
||||
"highaddr": 4294967295,
|
||||
"size": 4294967296
|
||||
}
|
||||
},
|
||||
"pcie_bars": {
|
||||
"BAR0": {
|
||||
"translation": 0
|
||||
}
|
||||
}
|
||||
},
|
||||
"dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axi_pcie_intc:1.0",
|
||||
"parameters": {
|
||||
"component_name": "design_1_axi_pcie_intc_0_0",
|
||||
"edk_iptype": "PERIPHERAL",
|
||||
"c_baseaddr": 8192,
|
||||
"c_highaddr": 9215
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,9 +2,9 @@
|
|||
"fpgas": {
|
||||
"vc707": {
|
||||
"id": "10ee:7021",
|
||||
"slot": "0000:88:00.0",
|
||||
"slot": "0000:89:00.0",
|
||||
"do_reset": true,
|
||||
"ips": "vc707-xbar-pcie-dino/vc707-xbar-pcie-dino-v2.json",
|
||||
"ips": "vc707-xbar-pcie/vc707-xbar-pcie.json",
|
||||
"polling": true,
|
||||
"interface": "pcie"
|
||||
}
|
||||
|
|
|
|||
2485
etc/fpga/zcu106-dino/zcu106-dino.json
Normal file
2485
etc/fpga/zcu106-dino/zcu106-dino.json
Normal file
File diff suppressed because it is too large
Load diff
47
fpga/include/villas/fpga/ips/axis_cache.hpp
Normal file
47
fpga/include/villas/fpga/ips/axis_cache.hpp
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/* Driver for AXI Stream read cache. This module is used to lower latency of
|
||||
* a DMA Scatter Gather engine's descriptor fetching. The driver allows for
|
||||
* invalidating the cache.
|
||||
*
|
||||
* Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
|
||||
* SPDX-FileCopyrightText: 2024 Niklas Eiling
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <villas/fpga/node.hpp>
|
||||
|
||||
namespace villas {
|
||||
namespace fpga {
|
||||
namespace ip {
|
||||
|
||||
class AxisCache : public Node {
|
||||
public:
|
||||
AxisCache();
|
||||
virtual ~AxisCache();
|
||||
virtual bool init() override;
|
||||
virtual bool check() override;
|
||||
void invalidate();
|
||||
|
||||
protected:
|
||||
const size_t registerNum = 1;
|
||||
const size_t registerSize = 32;
|
||||
static constexpr char registerMemory[] = "reg0";
|
||||
std::list<MemoryBlockName> getMemoryBlocks() const override {
|
||||
return {registerMemory};
|
||||
}
|
||||
bool setRegister(size_t reg, uint32_t value);
|
||||
bool getRegister(size_t reg, uint32_t &value);
|
||||
bool resetRegister(size_t reg);
|
||||
bool resetAllRegisters();
|
||||
};
|
||||
|
||||
} // namespace ip
|
||||
} // namespace fpga
|
||||
} // namespace villas
|
||||
|
||||
#ifndef FMT_LEGACY_OSTREAM_FORMATTER
|
||||
template <>
|
||||
class fmt::formatter<villas::fpga::ip::AxisCache>
|
||||
: public fmt::ostream_formatter {};
|
||||
#endif
|
||||
|
|
@ -27,7 +27,7 @@ public:
|
|||
void resetAllRegisters();
|
||||
|
||||
protected:
|
||||
const size_t registerNum = 8;
|
||||
const size_t registerNum = 9;
|
||||
const size_t registerSize = 32;
|
||||
static constexpr char registerMemory[] = "reg0";
|
||||
std::list<MemoryBlockName> getMemoryBlocks() const override {
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ public:
|
|||
ConnectString(std::string &connectString, int maxPortNum = 7);
|
||||
void parseString(std::string &connectString);
|
||||
int portStringToInt(std::string &str) const;
|
||||
void configCrossBar(std::shared_ptr<villas::fpga::Card> card) const;
|
||||
bool configCrossBar(std::shared_ptr<villas::fpga::Card> card) const;
|
||||
bool isBidirectional() const { return bidirectional; };
|
||||
bool isDmaLoopback() const { return srcType == ConnectType::LOOPBACK; };
|
||||
bool isSrcStdin() const { return srcType == ConnectType::DMA; };
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@ set(SOURCES
|
|||
ips/timer.cpp
|
||||
ips/i2c.cpp
|
||||
ips/register.cpp
|
||||
ips/axis_cache.cpp
|
||||
|
||||
ips/rtds2gpu/rtds2gpu.cpp
|
||||
ips/rtds2gpu/xrtds2gpu.c
|
||||
|
|
|
|||
|
|
@ -65,7 +65,10 @@ villasfpga_handle villasfpga_init(const char *configFile) {
|
|||
|
||||
// Configure Crossbar switch
|
||||
const fpga::ConnectString parsedConnectString(connectStr);
|
||||
parsedConnectString.configCrossBar(handle->card);
|
||||
if (!parsedConnectString.configCrossBar(handle->card)) {
|
||||
logger->error("Failed to configure crossbar");
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
return handle;
|
||||
} catch (const RuntimeError &e) {
|
||||
|
|
|
|||
101
fpga/lib/ips/axis_cache.cpp
Normal file
101
fpga/lib/ips/axis_cache.cpp
Normal file
|
|
@ -0,0 +1,101 @@
|
|||
/* Driver for AXI Stream read cache.
|
||||
*
|
||||
* This module is used to lower latency of
|
||||
* a DMA Scatter Gather engine's descriptor fetching. The driver allows for
|
||||
* invalidating the cache.
|
||||
*
|
||||
* Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
|
||||
* SPDX-FileCopyrightText: 2024 Niklas Eiling
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <xilinx/xil_io.h>
|
||||
|
||||
#include <villas/fpga/ips/axis_cache.hpp>
|
||||
|
||||
using namespace villas::fpga::ip;
|
||||
|
||||
#define REGISTER_OUT(NUM) (4 * NUM)
|
||||
|
||||
AxisCache::AxisCache() : Node() {}
|
||||
|
||||
bool AxisCache::init() {
|
||||
invalidate();
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AxisCache::check() {
|
||||
|
||||
logger->debug("Checking register interface: Base address: 0x{:08x}",
|
||||
getBaseAddr(registerMemory));
|
||||
uint32_t buf;
|
||||
|
||||
// We should not change the rate register, because this can lead to hardware fault, so start at 1
|
||||
for (size_t i = 1; i < registerNum; i++) {
|
||||
setRegister(i, static_cast<uint32_t>(0x00FF00FF));
|
||||
}
|
||||
|
||||
for (size_t i = 1; i < registerNum; i++) {
|
||||
if (!getRegister(i, buf)) {
|
||||
logger->error("Failed to read register {}", i);
|
||||
return false;
|
||||
}
|
||||
if (buf != 0x00FF00FF) {
|
||||
logger->error("Register {}: 0x{:08x} != 0x{:08x}", i, buf, i);
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
// Reset Registers
|
||||
resetAllRegisters();
|
||||
|
||||
for (size_t i = 0; i < registerNum; i++) {
|
||||
if (!getRegister(i, buf)) {
|
||||
logger->error("Failed to read register {}", i);
|
||||
return false;
|
||||
}
|
||||
logger->debug("Register {}: 0x{:08x}", i, buf);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void AxisCache::invalidate() {
|
||||
setRegister(0, 1U << 31);
|
||||
logger->info("invalidated AXIS cache.");
|
||||
}
|
||||
|
||||
bool AxisCache::setRegister(size_t reg, uint32_t value) {
|
||||
if (reg >= registerNum) {
|
||||
logger->error("Register index out of range: {}/{}", reg, registerNum);
|
||||
return false;
|
||||
}
|
||||
Xil_Out32(getBaseAddr(registerMemory) + REGISTER_OUT(reg), value);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AxisCache::getRegister(size_t reg, uint32_t &value) {
|
||||
if (reg >= registerNum) {
|
||||
logger->error("Register index out of range: {}/{}", reg, registerNum);
|
||||
return false;
|
||||
}
|
||||
value = Xil_In32(getBaseAddr(registerMemory) + REGISTER_OUT(reg));
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AxisCache::resetRegister(size_t reg) { return setRegister(reg, 0); }
|
||||
|
||||
bool AxisCache::resetAllRegisters() {
|
||||
bool result = true;
|
||||
for (size_t i = 1; i < registerNum; i++) {
|
||||
result &= resetRegister(i);
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
AxisCache::~AxisCache() {}
|
||||
|
||||
static char n[] = "axis_cache";
|
||||
static char d[] = "Register interface VHDL module 'axi_read_cache'";
|
||||
static char v[] = "xilinx.com:module_ref:axi_read_cache:";
|
||||
static CorePlugin<AxisCache, n, d, v> f;
|
||||
|
|
@ -140,6 +140,10 @@ void DinoAdc::configureHardware() {
|
|||
void DinoAdc::setRegisterConfig(std::shared_ptr<Register> reg,
|
||||
double sampleRate) {
|
||||
constexpr double dinoClk = 25e6; // Dino is clocked with 25 Mhz
|
||||
// From the data sheets we can assume an analog delay of 828e-9s
|
||||
// However this will eat into our computation time, so it should be
|
||||
// configurable. Let's assume 0 until we implement this.
|
||||
constexpr double dinoDacDelay = 0; // Delay for DAC to settle
|
||||
constexpr size_t dinoRegisterTimer = 0;
|
||||
constexpr size_t dinoRegisterAdcScale = 1;
|
||||
constexpr size_t dinoRegisterAdcOffset = 2;
|
||||
|
|
@ -147,23 +151,41 @@ void DinoAdc::setRegisterConfig(std::shared_ptr<Register> reg,
|
|||
constexpr size_t dinoRegisterStsActive = 5;
|
||||
constexpr size_t dinoRegisterDacScale = 6;
|
||||
constexpr size_t dinoRegisterDacOffset = 7;
|
||||
constexpr size_t dinoRegisterTimerPreThresh = 8;
|
||||
|
||||
// -1 because the timer counts from 0 to the value set in the register. Should really be fixed in hardware.
|
||||
uint32_t dinoTimerVal = static_cast<uint32_t>(dinoClk / sampleRate) - 1;
|
||||
uint32_t dinoDacDelayCycles = static_cast<uint32_t>(dinoClk * dinoDacDelay);
|
||||
double rateError = dinoClk / (dinoTimerVal + 1) - sampleRate;
|
||||
|
||||
// Timer value for generating ADC trigger signal
|
||||
reg->setRegister(dinoRegisterTimer, dinoTimerVal);
|
||||
|
||||
uint32_t dinoTimerVal = static_cast<uint32_t>(dinoClk / sampleRate);
|
||||
double rateError = dinoClk / dinoTimerVal - sampleRate;
|
||||
reg->setRegister(
|
||||
dinoRegisterTimer,
|
||||
dinoTimerVal); // Timer value for generating ADC trigger signal
|
||||
// The following are calibration values for the ADC and DAC. Scale
|
||||
// sets an factor to be multiplied with the input value. This is the
|
||||
// raw 16 bit ADC value for the ADC and the float value from VILLAS for
|
||||
// the DAC. Offset is a value to be added to the result of the multiplication.
|
||||
// All values are IEE 754 single precision floating point values.
|
||||
// Calibration for ADC filter with C=330pF and R=2,2kOhm
|
||||
// TODO: These values should be read from the FPGA or configured via the configuration file.
|
||||
reg->setRegister(dinoRegisterAdcScale,
|
||||
-0.001615254F); // Scale factor for ADC value
|
||||
reg->setRegister(dinoRegisterAdcOffset, 10.8061F); // Offset for ADC value
|
||||
0.0016874999385349976F); // Scale factor for ADC value
|
||||
reg->setRegister(dinoRegisterAdcOffset,
|
||||
-11.365293957141239F); // Offset for ADC value
|
||||
reg->setRegister(dinoRegisterDacScale,
|
||||
3448.53852516F); // Scale factor for DAC value
|
||||
reg->setRegister(dinoRegisterDacOffset, 32767.5F); // Offset for DAC value
|
||||
3204.7355379027363F); // Scale factor for DAC value
|
||||
reg->setRegister(dinoRegisterDacOffset,
|
||||
32772.159015058445F); // Offset for DAC value
|
||||
reg->setRegister(dinoRegisterDacExternalTrig,
|
||||
(uint32_t)0x0); // External trigger for DAC
|
||||
|
||||
if (dinoTimerVal > dinoDacDelayCycles) {
|
||||
reg->setRegister(dinoRegisterTimerPreThresh,
|
||||
dinoTimerVal - dinoDacDelayCycles);
|
||||
} else {
|
||||
reg->setRegister(dinoRegisterTimerPreThresh, dinoTimerVal);
|
||||
}
|
||||
|
||||
uint32_t rate = reg->getRegister(dinoRegisterTimer);
|
||||
float adcScale = reg->getRegisterFloat(dinoRegisterAdcScale);
|
||||
float adcOffset = reg->getRegisterFloat(dinoRegisterAdcOffset);
|
||||
|
|
@ -171,12 +193,13 @@ void DinoAdc::setRegisterConfig(std::shared_ptr<Register> reg,
|
|||
float dacOffset = reg->getRegisterFloat(dinoRegisterDacOffset);
|
||||
uint32_t dacExternalTrig = reg->getRegister(dinoRegisterDacExternalTrig);
|
||||
uint32_t stsActive = reg->getRegister(dinoRegisterStsActive);
|
||||
uint32_t ratePreThresh = reg->getRegister(dinoRegisterTimerPreThresh);
|
||||
Log::get("Dino")->info(
|
||||
"Check: Register configuration: TimerThresh: {}, Rate-Error: {} Hz, ADC "
|
||||
"Scale: {}, ADC Offset: {}, DAC Scale: {}, DAC Offset: {}, DAC External "
|
||||
"Trig: {:#x}, STS Active: {:#x}",
|
||||
"Trig: {:#x}, STS Active: {:#x}, TimerPreThresh: {}",
|
||||
rate, rateError, adcScale, adcOffset, dacScale, dacOffset,
|
||||
dacExternalTrig, stsActive);
|
||||
dacExternalTrig, stsActive, ratePreThresh);
|
||||
}
|
||||
|
||||
DinoDac::DinoDac() : Dino() {}
|
||||
|
|
|
|||
|
|
@ -65,7 +65,12 @@ bool I2c::check() {
|
|||
if (!initDone) {
|
||||
throw RuntimeError("I2C not initialized");
|
||||
}
|
||||
return getSwitch().selfTest();
|
||||
// Note: While testing the I2C switch here would be great, there might not be a switch connected
|
||||
// Then a call to getSwitch().selfTest() will fail even though the I2C might be working.
|
||||
// The only reliable thing to do is to assume there is nothing connected to the I2C bus and
|
||||
// always return true.
|
||||
// In the future we might check the FMC EEPROM to determine whether the FMC is connected.
|
||||
return 1;
|
||||
}
|
||||
|
||||
bool I2c::stop() { return reset(); }
|
||||
|
|
|
|||
|
|
@ -130,20 +130,20 @@ int fpga::ConnectString::portStringToInt(std::string &str) const {
|
|||
}
|
||||
|
||||
// parses a string like "1->2" or "1<->stdout" and configures the crossbar accordingly
|
||||
void fpga::ConnectString::configCrossBar(
|
||||
bool fpga::ConnectString::configCrossBar(
|
||||
std::shared_ptr<villas::fpga::Card> card) const {
|
||||
|
||||
auto dma = std::dynamic_pointer_cast<fpga::ip::Dma>(
|
||||
card->lookupIp(fpga::Vlnv("xilinx.com:ip:axi_dma:")));
|
||||
if (dma == nullptr) {
|
||||
logger->error("No DMA found on FPGA ");
|
||||
throw std::runtime_error("No DMA found on FPGA");
|
||||
return false;
|
||||
}
|
||||
|
||||
if (isDmaLoopback()) {
|
||||
log->info("Configuring DMA loopback");
|
||||
dma->connectLoopback();
|
||||
return;
|
||||
return true;
|
||||
}
|
||||
|
||||
auto aurora_channels = getAuroraChannels(card);
|
||||
|
|
@ -155,7 +155,7 @@ void fpga::ConnectString::configCrossBar(
|
|||
}
|
||||
|
||||
auto dinoAdc = std::dynamic_pointer_cast<fpga::ip::DinoAdc>(
|
||||
card->lookupIp(fpga::Vlnv("xilinx.com:module_ref:dinoif_fast:")));
|
||||
card->lookupIp(fpga::Vlnv("xilinx.com:module_ref:dinoif_adc:")));
|
||||
if (dinoAdc == nullptr) {
|
||||
logger->warn("No Dino ADC found on FPGA ");
|
||||
}
|
||||
|
|
@ -176,7 +176,12 @@ void fpga::ConnectString::configCrossBar(
|
|||
} else if (aurora_channels->size() > 0) {
|
||||
src = (*aurora_channels)[srcAsInt];
|
||||
} else {
|
||||
throw std::runtime_error("No Aurora channels found on FPGA");
|
||||
logger->error("No Aurora channels found on FPGA");
|
||||
return false;
|
||||
}
|
||||
if (!src) {
|
||||
logger->error("Source does not exist");
|
||||
return false;
|
||||
}
|
||||
|
||||
if (dinoDac && dstType == ConnectType::DINO) {
|
||||
|
|
@ -185,6 +190,13 @@ void fpga::ConnectString::configCrossBar(
|
|||
dest = dma;
|
||||
} else if (aurora_channels->size() > 0) {
|
||||
dest = (*aurora_channels)[dstAsInt];
|
||||
} else {
|
||||
logger->error("No Aurora channels found on FPGA");
|
||||
return false;
|
||||
}
|
||||
if (!dest) {
|
||||
logger->error("Destination does not exist");
|
||||
return false;
|
||||
}
|
||||
|
||||
src->connect(src->getDefaultMasterPort(), dest->getDefaultSlavePort());
|
||||
|
|
@ -197,6 +209,7 @@ void fpga::ConnectString::configCrossBar(
|
|||
}
|
||||
dest->connect(dest->getDefaultMasterPort(), src->getDefaultSlavePort());
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
void fpga::setupColorHandling() {
|
||||
|
|
|
|||
|
|
@ -69,52 +69,6 @@ void writeToDmaFromStdIn(std::shared_ptr<villas::fpga::ip::Dma> dma) {
|
|||
auto writeComp = dma->writeComplete();
|
||||
logger->debug("Wrote {} bytes", writeComp.bytes);
|
||||
}
|
||||
// auto &alloc = villas::HostRam::getAllocator();
|
||||
|
||||
// const std::shared_ptr<villas::MemoryBlock> block[] = {
|
||||
// alloc.allocateBlock(0x200 * sizeof(uint32_t)),
|
||||
// alloc.allocateBlock(0x200 * sizeof(uint32_t))
|
||||
// };
|
||||
// villas::MemoryAccessor<int32_t> mem[] = {*block[0], *block[1]};
|
||||
|
||||
// for (auto b : block) {
|
||||
// dma->makeAccesibleFromVA(b);
|
||||
// }
|
||||
|
||||
// size_t cur = 0, next = 1;
|
||||
// std::ios::sync_with_stdio(false);
|
||||
// std::string line;
|
||||
// bool firstXfer = true;
|
||||
|
||||
// while(true) {
|
||||
// // Read values from stdin
|
||||
|
||||
// std::getline(std::cin, line);
|
||||
// auto values = villas::utils::tokenize(line, ";");
|
||||
|
||||
// size_t i = 0;
|
||||
// for (auto &value: values) {
|
||||
// if (value.empty()) continue;
|
||||
|
||||
// const float number = std::stof(value);
|
||||
// mem[cur][i++] = number;
|
||||
// }
|
||||
|
||||
// // Initiate write transfer
|
||||
// bool state = dma->write(*block[cur], i * sizeof(float));
|
||||
// if (!state)
|
||||
// logger->error("Failed to write to device");
|
||||
|
||||
// if (!firstXfer) {
|
||||
// auto bytesWritten = dma->writeComplete();
|
||||
// logger->debug("Wrote {} bytes", bytesWritten.bytes);
|
||||
// } else {
|
||||
// firstXfer = false;
|
||||
// }
|
||||
|
||||
// cur = next;
|
||||
// next = (next + 1) % (sizeof(mem) / sizeof(mem[0]));
|
||||
// }
|
||||
}
|
||||
|
||||
void readFromDmaToStdOut(
|
||||
|
|
@ -196,9 +150,11 @@ int main(int argc, char *argv[]) {
|
|||
bool dumpGraph = false;
|
||||
app.add_flag("--dump-graph", dumpGraph,
|
||||
"Dumps the graph of memory regions into \"graph.dot\"");
|
||||
bool dumpAuroraChannels = true;
|
||||
bool dumpAuroraChannels = false;
|
||||
app.add_flag("--dump-aurora", dumpAuroraChannels,
|
||||
"Dumps the detected Aurora channels.");
|
||||
double timestep = 10e-3;
|
||||
app.add_option("--timestep", timestep, "Timestep generated in the FPGA");
|
||||
app.parse(argc, argv);
|
||||
|
||||
// Logging setup
|
||||
|
|
@ -230,7 +186,10 @@ int main(int argc, char *argv[]) {
|
|||
// Configure Crossbar switch
|
||||
for (std::string str : connectStr) {
|
||||
const fpga::ConnectString parsedConnectString(str);
|
||||
parsedConnectString.configCrossBar(card);
|
||||
if (!parsedConnectString.configCrossBar(card)) {
|
||||
logger->error("Failed to configure crossbar");
|
||||
return -1;
|
||||
}
|
||||
if (parsedConnectString.isSrcStdin()) {
|
||||
readFromStdin = true;
|
||||
if (parsedConnectString.isBidirectional()) {
|
||||
|
|
@ -249,7 +208,7 @@ int main(int argc, char *argv[]) {
|
|||
|
||||
if (reg != nullptr &&
|
||||
card->lookupIp(fpga::Vlnv("xilinx.com:module_ref:dinoif_fast:"))) {
|
||||
fpga::ip::DinoAdc::setRegisterConfigTimestep(reg, 10e-3);
|
||||
fpga::ip::DinoAdc::setRegisterConfigTimestep(reg, timestep);
|
||||
}
|
||||
|
||||
if (writeToStdout || readFromStdin) {
|
||||
|
|
|
|||
|
|
@ -69,7 +69,10 @@ int FpgaNode::prepare() {
|
|||
// Configure Crossbar switch
|
||||
for (std::string str : connectStrings) {
|
||||
const fpga::ConnectString parsedConnectString(str);
|
||||
parsedConnectString.configCrossBar(card);
|
||||
if (!parsedConnectString.configCrossBar(card)) {
|
||||
logger->error("Failed to configure crossbar");
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
auto reg = std::dynamic_pointer_cast<fpga::ip::Register>(
|
||||
|
|
|
|||
|
|
@ -85,6 +85,12 @@ static const struct {
|
|||
{"unipolar-0.01", UNIPT01VOLTS, 0.0, +0.01},
|
||||
{"unipolar-0.005", UNIPT005VOLTS, 0.0, +0.005}};
|
||||
|
||||
static const struct {
|
||||
const char *name;
|
||||
ScanOption clock_source;
|
||||
} clock_sources[] = {{"internal", (ScanOption)(0 << 4)},
|
||||
{"external", SO_EXTCLOCK}};
|
||||
|
||||
static AiInputMode uldaq_parse_input_mode(const char *str) {
|
||||
for (unsigned i = 0; i < ARRAY_LEN(input_modes); i++) {
|
||||
if (!strcmp(input_modes[i].name, str))
|
||||
|
|
@ -121,6 +127,15 @@ static Range uldaq_parse_range(const char *str) {
|
|||
return (Range)-1;
|
||||
}
|
||||
|
||||
static ScanOption uldaq_parse_clock_source(const char *str) {
|
||||
for (unsigned i = 0; i < ARRAY_LEN(clock_sources); i++) {
|
||||
if (!strcmp(clock_sources[i].name, str))
|
||||
return clock_sources[i].clock_source;
|
||||
}
|
||||
|
||||
return (ScanOption)(0 << 4);
|
||||
}
|
||||
|
||||
static DaqDeviceDescriptor *uldaq_find_device(struct uldaq *u) {
|
||||
DaqDeviceDescriptor *d = nullptr;
|
||||
|
||||
|
|
@ -254,6 +269,7 @@ int villas::node::uldaq_parse(NodeCompat *n, json_t *json) {
|
|||
const char *default_range_str = nullptr;
|
||||
const char *default_input_mode_str = nullptr;
|
||||
const char *interface_type = nullptr;
|
||||
const char *sample_clock_source = nullptr;
|
||||
|
||||
size_t i;
|
||||
json_t *json_signals;
|
||||
|
|
@ -261,10 +277,12 @@ int villas::node::uldaq_parse(NodeCompat *n, json_t *json) {
|
|||
json_error_t err;
|
||||
|
||||
ret = json_unpack_ex(
|
||||
json, &err, 0, "{ s?: s, s?: s, s: { s: o, s: F, s?: s, s?: s } }",
|
||||
json, &err, 0,
|
||||
"{ s?: s, s?: s, s: { s: o, s: F, s?: s, s?: s, s?: s } }",
|
||||
"interface_type", &interface_type, "device_id", &u->device_id, "in",
|
||||
"signals", &json_signals, "sample_rate", &u->in.sample_rate, "range",
|
||||
&default_range_str, "input_mode", &default_input_mode_str);
|
||||
&default_range_str, "input_mode", &default_input_mode_str,
|
||||
"sample_clock_source", &sample_clock_source);
|
||||
if (ret)
|
||||
throw ConfigError(json, err, "node-config-node-uldaq");
|
||||
|
||||
|
|
@ -277,6 +295,15 @@ int villas::node::uldaq_parse(NodeCompat *n, json_t *json) {
|
|||
u->device_interface_type = (DaqDeviceInterface)iftype;
|
||||
}
|
||||
|
||||
if (sample_clock_source) {
|
||||
int clksrc = uldaq_parse_clock_source(sample_clock_source);
|
||||
if (clksrc < 0) {
|
||||
throw ConfigError(json, "node-config-node-uldaq-clock_source",
|
||||
"Invalid clock source type: {}", sample_clock_source);
|
||||
}
|
||||
u->in.scan_options = (ScanOption) (u->in.scan_options | clksrc);
|
||||
}
|
||||
|
||||
if (u->in.queues)
|
||||
delete[] u->in.queues;
|
||||
|
||||
|
|
|
|||
|
|
@ -6,10 +6,12 @@ Author: Steffen Vogel <post@steffenvogel.de>
|
|||
Author: Daniel Krebs <github@daniel-krebs.net>
|
||||
Author: Hatim Kanchwala <hatim@hatimak.me>
|
||||
Author: Pascal Bauer <pascal.bauer@rwth-aachen.de>
|
||||
Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de
|
||||
SPDX-FileCopyrightText: 2017-2022 Steffen Vogel <post@steffenvogel.de>
|
||||
SPDX-FileCopyrightText: 2017-2022 Daniel Krebs <github@daniel-krebs.net>
|
||||
SPDX-FileCopyrightText: 2017-2022 Hatim Kanchwala <hatim@hatimak.me>
|
||||
SPDX-FileCopyrightText: 2023 Pascal Bauer <pascal.bauer@rwth-aachen.de>
|
||||
SPDX-FileCopyrightText: 2024 Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
|
||||
SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
|
|
@ -47,9 +49,11 @@ whitelist = [
|
|||
["xilinx.com", "ip", "axi_iic"],
|
||||
["xilinx.com", "module_ref", "dinoif_fast"],
|
||||
["xilinx.com", "module_ref", "dinoif_fast_nologic"],
|
||||
["xilinx.com", "module_ref", "dinoif_adc"],
|
||||
["xilinx.com", "module_ref", "dinoif_dac"],
|
||||
["xilinx.com", "module_ref", "axi_pcie_intc"],
|
||||
["xilinx.com", "module_ref", "registerif"],
|
||||
["xilinx.com", "module_ref", "axi_read_cache"],
|
||||
["xilinx.com", "hls", "rtds2gpu"],
|
||||
["xilinx.com", "hls", "mem"],
|
||||
["acs.eonerc.rwth-aachen.de", "user", "axi_pcie_intc"],
|
||||
|
|
@ -69,6 +73,7 @@ axi_converter_whitelist = [
|
|||
["xilinx.com", "ip", "axis_register_slice"],
|
||||
["xilinx.com", "ip", "axis_data_fifo"],
|
||||
["xilinx.com", "ip", "floating_point"],
|
||||
["xilinx.com", "module_ref", "prepend_seqnum"],
|
||||
]
|
||||
|
||||
opponent = {
|
||||
|
|
@ -253,14 +258,26 @@ for busif in busifs:
|
|||
ips[switch.get("INSTANCE")]["num_ports"] = int(switch_ports / 2)
|
||||
|
||||
# find interrupt assignments
|
||||
intc = root.find('.//MODULE[@MODTYPE="axi_pcie_intc"]')
|
||||
if intc is not None:
|
||||
intr = intc.xpath('.//PORT[@NAME="intr" and @DIR="I"]')[0]
|
||||
concat = root.xpath(
|
||||
'.//MODULE[@MODTYPE="xlconcat" and .//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(
|
||||
intr.get("SIGNAME")
|
||||
)
|
||||
)[0]
|
||||
|
||||
|
||||
|
||||
# find interrupt assignments
|
||||
intr_controllers = []
|
||||
intr_signals = []
|
||||
|
||||
intc_pcie = root.findall('.//MODULE[@MODTYPE="axi_pcie_intc"]')
|
||||
intc_zynq = root.findall('.//MODULE[@MODTYPE="zynq_ultra_ps_e"]')
|
||||
|
||||
intr_controllers += intc_pcie
|
||||
for intc in intc_pcie:
|
||||
intr_signals.append(intc.xpath('.//PORT[@NAME="intr" and @DIR="I"]')[0].get("SIGNAME"))
|
||||
|
||||
intr_controllers += intc_zynq
|
||||
for intc in intc_zynq:
|
||||
intr_signals.append(intc.xpath('.//PORT[@NAME="pl_ps_irq0" and @DIR="I"]')[0].get("SIGNAME"))
|
||||
|
||||
for intc, intr in zip(intr_controllers, intr_signals):
|
||||
concat = root.xpath('.//MODULE[@MODTYPE="xlconcat" and .//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(intr))[0]
|
||||
ports = concat.xpath('.//PORT[@DIR="I"]')
|
||||
|
||||
for port in ports:
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue