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fix structure of VILLASfpga config files

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This commit is contained in:
Steffen Vogel 2017-08-05 21:03:04 +02:00
parent 57ecb76586
commit 5a21d05c40
2 changed files with 17 additions and 21 deletions
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11
etc/fpga-simple.conf
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@ -44,6 +44,11 @@ fpgas = {
vlnv = "xilinx.com:ip:axis_interconnect:2.1"
baseaddr = 0x0000;
numports = 3;
paths = (
{ in = "dma_0", out = "rtds_0" },
{ in = "rtds_0", out = "dma_0" }
)
},
rtds_0 = {
vlnv = "acs.eonerc.rwth-aachen.de:user:rtds_axis:1.0"
@ -57,12 +62,6 @@ fpgas = {
irq = 0
}
}
/* Configure switch_0 */
paths = (
{ in = "dma_0", out = "rtds_0" },
{ in = "rtds_0", out = "dma_0" }
)
}
}

27
etc/fpga.conf
View file

@ -56,6 +56,18 @@ fpgas = {
vlnv = "xilinx.com:ip:axis_interconnect:2.1"
baseaddr = 0x5000;
num_ports = 10;
paths = (
// { in = "fifo_mm_s_0", out = "fifo_mm_s_0" }, # Loopback fifo_mm_s_0
// { in = "dma_0", out = "dma_0" }, # Loopback dma_0
// { in = "dma_1", out = "dma_1" } # Loopback dma_1
// { in = "rtds_axis_0", out = "fifo_mm_s_0", reverse = true } # Linux <-> RTDS
// { in = "rtds_axis_0", out = "dma_0", reverse = true } # Linux (dma_0) <-> RTDS
{ in = "rtds_axis_0", out = "dma_1", reverse = true } # Linux (dma_1) <-> RTDS
// { in = "rtds_axis_0", out = "fifo_mm_s_0", reverse = true } # Linux (fifo_mm_s_0) <-> RTDS
// { in = "dma_0", out = "hls_dft_0", reverse = true } # DFT <-> Linux
// { in = "rtds_axis_0", out = "hls_dft_0", reverse = true }, # DFT <-> RTDS
)
},
axi_reset_0 = {
vlnv = "xilinx.com:ip:axi_gpio:2.0";
@ -117,21 +129,6 @@ fpgas = {
port = 6;
},
}
############ Switch config ############
# Requires a single IP core with VLNV:
# xilinx.com:ip:axis_interconnect
paths = (
// { in = "fifo_mm_s_0", out = "fifo_mm_s_0" }, # Loopback fifo_mm_s_0
// { in = "dma_0", out = "dma_0" }, # Loopback dma_0
// { in = "dma_1", out = "dma_1" } # Loopback dma_1
// { in = "rtds_axis_0", out = "fifo_mm_s_0", reverse = true } # Linux <-> RTDS
// { in = "rtds_axis_0", out = "dma_0", reverse = true } # Linux (dma_0) <-> RTDS
{ in = "rtds_axis_0", out = "dma_1", reverse = true } # Linux (dma_1) <-> RTDS
// { in = "rtds_axis_0", out = "fifo_mm_s_0", reverse = true } # Linux (fifo_mm_s_0) <-> RTDS
// { in = "dma_0", out = "hls_dft_0", reverse = true } # DFT <-> Linux
// { in = "rtds_axis_0", out = "hls_dft_0", reverse = true }, # DFT <-> RTDS
)
}
}