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lib/ips/intc: change waitForInterrupt() interface

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Return -1 on failure, change type to `int`. int/2 bits should still
be enough to track overflowed interrupts.
This commit is contained in:
daniel-k 2018-01-16 14:47:53 +01:00
parent 82204990cd
commit 80bc9af0e7
2 changed files with 14 additions and 7 deletions
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4
fpga/include/villas/fpga/ips/intc.hpp
View file

@ -56,7 +56,9 @@ public:
int disableInterrupt(IrqPort irq) int disableInterrupt(IrqPort irq)
{ return disableInterrupt(1 << irq.num); } { return disableInterrupt(1 << irq.num); }
uint64_t waitForInterrupt(int irq); int waitForInterrupt(int irq);
int waitForInterrupt(IrqPort irq)
{ return waitForInterrupt(irq.num); }
private: private:
struct Interrupt { struct Interrupt {

17
fpga/lib/ips/intc.cpp
View file

@ -124,7 +124,7 @@ InterruptController::disableInterrupt(InterruptController::IrqMaskType mask)
return true; return true;
} }
uint64_t InterruptController::waitForInterrupt(int irq) int InterruptController::waitForInterrupt(int irq)
{ {
assert(irq < maxIrqs); assert(irq < maxIrqs);
@ -134,21 +134,26 @@ uint64_t InterruptController::waitForInterrupt(int irq)
uint32_t isr, mask = 1 << irq; uint32_t isr, mask = 1 << irq;
do { do {
// poll status register
isr = XIntc_In32(base + XIN_ISR_OFFSET); isr = XIntc_In32(base + XIN_ISR_OFFSET);
pthread_testcancel(); pthread_testcancel();
} while ((isr & mask) != mask); } while ((isr & mask) != mask);
// acknowledge interrupt
XIntc_Out32(base + XIN_IAR_OFFSET, mask); XIntc_Out32(base + XIN_IAR_OFFSET, mask);
// we can only tell that there has been (at least) one interrupt
return 1; return 1;
} }
else { else {
uint64_t cnt; uint64_t count;
ssize_t ret = read(efds[irq], &cnt, sizeof(cnt));
if (ret != sizeof(cnt))
return 0;
return cnt; // block until there has been an interrupt, read number of interrupts
ssize_t ret = read(efds[irq], &count, sizeof(count));
if (ret != sizeof(count))
return -1;
return static_cast<int>(count);
} }
} }