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https://git.rwth-aachen.de/acs/public/villas/node/
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finished FPGA tests
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commit
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1 changed files with 55 additions and 81 deletions
136
src/fpga-tests.c
136
src/fpga-tests.c
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@ -10,15 +10,10 @@
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#include <stdint.h>
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#include <stdbool.h>
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#include <fcntl.h>
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#include <poll.h>
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#include <time.h>
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#include <unistd.h>
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#include <xilinx/xtmrctr.h>
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#include <xilinx/xintc.h>
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#include <xilinx/xllfifo.h>
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#include <xilinx/xaxis_switch.h>
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#include <xilinx/xaxidma.h>
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#include <villas/utils.h>
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#include <villas/nodes/fpga.h>
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@ -59,12 +54,6 @@ int fpga_tests(int argc, char *argv[], struct fpga *f)
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{ "RTDS: tight rtt", fpga_test_rtds_rtt }
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};
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/* We need to overwrite the AXI4-Stream switch configuration from the
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* config file. Therefore we first disable everything here. */
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XAxisScr_RegUpdateDisable(&f->sw->sw.inst);
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XAxisScr_MiPortDisableAll(&f->sw->sw.inst);
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XAxisScr_RegUpdateEnable(&f->sw->sw.inst);
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for (int i = 0; i < ARRAY_LEN(tests); i++) {
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ret = tests[i].func(f);
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@ -91,7 +80,7 @@ int fpga_test_intc(struct fpga *f)
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/* Wait for 8 SW triggered IRQs */
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for (int i = 0; i < 8; i++)
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intc_wait(f->intc, i+8, 0);
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intc_wait(f->intc, i+8);
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/* Check ISR if all SW IRQs have been deliverd */
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isr = XIntc_In32((uintptr_t) f->map + f->intc->baseaddr + XIN_ISR_OFFSET);
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@ -105,11 +94,13 @@ int fpga_test_intc(struct fpga *f)
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int fpga_test_xsg(struct fpga *f)
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{
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struct ip *xsg, *dma;
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struct model_param *p;
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int ret;
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double factor, err = 0;
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struct ip *xsg, *dma;
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struct model_param *p;
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struct dma_mem mem;
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xsg = ip_vlnv_lookup(&f->ips, NULL, "sysgen", "xsg_multiply", NULL);
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dma = ip_vlnv_lookup(&f->ips, "xilinx.com", "ip", "axi_dma", NULL);
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@ -134,8 +125,12 @@ int fpga_test_xsg(struct fpga *f)
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if (ret)
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error("Failed to configure switch");
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float *src = (float *) f->dma;
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float *dst = (float *) f->dma + TEST_LEN;
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ret = dma_alloc(dma, &mem, 0x1000, 0);
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if (ret)
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error("Failed to allocate DMA memory");
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float *src = (float *) mem.base_virt;
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float *dst = (float *) mem.base_virt + 0x800;
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for (int i = 0; i < 6; i++)
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src[i] = 1.1 * (i+1);
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@ -156,6 +151,10 @@ int fpga_test_xsg(struct fpga *f)
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if (ret)
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error("Failed to configure switch");
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ret = dma_free(dma, &mem);
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if (ret)
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error("Failed to release DMA memory");
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return err > 1e-3;
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}
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@ -260,21 +259,29 @@ int fpga_test_fifo(struct fpga *f)
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int fpga_test_dma(struct fpga *f)
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{
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struct ip *bram;
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ssize_t len = 0x100;
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int ret;
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char *src = (char *) f->dma;
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char *dst = (char *) f->dma + len;
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struct dma_mem mem, src, dst;
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list_foreach(struct ip *dma, &f->ips) { INDENT
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if (!ip_vlnv_match(dma, "xilinx.com", "ip", "axi_dma", NULL))
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continue; /* skip non DMA IP cores */
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/* Simple DMA can only transfer up to 4 kb due to
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* PCIe page size burst limitation */
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ssize_t len = dma->dma.inst.HasSg ? 64 << 20 : 1 << 2;
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ret = dma_alloc(dma, &mem, 2 * len, 0);
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if (ret)
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return -1;
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ret = dma_mem_split(&mem, &src, &dst);
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if (ret)
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return -1;
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/* Get new random data */
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ret = read_random(src, len);
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ret = read_random(src.base_virt, len);
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if (ret)
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error("Failed to get random data");
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serror("Failed to get random data");
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int irq_mm2s = dma->irq;
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int irq_s2mm = dma->irq + 1;
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@ -287,47 +294,12 @@ int fpga_test_dma(struct fpga *f)
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if (ret)
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error("Failed to configure switch");
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XAxiDma_Reset(&dma->dma.inst);
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if (dma->dma.inst.HasSg) {
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/* Init BD rings */
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bram = ip_vlnv_lookup(&f->ips, "xilinx.com", "ip", "axi_bram_ctrl", NULL);
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if (!bram)
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return -3;
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/* Memory for buffer descriptors */
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struct dma_mem bd = {
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.base_virt = (uintptr_t) f->map + bram->baseaddr,
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.base_phys = bram->baseaddr,
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.len = bram->bram.size
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};
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ret = dma_init_rings(dma, &bd);
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if (ret)
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return -4;
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}
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/* Start transfer */
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ret = dma_read(dma, dst, len);
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ret = dma_ping_pong(dma, src.base_phys, dst.base_phys, dst.len);
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if (ret)
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error("Failed to start DMA read: %d", ret);
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error("DMA ping pong failed");
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ret = dma_write(dma, src, len);
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if (ret)
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error("Failed to start DMA write: %d", ret);
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size_t recvlen;
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ret = dma_read_complete(dma, NULL, &recvlen);
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if (ret)
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error("Failed to complete DMA read");
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ret = dma_write_complete(dma, NULL, NULL);
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if (ret)
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error("Failed to complete DMA write");
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info("recvlen = %#zx", recvlen);
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ret = memcmp(src, dst, len);
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ret = memcmp(src.base_virt, dst.base_virt, src.len);
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info("DMA %s (%s): %s", dma->name, dma->dma.inst.HasSg ? "scatter-gather" : "simple", ret ? RED("failed") : GRN("passed"));
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ret = intc_disable(f->intc, (1 << irq_mm2s) | (1 << irq_s2mm));
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if (ret)
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error("Failed to disable interrupt");
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ret = dma_free(dma, &mem);
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if (ret)
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error("Failed to release DMA memory");
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}
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return ret;
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XTmrCtr_SetResetValue(xtmr, 0, AXI_HZ / 125);
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XTmrCtr_Start(xtmr, 0);
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struct pollfd pfd = {
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.fd = f->vd.msi_efds[tmr->irq],
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.events = POLLIN
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};
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uint64_t counter = intc_wait(f->intc, tmr->irq);
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info("Got IRQ: counter = %ju", counter);
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ret = poll(&pfd, 1, 1000);
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if (ret == 1) {
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uint64_t counter = intc_wait(f->intc, tmr->irq, 0);
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info("Got IRQ: counter = %ju", counter);
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if (counter == 1)
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return 0;
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else
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warn("Counter was not 1");
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}
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if (counter == 1)
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return 0;
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else
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warn("Counter was not 1");
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intc_disable(f->intc, (1 << tmr->irq));
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if (ret)
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@ -390,7 +357,10 @@ int fpga_test_rtds_rtt(struct fpga *f)
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{
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int ret;
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struct ip *dma, *rtds;
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struct dma_mem buf;
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size_t recvlen;
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/* Get IP cores */
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rtds = ip_vlnv_lookup(&f->ips, "acs.eonerc.rwth-aachen.de", "user", "rtds_axis", NULL);
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dma = list_lookup(&f->ips, "dma_1");
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if (ret)
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error("Failed to configure switch");
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size_t len = 0x100;
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size_t recvlen;
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char *buf = f->dma;
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ret = dma_alloc(dma, &buf, 0x100, 0);
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if (ret)
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error("Failed to allocate DMA memory");
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while (1) {
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ret = dma_read(dma, buf, len);
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ret = dma_read(dma, buf.base_phys, buf.len);
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if (ret)
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error("Failed to start DMA read: %d", ret);
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if (ret)
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error("Failed to complete DMA read: %d", ret);
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ret = dma_write(dma, buf, recvlen);
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ret = dma_write(dma, buf.base_phys, recvlen);
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if (ret)
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error("Failed to start DMA write: %d", ret);
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ret = switch_disconnect(f->sw, dma, rtds);
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if (ret)
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error("Failed to configure switch");
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ret = dma_free(dma, &buf);
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if (ret)
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error("Failed to release DMA memory");
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return 0;
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}
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